aarch64: Reimplement vshrn_high_n* intrinsics using builtins
This patch reimplements the vshrn_high_n* intrinsics that generate the SHRN2 instruction. It is a vec_concat of the narrowing shift with the bottom part of the destination register, so we need a little-endian and a big-endian version and an expander to pick between them. gcc/ChangeLog: * config/aarch64/aarch64-simd-builtins.def (shrn2): Define builtin. * config/aarch64/aarch64-simd.md (aarch64_shrn2<mode>_insn_le): Define. (aarch64_shrn2<mode>_insn_be): Likewise. (aarch64_shrn2<mode>): Likewise. * config/aarch64/arm_neon.h (vshrn_high_n_s16): Reimlplement using builtins. (vshrn_high_n_s32): Likewise. (vshrn_high_n_s64): Likewise. (vshrn_high_n_u16): Likewise. (vshrn_high_n_u32): Likewise. (vshrn_high_n_u64): Likewise.
This commit is contained in:
Kyrylo Tkachov
parent
fdb904a182
commit
d61ca09ec9
3 changed files with 85 additions and 84 deletions
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@ -191,6 +191,9 @@
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/* Implemented by aarch64_shrn<mode>". */
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BUILTIN_VQN (SHIFTIMM, shrn, 0, NONE)
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/* Implemented by aarch64_shrn2<mode>. */
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BUILTIN_VQN (SHIFTACC, shrn2, 0, NONE)
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/* Implemented by aarch64_<su>mlsl<mode>. */
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BUILTIN_VD_BHSI (TERNOP, smlsl, 0, NONE)
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BUILTIN_VD_BHSI (TERNOPU, umlsl, 0, NONE)
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@ -1728,6 +1728,49 @@
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}
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)
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(define_insn "aarch64_shrn2<mode>_insn_le"
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[(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
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(vec_concat:<VNARROWQ2>
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(match_operand:<VNARROWQ> 1 "register_operand" "0")
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(truncate:<VNARROWQ>
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(lshiftrt:VQN (match_operand:VQN 2 "register_operand" "w")
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(match_operand:VQN 3 "aarch64_simd_rshift_imm")))))]
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"TARGET_SIMD && !BYTES_BIG_ENDIAN"
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"shrn2\\t%0.<V2ntype>, %2.<Vtype>, %3"
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[(set_attr "type" "neon_shift_imm_narrow_q")]
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)
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(define_insn "aarch64_shrn2<mode>_insn_be"
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[(set (match_operand:<VNARROWQ2> 0 "register_operand" "=w")
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(vec_concat:<VNARROWQ2>
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(truncate:<VNARROWQ>
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(lshiftrt:VQN (match_operand:VQN 2 "register_operand" "w")
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(match_operand:VQN 3 "aarch64_simd_rshift_imm")))
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(match_operand:<VNARROWQ> 1 "register_operand" "0")))]
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"TARGET_SIMD && BYTES_BIG_ENDIAN"
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"shrn2\\t%0.<V2ntype>, %2.<Vtype>, %3"
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[(set_attr "type" "neon_shift_imm_narrow_q")]
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)
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(define_expand "aarch64_shrn2<mode>"
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[(match_operand:<VNARROWQ2> 0 "register_operand")
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(match_operand:<VNARROWQ> 1 "register_operand")
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(match_operand:VQN 2 "register_operand")
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(match_operand:SI 3 "aarch64_simd_shift_imm_offset_<vn_mode>")]
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"TARGET_SIMD"
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{
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operands[3] = aarch64_simd_gen_const_vector_dup (<MODE>mode,
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INTVAL (operands[3]));
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if (BYTES_BIG_ENDIAN)
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emit_insn (gen_aarch64_shrn2<mode>_insn_be (operands[0], operands[1],
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operands[2], operands[3]));
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else
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emit_insn (gen_aarch64_shrn2<mode>_insn_le (operands[0], operands[1],
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operands[2], operands[3]));
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DONE;
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}
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)
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;; For quads.
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@ -9809,95 +9809,50 @@ vrsqrteq_u32 (uint32x4_t __a)
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return __result;
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}
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#define vshrn_high_n_s16(a, b, c) \
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__extension__ \
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({ \
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int16x8_t b_ = (b); \
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int8x8_t a_ = (a); \
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int8x16_t result = vcombine_s8 \
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(a_, vcreate_s8 \
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(__AARCH64_UINT64_C (0x0))); \
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__asm__ ("shrn2 %0.16b,%1.8h,#%2" \
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: "+w"(result) \
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: "w"(b_), "i"(c) \
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: /* No clobbers */); \
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result; \
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})
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__extension__ extern __inline int8x16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vshrn_high_n_s16 (int8x8_t __a, int16x8_t __b, const int __c)
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{
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return __builtin_aarch64_shrn2v8hi (__a, __b, __c);
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}
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#define vshrn_high_n_s32(a, b, c) \
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__extension__ \
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({ \
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int32x4_t b_ = (b); \
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int16x4_t a_ = (a); \
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int16x8_t result = vcombine_s16 \
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(a_, vcreate_s16 \
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(__AARCH64_UINT64_C (0x0))); \
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__asm__ ("shrn2 %0.8h,%1.4s,#%2" \
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: "+w"(result) \
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: "w"(b_), "i"(c) \
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: /* No clobbers */); \
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result; \
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})
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__extension__ extern __inline int16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vshrn_high_n_s32 (int16x4_t __a, int32x4_t __b, const int __c)
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{
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return __builtin_aarch64_shrn2v4si (__a, __b, __c);
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}
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#define vshrn_high_n_s64(a, b, c) \
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__extension__ \
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({ \
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int64x2_t b_ = (b); \
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int32x2_t a_ = (a); \
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int32x4_t result = vcombine_s32 \
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(a_, vcreate_s32 \
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(__AARCH64_UINT64_C (0x0))); \
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__asm__ ("shrn2 %0.4s,%1.2d,#%2" \
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: "+w"(result) \
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: "w"(b_), "i"(c) \
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: /* No clobbers */); \
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result; \
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})
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__extension__ extern __inline int32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vshrn_high_n_s64 (int32x2_t __a, int64x2_t __b, const int __c)
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{
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return __builtin_aarch64_shrn2v2di (__a, __b, __c);
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}
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#define vshrn_high_n_u16(a, b, c) \
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__extension__ \
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({ \
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uint16x8_t b_ = (b); \
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uint8x8_t a_ = (a); \
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uint8x16_t result = vcombine_u8 \
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(a_, vcreate_u8 \
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(__AARCH64_UINT64_C (0x0))); \
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__asm__ ("shrn2 %0.16b,%1.8h,#%2" \
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: "+w"(result) \
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: "w"(b_), "i"(c) \
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: /* No clobbers */); \
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result; \
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})
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__extension__ extern __inline uint8x16_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vshrn_high_n_u16 (uint8x8_t __a, uint16x8_t __b, const int __c)
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{
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return (uint8x16_t)
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__builtin_aarch64_shrn2v8hi ((int8x8_t) __a, (int16x8_t) __b, __c);
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}
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#define vshrn_high_n_u32(a, b, c) \
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__extension__ \
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({ \
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uint32x4_t b_ = (b); \
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uint16x4_t a_ = (a); \
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uint16x8_t result = vcombine_u16 \
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(a_, vcreate_u16 \
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(__AARCH64_UINT64_C (0x0))); \
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__asm__ ("shrn2 %0.8h,%1.4s,#%2" \
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: "+w"(result) \
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: "w"(b_), "i"(c) \
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: /* No clobbers */); \
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result; \
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})
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__extension__ extern __inline uint16x8_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vshrn_high_n_u32 (uint16x4_t __a, uint32x4_t __b, const int __c)
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{
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return (uint16x8_t)
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__builtin_aarch64_shrn2v4si ((int16x4_t) __a, (int32x4_t) __b, __c);
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}
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#define vshrn_high_n_u64(a, b, c) \
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__extension__ \
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({ \
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uint64x2_t b_ = (b); \
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uint32x2_t a_ = (a); \
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uint32x4_t result = vcombine_u32 \
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(a_, vcreate_u32 \
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(__AARCH64_UINT64_C (0x0))); \
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__asm__ ("shrn2 %0.4s,%1.2d,#%2" \
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: "+w"(result) \
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: "w"(b_), "i"(c) \
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: /* No clobbers */); \
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result; \
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})
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__extension__ extern __inline uint32x4_t
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__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
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vshrn_high_n_u64 (uint32x2_t __a, uint64x2_t __b, const int __c)
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{
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return (uint32x4_t)
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__builtin_aarch64_shrn2v2di ((int32x2_t) __a, (int64x2_t) __b, __c);
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}
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#define vsli_n_p8(a, b, c) \
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__extension__ \
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