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Document AMD btver2

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Venkataramanan Kumar 2012-08-05 12:29:52 +00:00 • committed by Venkataramanan Kumar
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gcc/ChangeLog
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@ -1,3 +1,8 @@
2012-08-05 Venkataramanan Kumar <venkataramanan.kumar@amd.com>
* doc/invoke.texi: Document AMD btver2.
* doc/extend.texi: Document AMD btver1 and btver2.
2012-08-04 Sandra Loosemore <sandra@codesourcery.com>
Richard Sandiford <rdsandiford@googlemail.com>

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gcc/doc/extend.texi
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@ -9560,6 +9560,9 @@ AMD family 10h Shanghai CPU.
@item istanbul
AMD family 10h Istanbul CPU.
@item btver1
AMD family 14h CPU.
@item amdfam15h
AMD family 15h CPU.
@ -9568,6 +9571,9 @@ AMD family 15h Bulldozer version 1.
@item bdver2
AMD family 15h Bulldozer version 2.
@item btver2
AMD family 16h CPU.
@end table
Here is an example:

5
gcc/doc/invoke.texi
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@ -13304,6 +13304,11 @@ CPUs based on AMD Family 14h cores with x86-64 instruction set support. (This
supersets MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, CX16, ABM and 64-bit
instruction set extensions.)
@item btver2
CPUs based on AMD Family 16h cores with x86-64 instruction set support. This
includes MOVBE, F16C, BMI, AVX, PCL_MUL, AES, SSE4.2, SSE4.1, CX16, ABM,
SSE4A, SSSE3, SSE3, SSE2, SSE, MMX and 64-bit instruction set extensions.
@item winchip-c6
IDT WinChip C6 CPU, dealt in same way as i486 with additional MMX instruction
set support.