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arm.c: Use CONST_INT_P...

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2012-09-06  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

	* config/arm/arm.c: Use CONST_INT_P, CONST_DOUBLE_P, REG_P, MEM_P,
	LABEL_P, JUMP_P, CALL_P, NOTE_P, BARRIER_P consistently.
	* config/arm/arm.h: Use REG_P, MEM_P consistently.
	* config/arm/arm.md: Use CONST_INT_P, REG_P, MEM_P, CONST_DOUBLE_P
	consistently.
	* config/arm/neon.md: Use REG_P consistently.
	* config/arm/predicates.md: Use CONST_INT_P, REG_P, MEM_P
	consistently.
	* config/arm/thumb2.md: Use CONST_INT_P, REG_P consistently.
	* config/arm/vec-common.md: Use REG_P consistently.

From-SVN: r191034
This commit is contained in:
Kyrylo Tkachov 2012-09-06 17:11:18 +00:00 • committed by Richard Earnshaw
parent c2b3ec18a4
commit d435a4be2a
8 changed files with 392 additions and 382 deletions
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13
gcc/ChangeLog
View file

@ -1,3 +1,16 @@
2012-09-06 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c: Use CONST_INT_P, CONST_DOUBLE_P, REG_P, MEM_P,
LABEL_P, JUMP_P, CALL_P, NOTE_P, BARRIER_P consistently.
* config/arm/arm.h: Use REG_P, MEM_P consistently.
* config/arm/arm.md: Use CONST_INT_P, REG_P, MEM_P, CONST_DOUBLE_P
consistently.
* config/arm/neon.md: Use REG_P consistently.
* config/arm/predicates.md: Use CONST_INT_P, REG_P, MEM_P
consistently.
* config/arm/thumb2.md: Use CONST_INT_P, REG_P consistently.
* config/arm/vec-common.md: Use REG_P consistently.
2012-09-06 Richard Guenther <rguenther@suse.de>
PR tree-optimization/54498

498
gcc/config/arm/arm.c
View file

File diff suppressed because it is too large Load diff

8
gcc/config/arm/arm.h
View file

@ -1262,8 +1262,8 @@ enum reg_class
&& CONSTANT_P (X)) \
? GENERAL_REGS : \
(((MODE) == HImode && ! arm_arch4 \
&& (GET_CODE (X) == MEM \
|| ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \
&& (MEM_P (X) \
|| ((REG_P (X) || GET_CODE (X) == SUBREG) \
&& true_regnum (X) == -1))) \
? GENERAL_REGS : NO_REGS) \
: THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X)))
@ -1909,10 +1909,10 @@ enum arm_auto_incmodes
REG_OK_FOR_INDEX_P (X)
#define ARM_BASE_REGISTER_RTX_P(X) \
(GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X))
(REG_P (X) && ARM_REG_OK_FOR_BASE_P (X))
#define ARM_INDEX_REGISTER_RTX_P(X) \
(GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X))
(REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X))
/* Specify the machine mode that this machine uses
for the index in the tablejump instruction. */

207
gcc/config/arm/arm.md
View file

@ -607,9 +607,9 @@
"
if (TARGET_THUMB1)
{
if (GET_CODE (operands[1]) != REG)
if (!REG_P (operands[1]))
operands[1] = force_reg (DImode, operands[1]);
if (GET_CODE (operands[2]) != REG)
if (!REG_P (operands[2]))
operands[2] = force_reg (DImode, operands[2]);
}
"
@ -716,7 +716,7 @@
(match_operand:SI 2 "reg_or_int_operand" "")))]
"TARGET_EITHER"
"
if (TARGET_32BIT && GET_CODE (operands[2]) == CONST_INT)
if (TARGET_32BIT && CONST_INT_P (operands[2]))
{
arm_split_constant (PLUS, SImode, NULL_RTX,
INTVAL (operands[2]), operands[0], operands[1],
@ -764,7 +764,7 @@
subw%?\\t%0, %1, #%n2
#"
"TARGET_32BIT
&& GET_CODE (operands[2]) == CONST_INT
&& CONST_INT_P (operands[2])
&& !const_ok_for_op (INTVAL (operands[2]), PLUS)
&& (reload_completed || !arm_eliminable_register (operands[1]))"
[(clobber (const_int 0))]
@ -799,7 +799,7 @@
\"#\"
};
if ((which_alternative == 2 || which_alternative == 6)
&& GET_CODE (operands[2]) == CONST_INT
&& CONST_INT_P (operands[2])
&& INTVAL (operands[2]) < 0)
return \"sub\\t%0, %1, #%n2\";
return asms[which_alternative];
@ -1111,9 +1111,9 @@
"
if (TARGET_THUMB1)
{
if (GET_CODE (operands[1]) != REG)
if (!REG_P (operands[1]))
operands[1] = force_reg (DImode, operands[1]);
if (GET_CODE (operands[2]) != REG)
if (!REG_P (operands[2]))
operands[2] = force_reg (DImode, operands[2]);
}
"
@ -1207,7 +1207,7 @@
(match_operand:SI 2 "s_register_operand" "")))]
"TARGET_EITHER"
"
if (GET_CODE (operands[1]) == CONST_INT)
if (CONST_INT_P (operands[1]))
{
if (TARGET_32BIT)
{
@ -1242,7 +1242,7 @@
sub%?\\t%0, %1, %2
sub%?\\t%0, %1, %2
#"
"&& (GET_CODE (operands[1]) == CONST_INT
"&& (CONST_INT_P (operands[1])
&& !const_ok_for_arm (INTVAL (operands[1])))"
[(clobber (const_int 0))]
"
@ -2097,7 +2097,7 @@
"
if (TARGET_32BIT)
{
if (GET_CODE (operands[2]) == CONST_INT)
if (CONST_INT_P (operands[2]))
{
if (INTVAL (operands[2]) == 255 && arm_arch6)
{
@ -2116,7 +2116,7 @@
}
else /* TARGET_THUMB1 */
{
if (GET_CODE (operands[2]) != CONST_INT)
if (!CONST_INT_P (operands[2]))
{
rtx tmp = force_reg (SImode, operands[2]);
if (rtx_equal_p (operands[0], operands[1]))
@ -2179,7 +2179,7 @@
bic%?\\t%0, %1, #%B2
#"
"TARGET_32BIT
&& GET_CODE (operands[2]) == CONST_INT
&& CONST_INT_P (operands[2])
&& !(const_ok_for_arm (INTVAL (operands[2]))
|| const_ok_for_arm (~INTVAL (operands[2])))"
[(clobber (const_int 0))]
@ -2512,7 +2512,7 @@
{
bool use_bfi = TRUE;
if (GET_CODE (operands[3]) == CONST_INT)
if (CONST_INT_P (operands[3]))
{
HOST_WIDE_INT val = INTVAL (operands[3]) & mask;
@ -2530,7 +2530,7 @@
if (use_bfi)
{
if (GET_CODE (operands[3]) != REG)
if (!REG_P (operands[3]))
operands[3] = force_reg (SImode, operands[3]);
emit_insn (gen_insv_t2 (operands[0], operands[1], operands[2],
@ -2558,7 +2558,7 @@
else
subtarget = target;
if (GET_CODE (operands[3]) == CONST_INT)
if (CONST_INT_P (operands[3]))
{
/* Since we are inserting a known constant, we may be able to
reduce the number of bits that we have to clear so that
@ -2625,7 +2625,7 @@
/* Mask out any bits in operand[3] that are not needed. */
emit_insn (gen_andsi3 (op1, operands[3], op0));
if (GET_CODE (op0) == CONST_INT
if (CONST_INT_P (op0)
&& (const_ok_for_arm (mask << start_bit)
|| const_ok_for_arm (~(mask << start_bit))))
{
@ -2634,7 +2634,7 @@
}
else
{
if (GET_CODE (op0) == CONST_INT)
if (CONST_INT_P (op0))
{
rtx tmp = gen_reg_rtx (SImode);
@ -2871,7 +2871,7 @@
(match_operand:SI 2 "reg_or_int_operand" "")))]
"TARGET_EITHER"
"
if (GET_CODE (operands[2]) == CONST_INT)
if (CONST_INT_P (operands[2]))
{
if (TARGET_32BIT)
{
@ -2905,7 +2905,7 @@
orn%?\\t%0, %1, #%B2
#"
"TARGET_32BIT
&& GET_CODE (operands[2]) == CONST_INT
&& CONST_INT_P (operands[2])
&& !(const_ok_for_arm (INTVAL (operands[2]))
|| (TARGET_THUMB2 && const_ok_for_arm (~INTVAL (operands[2]))))"
[(clobber (const_int 0))]
@ -3010,7 +3010,7 @@
(xor:SI (match_operand:SI 1 "s_register_operand" "")
(match_operand:SI 2 "reg_or_int_operand" "")))]
"TARGET_EITHER"
"if (GET_CODE (operands[2]) == CONST_INT)
"if (CONST_INT_P (operands[2]))
{
if (TARGET_32BIT)
{
@ -3042,7 +3042,7 @@
eor%?\\t%0, %1, %2
#"
"TARGET_32BIT
&& GET_CODE (operands[2]) == CONST_INT
&& CONST_INT_P (operands[2])
&& !const_ok_for_arm (INTVAL (operands[2]))"
[(clobber (const_int 0))]
{
@ -3542,7 +3542,7 @@
(match_operand:SI 2 "arm_rhs_operand" "")))]
"TARGET_EITHER"
"
if (GET_CODE (operands[2]) == CONST_INT
if (CONST_INT_P (operands[2])
&& ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
{
emit_insn (gen_movsi (operands[0], const0_rtx));
@ -3617,7 +3617,7 @@
(match_operand:SI 2 "arm_rhs_operand" "")))]
"TARGET_EITHER"
"
if (GET_CODE (operands[2]) == CONST_INT
if (CONST_INT_P (operands[2])
&& ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
operands[2] = GEN_INT (31);
"
@ -3689,7 +3689,7 @@
(match_operand:SI 2 "arm_rhs_operand" "")))]
"TARGET_EITHER"
"
if (GET_CODE (operands[2]) == CONST_INT
if (CONST_INT_P (operands[2])
&& ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
{
emit_insn (gen_movsi (operands[0], const0_rtx));
@ -3713,7 +3713,7 @@
(match_operand:SI 2 "reg_or_int_operand" "")))]
"TARGET_32BIT"
"
if (GET_CODE (operands[2]) == CONST_INT)
if (CONST_INT_P (operands[2]))
operands[2] = GEN_INT ((32 - INTVAL (operands[2])) % 32);
else
{
@ -3732,13 +3732,13 @@
"
if (TARGET_32BIT)
{
if (GET_CODE (operands[2]) == CONST_INT
if (CONST_INT_P (operands[2])
&& ((unsigned HOST_WIDE_INT) INTVAL (operands[2])) > 31)
operands[2] = GEN_INT (INTVAL (operands[2]) % 32);
}
else /* TARGET_THUMB1 */
{
if (GET_CODE (operands [2]) == CONST_INT)
if (CONST_INT_P (operands [2]))
operands [2] = force_reg (SImode, operands[2]);
}
"
@ -4595,7 +4595,7 @@
rtx a = XEXP (mem, 0);
/* This can happen due to bugs in reload. */
if (GET_CODE (a) == REG && REGNO (a) == SP_REGNUM)
if (REG_P (a) && REGNO (a) == SP_REGNUM)
{
rtx ops[2];
ops[0] = operands[0];
@ -4653,7 +4653,7 @@
(zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
"TARGET_EITHER"
{
if (TARGET_ARM && !arm_arch6 && GET_CODE (operands[1]) != MEM)
if (TARGET_ARM && !arm_arch6 && !MEM_P (operands[1]))
{
emit_insn (gen_andsi3 (operands[0],
gen_lowpart (SImode, operands[1]),
@ -4746,7 +4746,7 @@
[(set (match_operand:SI 0 "s_register_operand" "")
(zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 0)))
(clobber (match_operand:SI 2 "s_register_operand" ""))]
"TARGET_32BIT && (GET_CODE (operands[1]) != MEM) && ! BYTES_BIG_ENDIAN"
"TARGET_32BIT && (!MEM_P (operands[1])) && ! BYTES_BIG_ENDIAN"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))]
""
@ -4756,7 +4756,7 @@
[(set (match_operand:SI 0 "s_register_operand" "")
(zero_extend:SI (subreg:QI (match_operand:SI 1 "" "") 3)))
(clobber (match_operand:SI 2 "s_register_operand" ""))]
"TARGET_32BIT && (GET_CODE (operands[1]) != MEM) && BYTES_BIG_ENDIAN"
"TARGET_32BIT && (!MEM_P (operands[1])) && BYTES_BIG_ENDIAN"
[(set (match_dup 2) (match_dup 1))
(set (match_dup 0) (and:SI (match_dup 2) (const_int 255)))]
""
@ -4872,10 +4872,10 @@
rtx b = XEXP (mem, 1);
if (GET_CODE (a) == LABEL_REF
&& GET_CODE (b) == CONST_INT)
&& CONST_INT_P (b))
return \"ldr\\t%0, %1\";
if (GET_CODE (b) == REG)
if (REG_P (b))
return \"ldrsh\\t%0, %1\";
ops[1] = a;
@ -4887,7 +4887,7 @@
ops[2] = const0_rtx;
}
gcc_assert (GET_CODE (ops[1]) == REG);
gcc_assert (REG_P (ops[1]));
ops[0] = operands[0];
if (reg_mentioned_p (operands[2], ops[1]))
@ -4998,7 +4998,7 @@
"TARGET_ARM"
"
{
if (arm_arch4 && GET_CODE (operands[1]) == MEM)
if (arm_arch4 && MEM_P (operands[1]))
{
emit_insn (gen_rtx_SET (VOIDmode,
operands[0],
@ -5235,11 +5235,11 @@
;;{
;; rtx insn;
;;
;; if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
;; if (MEM_P (operands[0]) && MEM_P (operands[1]))
;; operands[1] = copy_to_reg (operands[1]);
;; if (GET_CODE (operands[0]) == MEM)
;; if (MEM_P (operands[0]))
;; insn = gen_storeti (XEXP (operands[0], 0), operands[1]);
;; else if (GET_CODE (operands[1]) == MEM)
;; else if (MEM_P (operands[1]))
;; insn = gen_loadti (operands[0], XEXP (operands[1], 0));
;; else
;; FAIL;
@ -5280,7 +5280,7 @@
"
if (can_create_pseudo_p ())
{
if (GET_CODE (operands[0]) != REG)
if (!REG_P (operands[0]))
operands[1] = force_reg (DImode, operands[1]);
}
"
@ -5462,10 +5462,10 @@
if (TARGET_32BIT)
{
/* Everything except mem = const or mem = mem can be done easily. */
if (GET_CODE (operands[0]) == MEM)
if (MEM_P (operands[0]))
operands[1] = force_reg (SImode, operands[1]);
if (arm_general_register_operand (operands[0], SImode)
&& GET_CODE (operands[1]) == CONST_INT
&& CONST_INT_P (operands[1])
&& !(const_ok_for_arm (INTVAL (operands[1]))
|| const_ok_for_arm (~INTVAL (operands[1]))))
{
@ -5479,7 +5479,7 @@
{
if (can_create_pseudo_p ())
{
if (GET_CODE (operands[0]) != REG)
if (!REG_P (operands[0]))
operands[1] = force_reg (SImode, operands[1]);
}
}
@ -5886,7 +5886,7 @@
rtx addr = XEXP (op1, 0);
enum rtx_code code = GET_CODE (addr);
if ((code == PLUS && GET_CODE (XEXP (addr, 1)) != CONST_INT)
if ((code == PLUS && !CONST_INT_P (XEXP (addr, 1)))
|| code == MINUS)
op1 = replace_equiv_address (operands[1], force_reg (SImode, addr));
@ -5911,7 +5911,7 @@
rtx addr = XEXP (op1, 0);
enum rtx_code code = GET_CODE (addr);
if ((code == PLUS && GET_CODE (XEXP (addr, 1)) != CONST_INT)
if ((code == PLUS && !CONST_INT_P (XEXP (addr, 1)))
|| code == MINUS)
op1 = replace_equiv_address (op1, force_reg (SImode, addr));
@ -5937,7 +5937,7 @@
rtx op0 = operands[0];
enum rtx_code code = GET_CODE (addr);
if ((code == PLUS && GET_CODE (XEXP (addr, 1)) != CONST_INT)
if ((code == PLUS && !CONST_INT_P (XEXP (addr, 1)))
|| code == MINUS)
op0 = replace_equiv_address (op0, force_reg (SImode, addr));
@ -5991,18 +5991,18 @@
{
if (can_create_pseudo_p ())
{
if (GET_CODE (operands[0]) == MEM)
if (MEM_P (operands[0]))
{
if (arm_arch4)
{
emit_insn (gen_storehi_single_op (operands[0], operands[1]));
DONE;
}
if (GET_CODE (operands[1]) == CONST_INT)
if (CONST_INT_P (operands[1]))
emit_insn (gen_storeinthi (operands[0], operands[1]));
else
{
if (GET_CODE (operands[1]) == MEM)
if (MEM_P (operands[1]))
operands[1] = force_reg (HImode, operands[1]);
if (BYTES_BIG_ENDIAN)
emit_insn (gen_storehi_bigend (operands[1], operands[0]));
@ -6012,7 +6012,7 @@
DONE;
}
/* Sign extend a constant, and keep it in an SImode reg. */
else if (GET_CODE (operands[1]) == CONST_INT)
else if (CONST_INT_P (operands[1]))
{
rtx reg = gen_reg_rtx (SImode);
HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffff;
@ -6034,7 +6034,7 @@
operands[1] = gen_lowpart (HImode, reg);
}
else if (arm_arch4 && optimize && can_create_pseudo_p ()
&& GET_CODE (operands[1]) == MEM)
&& MEM_P (operands[1]))
{
rtx reg = gen_reg_rtx (SImode);
@ -6043,18 +6043,17 @@
}
else if (!arm_arch4)
{
if (GET_CODE (operands[1]) == MEM)
if (MEM_P (operands[1]))
{
rtx base;
rtx offset = const0_rtx;
rtx reg = gen_reg_rtx (SImode);
if ((GET_CODE (base = XEXP (operands[1], 0)) == REG
if ((REG_P (base = XEXP (operands[1], 0))
|| (GET_CODE (base) == PLUS
&& (GET_CODE (offset = XEXP (base, 1))
== CONST_INT)
&& (CONST_INT_P (offset = XEXP (base, 1)))
&& ((INTVAL(offset) & 1) != 1)
&& GET_CODE (base = XEXP (base, 0)) == REG))
&& REG_P (base = XEXP (base, 0))))
&& REGNO_POINTER_ALIGN (REGNO (base)) >= 32)
{
rtx new_rtx;
@ -6080,13 +6079,13 @@
}
}
/* Handle loading a large integer during reload. */
else if (GET_CODE (operands[1]) == CONST_INT
else if (CONST_INT_P (operands[1])
&& !const_ok_for_arm (INTVAL (operands[1]))
&& !const_ok_for_arm (~INTVAL (operands[1])))
{
/* Writing a constant to memory needs a scratch, which should
be handled with SECONDARY_RELOADs. */
gcc_assert (GET_CODE (operands[0]) == REG);
gcc_assert (REG_P (operands[0]));
operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
emit_insn (gen_movsi (operands[0], operands[1]));
@ -6098,10 +6097,10 @@
/* Thumb-2 can do everything except mem=mem and mem=const easily. */
if (can_create_pseudo_p ())
{
if (GET_CODE (operands[0]) != REG)
if (!REG_P (operands[0]))
operands[1] = force_reg (HImode, operands[1]);
/* Zero extend a constant, and keep it in an SImode reg. */
else if (GET_CODE (operands[1]) == CONST_INT)
else if (CONST_INT_P (operands[1]))
{
rtx reg = gen_reg_rtx (SImode);
HOST_WIDE_INT val = INTVAL (operands[1]) & 0xffff;
@ -6115,7 +6114,7 @@
{
if (can_create_pseudo_p ())
{
if (GET_CODE (operands[1]) == CONST_INT)
if (CONST_INT_P (operands[1]))
{
rtx reg = gen_reg_rtx (SImode);
@ -6131,21 +6130,21 @@
fixup_stack_1, by checking for other kinds of invalid addresses,
e.g. a bare reference to a virtual register. This may confuse the
alpha though, which must handle this case differently. */
if (GET_CODE (operands[0]) == MEM
if (MEM_P (operands[0])
&& !memory_address_p (GET_MODE (operands[0]),
XEXP (operands[0], 0)))
operands[0]
= replace_equiv_address (operands[0],
copy_to_reg (XEXP (operands[0], 0)));
if (GET_CODE (operands[1]) == MEM
if (MEM_P (operands[1])
&& !memory_address_p (GET_MODE (operands[1]),
XEXP (operands[1], 0)))
operands[1]
= replace_equiv_address (operands[1],
copy_to_reg (XEXP (operands[1], 0)));
if (GET_CODE (operands[1]) == MEM && optimize > 0)
if (MEM_P (operands[1]) && optimize > 0)
{
rtx reg = gen_reg_rtx (SImode);
@ -6153,17 +6152,17 @@
operands[1] = gen_lowpart (HImode, reg);
}
if (GET_CODE (operands[0]) == MEM)
if (MEM_P (operands[0]))
operands[1] = force_reg (HImode, operands[1]);
}
else if (GET_CODE (operands[1]) == CONST_INT
else if (CONST_INT_P (operands[1])
&& !satisfies_constraint_I (operands[1]))
{
/* Handle loading a large integer during reload. */
/* Writing a constant to memory needs a scratch, which should
be handled with SECONDARY_RELOADs. */
gcc_assert (GET_CODE (operands[0]) == REG);
gcc_assert (REG_P (operands[0]));
operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
emit_insn (gen_movsi (operands[0], operands[1]));
@ -6192,7 +6191,7 @@
/* The stack pointer can end up being taken as an index register.
Catch this case here and deal with it. */
if (GET_CODE (XEXP (operands[1], 0)) == PLUS
&& GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG
&& REG_P (XEXP (XEXP (operands[1], 0), 0))
&& REGNO (XEXP (XEXP (operands[1], 0), 0)) == SP_REGNUM)
{
rtx ops[2];
@ -6347,7 +6346,7 @@
if (can_create_pseudo_p ())
{
if (GET_CODE (operands[1]) == CONST_INT)
if (CONST_INT_P (operands[1]))
{
rtx reg = gen_reg_rtx (SImode);
@ -6370,13 +6369,13 @@
fixup_stack_1, by checking for other kinds of invalid addresses,
e.g. a bare reference to a virtual register. This may confuse the
alpha though, which must handle this case differently. */
if (GET_CODE (operands[0]) == MEM
if (MEM_P (operands[0])
&& !memory_address_p (GET_MODE (operands[0]),
XEXP (operands[0], 0)))
operands[0]
= replace_equiv_address (operands[0],
copy_to_reg (XEXP (operands[0], 0)));
if (GET_CODE (operands[1]) == MEM
if (MEM_P (operands[1])
&& !memory_address_p (GET_MODE (operands[1]),
XEXP (operands[1], 0)))
operands[1]
@ -6384,7 +6383,7 @@
copy_to_reg (XEXP (operands[1], 0)));
}
if (GET_CODE (operands[1]) == MEM && optimize > 0)
if (MEM_P (operands[1]) && optimize > 0)
{
rtx reg = gen_reg_rtx (SImode);
@ -6392,18 +6391,18 @@
operands[1] = gen_lowpart (QImode, reg);
}
if (GET_CODE (operands[0]) == MEM)
if (MEM_P (operands[0]))
operands[1] = force_reg (QImode, operands[1]);
}
else if (TARGET_THUMB
&& GET_CODE (operands[1]) == CONST_INT
&& CONST_INT_P (operands[1])
&& !satisfies_constraint_I (operands[1]))
{
/* Handle loading a large integer during reload. */
/* Writing a constant to memory needs a scratch, which should
be handled with SECONDARY_RELOADs. */
gcc_assert (GET_CODE (operands[0]) == REG);
gcc_assert (REG_P (operands[0]));
operands[0] = gen_rtx_SUBREG (SImode, operands[0], 0);
emit_insn (gen_movsi (operands[0], operands[1]));
@ -6460,14 +6459,14 @@
"
if (TARGET_32BIT)
{
if (GET_CODE (operands[0]) == MEM)
if (MEM_P (operands[0]))
operands[1] = force_reg (HFmode, operands[1]);
}
else /* TARGET_THUMB1 */
{
if (can_create_pseudo_p ())
{
if (GET_CODE (operands[0]) != REG)
if (!REG_P (operands[0]))
operands[1] = force_reg (HFmode, operands[1]);
}
}
@ -6531,13 +6530,13 @@
case 1:
{
rtx addr;
gcc_assert (GET_CODE(operands[1]) == MEM);
gcc_assert (MEM_P (operands[1]));
addr = XEXP (operands[1], 0);
if (GET_CODE (addr) == LABEL_REF
|| (GET_CODE (addr) == CONST
&& GET_CODE (XEXP (addr, 0)) == PLUS
&& GET_CODE (XEXP (XEXP (addr, 0), 0)) == LABEL_REF
&& GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST_INT))
&& CONST_INT_P (XEXP (XEXP (addr, 0), 1))))
{
/* Constant pool entry. */
return \"ldr\\t%0, %1\";
@ -6561,14 +6560,14 @@
"
if (TARGET_32BIT)
{
if (GET_CODE (operands[0]) == MEM)
if (MEM_P (operands[0]))
operands[1] = force_reg (SFmode, operands[1]);
}
else /* TARGET_THUMB1 */
{
if (can_create_pseudo_p ())
{
if (GET_CODE (operands[0]) != REG)
if (!REG_P (operands[0]))
operands[1] = force_reg (SFmode, operands[1]);
}
}
@ -6582,7 +6581,7 @@
(match_operand:SF 1 "immediate_operand" ""))]
"TARGET_EITHER
&& reload_completed
&& GET_CODE (operands[1]) == CONST_DOUBLE"
&& CONST_DOUBLE_P (operands[1])"
[(set (match_dup 2) (match_dup 3))]
"
operands[2] = gen_lowpart (SImode, operands[0]);
@ -6597,7 +6596,7 @@
(match_operand:SF 1 "general_operand" "r,mE,r"))]
"TARGET_32BIT
&& TARGET_SOFT_FLOAT
&& (GET_CODE (operands[0]) != MEM
&& (!MEM_P (operands[0])
|| register_operand (operands[1], SFmode))"
"@
mov%?\\t%0, %1
@ -6640,14 +6639,14 @@
"
if (TARGET_32BIT)
{
if (GET_CODE (operands[0]) == MEM)
if (MEM_P (operands[0]))
operands[1] = force_reg (DFmode, operands[1]);
}
else /* TARGET_THUMB */
{
if (can_create_pseudo_p ())
{
if (GET_CODE (operands[0]) != REG)
if (!REG_P (operands[0]))
operands[1] = force_reg (DFmode, operands[1]);
}
}
@ -6778,11 +6777,11 @@
HOST_WIDE_INT offset = 0;
/* Support only fixed point registers. */
if (GET_CODE (operands[2]) != CONST_INT
if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) > 14
|| INTVAL (operands[2]) < 2
|| GET_CODE (operands[1]) != MEM
|| GET_CODE (operands[0]) != REG
|| !MEM_P (operands[1])
|| !REG_P (operands[0])
|| REGNO (operands[0]) > (LAST_ARM_REGNUM - 1)
|| REGNO (operands[0]) + INTVAL (operands[2]) > LAST_ARM_REGNUM)
FAIL;
@ -6803,11 +6802,11 @@
HOST_WIDE_INT offset = 0;
/* Support only fixed point registers. */
if (GET_CODE (operands[2]) != CONST_INT
if (!CONST_INT_P (operands[2])
|| INTVAL (operands[2]) > 14
|| INTVAL (operands[2]) < 2
|| GET_CODE (operands[1]) != REG
|| GET_CODE (operands[0]) != MEM
|| !REG_P (operands[1])
|| !MEM_P (operands[0])
|| REGNO (operands[1]) > (LAST_ARM_REGNUM - 1)
|| REGNO (operands[1]) + INTVAL (operands[2]) > LAST_ARM_REGNUM)
FAIL;
@ -6999,7 +6998,7 @@
gcc_assert (GET_MODE (operands[1]) == DImode
|| GET_MODE (operands[2]) == DImode);
if (!arm_validize_comparison (&operands[0], &operands[1], &operands[2]))
if (!arm_validize_comparison (&operands[0], &operands[1], &operands[2]))
FAIL;
emit_jump_insn (gen_cbranch_cc (operands[0], operands[1], operands[2],
operands[3]));
@ -7430,7 +7429,7 @@
cond[1] = operands[2];
cond[2] = operands[3];
if (GET_CODE (cond[2]) == CONST_INT && INTVAL (cond[2]) < 0)
if (CONST_INT_P (cond[2]) && INTVAL (cond[2]) < 0)
output_asm_insn (\"sub\\t%0, %1, #%n2\", cond);
else
output_asm_insn (\"add\\t%0, %1, %2\", cond);
@ -9849,13 +9848,13 @@
if (GET_CODE (operands[5]) == LT
&& (operands[4] == const0_rtx))
{
if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
if (which_alternative != 1 && REG_P (operands[1]))
{
if (operands[2] == const0_rtx)
return \"and\\t%0, %1, %3, asr #31\";
return \"ands\\t%0, %1, %3, asr #32\;movcc\\t%0, %2\";
}
else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
else if (which_alternative != 0 && REG_P (operands[2]))
{
if (operands[1] == const0_rtx)
return \"bic\\t%0, %2, %3, asr #31\";
@ -9868,13 +9867,13 @@
if (GET_CODE (operands[5]) == GE
&& (operands[4] == const0_rtx))
{
if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
if (which_alternative != 1 && REG_P (operands[1]))
{
if (operands[2] == const0_rtx)
return \"bic\\t%0, %1, %3, asr #31\";
return \"bics\\t%0, %1, %3, asr #32\;movcs\\t%0, %2\";
}
else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
else if (which_alternative != 0 && REG_P (operands[2]))
{
if (operands[1] == const0_rtx)
return \"and\\t%0, %2, %3, asr #31\";
@ -9883,7 +9882,7 @@
/* The only case that falls through to here is when both ops 1 & 2
are constants. */
}
if (GET_CODE (operands[4]) == CONST_INT
if (CONST_INT_P (operands[4])
&& !const_ok_for_arm (INTVAL (operands[4])))
output_asm_insn (\"cmn\\t%3, #%n4\", operands);
else
@ -10023,8 +10022,8 @@
everything is in registers then we can do this in two instructions. */
if (operands[3] == const0_rtx
&& GET_CODE (operands[7]) != AND
&& GET_CODE (operands[5]) == REG
&& GET_CODE (operands[1]) == REG
&& REG_P (operands[5])
&& REG_P (operands[1])
&& REGNO (operands[1]) == REGNO (operands[4])
&& REGNO (operands[4]) != REGNO (operands[0]))
{
@ -10033,7 +10032,7 @@
else if (GET_CODE (operands[6]) == GE)
return \"bic\\t%0, %5, %2, asr #31\;%I7\\t%0, %4, %0\";
}
if (GET_CODE (operands[3]) == CONST_INT
if (CONST_INT_P (operands[3])
&& !const_ok_for_arm (INTVAL (operands[3])))
output_asm_insn (\"cmn\\t%2, #%n3\", operands);
else
@ -10081,8 +10080,8 @@
everything is in registers then we can do this in two instructions */
if (operands[5] == const0_rtx
&& GET_CODE (operands[7]) != AND
&& GET_CODE (operands[3]) == REG
&& GET_CODE (operands[1]) == REG
&& REG_P (operands[3])
&& REG_P (operands[1])
&& REGNO (operands[1]) == REGNO (operands[2])
&& REGNO (operands[2]) != REGNO (operands[0]))
{
@ -10092,7 +10091,7 @@
return \"bic\\t%0, %3, %4, asr #31\;%I7\\t%0, %2, %0\";
}
if (GET_CODE (operands[5]) == CONST_INT
if (CONST_INT_P (operands[5])
&& !const_ok_for_arm (INTVAL (operands[5])))
output_asm_insn (\"cmn\\t%4, #%n5\", operands);
else
@ -10677,7 +10676,7 @@
"
{
cfun->machine->eh_epilogue_sp_ofs = operands[1];
if (GET_CODE (operands[2]) != REG || REGNO (operands[2]) != 2)
if (!REG_P (operands[2]) || REGNO (operands[2]) != 2)
{
rtx ra = gen_rtx_REG (Pmode, 2);

4
gcc/config/arm/neon.md
View file

@ -255,7 +255,7 @@
{
if (can_create_pseudo_p ())
{
if (GET_CODE (operands[0]) != REG)
if (!REG_P (operands[0]))
operands[1] = force_reg (TImode, operands[1]);
}
})
@ -267,7 +267,7 @@
{
if (can_create_pseudo_p ())
{
if (GET_CODE (operands[0]) != REG)
if (!REG_P (operands[0]))
operands[1] = force_reg (<MODE>mode, operands[1]);
}
})

24
gcc/config/arm/predicates.md
View file

@ -26,7 +26,7 @@
/* We don't consider registers whose class is NO_REGS
to be a register operand. */
/* XXX might have to check for lo regs only for thumb ??? */
return (GET_CODE (op) == REG
return (REG_P (op)
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| REGNO_REG_CLASS (REGNO (op)) != NO_REGS));
})
@ -55,7 +55,7 @@
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
return (GET_CODE (op) == REG
return (REG_P (op)
&& (REGNO (op) <= LAST_ARM_REGNUM
|| REGNO (op) >= FIRST_PSEUDO_REGISTER));
})
@ -68,7 +68,7 @@
/* We don't consider registers whose class is NO_REGS
to be a register operand. */
return (GET_CODE (op) == REG
return (REG_P (op)
&& (REGNO (op) >= FIRST_PSEUDO_REGISTER
|| REGNO_REG_CLASS (REGNO (op)) == VFP_D0_D7_REGS
|| REGNO_REG_CLASS (REGNO (op)) == VFP_LO_REGS
@ -178,7 +178,7 @@
(and (match_code "mem,reg,subreg")
(match_test "(!CONSTANT_P (op)
&& (true_regnum(op) == -1
|| (GET_CODE (op) == REG
|| (REG_P (op)
&& REGNO (op) >= FIRST_PSEUDO_REGISTER)))")))
(define_predicate "vfp_compare_operand"
@ -195,7 +195,7 @@
(define_predicate "index_operand"
(ior (match_operand 0 "s_register_operand")
(and (match_operand 0 "immediate_operand")
(match_test "(GET_CODE (op) != CONST_INT
(match_test "(!CONST_INT_P (op)
|| (INTVAL (op) < 4096 && INTVAL (op) > -4096))"))))
;; True for operators that can be combined with a shift in ARM state.
@ -223,10 +223,10 @@
(and (ior (ior (and (match_code "mult")
(match_test "power_of_two_operand (XEXP (op, 1), mode)"))
(and (match_code "rotate")
(match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
(match_test "CONST_INT_P (XEXP (op, 1))
&& ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
(and (match_code "ashift,ashiftrt,lshiftrt,rotatert")
(match_test "GET_CODE (XEXP (op, 1)) != CONST_INT
(match_test "!CONST_INT_P (XEXP (op, 1))
|| ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1))) < 32")))
(match_test "mode == GET_MODE (op)")))
@ -235,7 +235,7 @@
(and (ior (and (match_code "mult")
(match_test "power_of_two_operand (XEXP (op, 1), mode)"))
(and (match_code "ashift,ashiftrt")
(match_test "GET_CODE (XEXP (op, 1)) == CONST_INT
(match_test "CONST_INT_P (XEXP (op, 1))
&& ((unsigned HOST_WIDE_INT) INTVAL (XEXP (op, 1)) < 32)")))
(match_test "mode == GET_MODE (op)")))
@ -332,7 +332,7 @@
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
return GET_CODE (op) == MEM && memory_address_p (DImode, XEXP (op, 0));
return MEM_P (op) && memory_address_p (DImode, XEXP (op, 0));
})
(define_predicate "di_operand"
@ -349,7 +349,7 @@
if (GET_CODE (op) == SUBREG)
op = SUBREG_REG (op);
return GET_CODE (op) == MEM && memory_address_p (DFmode, XEXP (op, 0));
return MEM_P (op) && memory_address_p (DFmode, XEXP (op, 0));
})
(define_predicate "soft_df_operand"
@ -559,7 +559,7 @@
rtx elt = XVECEXP (op, 0, i);
int val;
if (GET_CODE (elt) != CONST_INT)
if (!CONST_INT_P (elt))
return false;
val = INTVAL (elt);
@ -588,7 +588,7 @@
rtx elt = XVECEXP (op, 0, i);
int val;
if (GET_CODE (elt) != CONST_INT)
if (!CONST_INT_P (elt))
return false;
val = INTVAL (elt);

18
gcc/config/arm/thumb2.md
View file

@ -494,13 +494,13 @@
if (GET_CODE (operands[5]) == LT
&& (operands[4] == const0_rtx))
{
if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
if (which_alternative != 1 && REG_P (operands[1]))
{
if (operands[2] == const0_rtx)
return \"and\\t%0, %1, %3, asr #31\";
return \"ands\\t%0, %1, %3, asr #32\;it\\tcc\;movcc\\t%0, %2\";
}
else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
else if (which_alternative != 0 && REG_P (operands[2]))
{
if (operands[1] == const0_rtx)
return \"bic\\t%0, %2, %3, asr #31\";
@ -513,13 +513,13 @@
if (GET_CODE (operands[5]) == GE
&& (operands[4] == const0_rtx))
{
if (which_alternative != 1 && GET_CODE (operands[1]) == REG)
if (which_alternative != 1 && REG_P (operands[1]))
{
if (operands[2] == const0_rtx)
return \"bic\\t%0, %1, %3, asr #31\";
return \"bics\\t%0, %1, %3, asr #32\;it\\tcs\;movcs\\t%0, %2\";
}
else if (which_alternative != 0 && GET_CODE (operands[2]) == REG)
else if (which_alternative != 0 && REG_P (operands[2]))
{
if (operands[1] == const0_rtx)
return \"and\\t%0, %2, %3, asr #31\";
@ -528,7 +528,7 @@
/* The only case that falls through to here is when both ops 1 & 2
are constants. */
}
if (GET_CODE (operands[4]) == CONST_INT
if (CONST_INT_P (operands[4])
&& !const_ok_for_arm (INTVAL (operands[4])))
output_asm_insn (\"cmn\\t%3, #%n4\", operands);
else
@ -680,7 +680,7 @@
(clobber (reg:CC CC_REGNUM))]
"TARGET_THUMB2 && reload_completed
&& ((GET_CODE(operands[3]) != ROTATE && GET_CODE(operands[3]) != ROTATERT)
|| REG_P(operands[2]))"
|| REG_P (operands[2]))"
"* return arm_output_shift(operands, 2);"
[(set_attr "predicable" "yes")
(set_attr "shift" "1")
@ -709,7 +709,7 @@
"*
HOST_WIDE_INT val;
if (GET_CODE (operands[2]) == CONST_INT)
if (CONST_INT_P (operands[2]))
val = INTVAL(operands[2]);
else
val = 0;
@ -773,7 +773,7 @@
"*
HOST_WIDE_INT val;
if (GET_CODE (operands[2]) == CONST_INT)
if (CONST_INT_P (operands[2]))
val = INTVAL (operands[2]);
else
val = 0;
@ -797,7 +797,7 @@
"*
HOST_WIDE_INT val;
if (GET_CODE (operands[1]) == CONST_INT)
if (CONST_INT_P (operands[1]))
val = INTVAL (operands[1]);
else
val = 0;

2
gcc/config/arm/vec-common.md
View file

@ -28,7 +28,7 @@
{
if (can_create_pseudo_p ())
{
if (GET_CODE (operands[0]) != REG)
if (!REG_P (operands[0]))
operands[1] = force_reg (<MODE>mode, operands[1]);
else if (TARGET_NEON && CONSTANT_P (operands[1]))
{