gcc_update (gcc/config/mips/mips-tables.opt): New dependencies.
contrib: * gcc_update (gcc/config/mips/mips-tables.opt): New dependencies. gcc: * config/mips/genopt.sh, config/mips/mips-cpus.def: New files. * config/mips/mips-tables.opt: New file (generated). * config.gcc (mips*-*-*): Add mips/mips-tables.opt to extra_options. * config/mips/mips-opts.h (MIPS_ARCH_OPTION_FROM_ABI, MIPS_ARCH_OPTION_NATIVE): Define. * config/mips/mips.c (mips_cpu_info_table): Move contents to mips-cpus.def. (mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p, mips_parse_cpu): Remove. (mips_cpu_info_from_opt, mips_default_arch): New. (mips_handle_option): Don't assert that global structures are in use. Don't handle OPT_march_, OPT_mtune_ and OPT_mips here. (mips_option_override): Use new variables and functions to set state of these options. Use strcmp to check for individual CPU names. * config/mips/mips.h (MIPS_CPU_STRING_DEFAULT): Remove default definition. * config/mips/mips.opt (march=): Use ToLower and Enum. (mips): Use ToLower, Enum and Var. (mtune=): Use ToLower and Enum. * config/mips/t-mips ($(srcdir)/config/mips/mips-tables.opt): New. From-SVN: r173561
This commit is contained in:
Joseph Myers
Joseph Myers
parent
4fc07af967
commit
d371df6f10
12 changed files with 976 additions and 235 deletions
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@ -1,3 +1,7 @@
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2011-05-09 Joseph Myers <joseph@codesourcery.com>
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* gcc_update (gcc/config/mips/mips-tables.opt): New dependencies.
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2010-05-05 Joern Rennecke <joern.rennecke@embecosm.com>
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* config-list.mk: New file.
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@ -82,6 +82,7 @@ gcc/fixinc/fixincl.x: gcc/fixinc/fixincl.tpl gcc/fixinc/inclhack.def
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gcc/config/arm/arm-tune.md: gcc/config/arm/arm-cores.def gcc/config/arm/gentune.sh
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gcc/config/arm/arm-tables.opt: gcc/config/arm/arm-arches.def gcc/config/arm/arm-cores.def gcc/config/arm/genopt.sh
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gcc/config/m68k/m68k-tables.opt: gcc/config/m68k/m68k-devices.def gcc/config/m68k/m68k-isas.def gcc/config/m68k/m68k-microarchs.def gcc/config/m68k/genopt.sh
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gcc/config/mips/mips-tables.opt: gcc/config/mips/mips-cpus.def gcc/config/mips/genopt.sh
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# And then, language-specific files
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gcc/cp/cfns.h: gcc/cp/cfns.gperf
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gcc/java/keyword.h: gcc/java/keyword.gperf
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@ -1,3 +1,28 @@
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2011-05-09 Joseph Myers <joseph@codesourcery.com>
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* config/mips/genopt.sh, config/mips/mips-cpus.def: New files.
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* config/mips/mips-tables.opt: New file (generated).
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* config.gcc (mips*-*-*): Add mips/mips-tables.opt to
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extra_options.
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* config/mips/mips-opts.h (MIPS_ARCH_OPTION_FROM_ABI,
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MIPS_ARCH_OPTION_NATIVE): Define.
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* config/mips/mips.c (mips_cpu_info_table): Move contents to
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mips-cpus.def.
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(mips_strict_matching_cpu_name_p, mips_matching_cpu_name_p,
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mips_parse_cpu): Remove.
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(mips_cpu_info_from_opt, mips_default_arch): New.
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(mips_handle_option): Don't assert that global structures are in
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use. Don't handle OPT_march_, OPT_mtune_ and OPT_mips here.
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(mips_option_override): Use new variables and functions to set
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state of these options. Use strcmp to check for individual CPU
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names.
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* config/mips/mips.h (MIPS_CPU_STRING_DEFAULT): Remove default
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definition.
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* config/mips/mips.opt (march=): Use ToLower and Enum.
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(mips): Use ToLower, Enum and Var.
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(mtune=): Use ToLower and Enum.
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* config/mips/t-mips ($(srcdir)/config/mips/mips-tables.opt): New.
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2011-05-08 Jan Hubicka <jh@suse.cz>
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* gimple.c (type_pair_hash, type_pair_eq, lookup_type_pair):
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@ -371,7 +371,7 @@ mips*-*-*)
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cpu_type=mips
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need_64bit_hwint=yes
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extra_headers="loongson.h"
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extra_options="${extra_options} g.opt"
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extra_options="${extra_options} g.opt mips/mips-tables.opt"
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;;
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picochip-*-*)
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cpu_type=picochip
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123
gcc/config/mips/genopt.sh
Executable file
123
gcc/config/mips/genopt.sh
Executable file
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@ -0,0 +1,123 @@
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#!/bin/sh
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# Generate mips-tables.opt from the list of CPUs in mips-cpus.def.
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# Copyright (C) 2011 Free Software Foundation, Inc.
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#
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# This file is part of GCC.
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#
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# GCC is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 3, or (at your option)
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# any later version.
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#
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# GCC is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with GCC; see the file COPYING3. If not see
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# <http://www.gnu.org/licenses/>.
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cat <<EOF
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; -*- buffer-read-only: t -*-
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; Generated automatically by genopt.sh from mips-cpus.def.
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; Copyright (C) 2011 Free Software Foundation, Inc.
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;
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; This file is part of GCC.
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;
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; GCC is free software; you can redistribute it and/or modify it under
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; the terms of the GNU General Public License as published by the Free
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; Software Foundation; either version 3, or (at your option) any later
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; version.
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;
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; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
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; WARRANTY; without even the implied warranty of MERCHANTABILITY or
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; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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; for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with GCC; see the file COPYING3. If not see
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; <http://www.gnu.org/licenses/>.
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Enum
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Name(mips_arch_opt_value) Type(int)
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Known MIPS CPUs (for use with the -march= and -mtune= options):
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Enum
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Name(mips_mips_opt_value) Type(int)
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Known MIPS ISA levels (for use with the -mips option):
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EnumValue
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Enum(mips_arch_opt_value) String(from-abi) Value(MIPS_ARCH_OPTION_FROM_ABI)
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EnumValue
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Enum(mips_arch_opt_value) String(native) Value(MIPS_ARCH_OPTION_NATIVE) DriverOnly
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EOF
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awk -F'[(, ]+' '
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BEGIN {
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value = 0
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}
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# Write an entry for a single string accepted as a -march= argument.
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function write_one_arch_value(name, value, flags)
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{
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print "EnumValue"
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print "Enum(mips_arch_opt_value) String(" name ") Value(" value ")" flags
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print ""
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if (name ~ "^mips") {
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sub("^mips", "", name)
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print "EnumValue"
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print "Enum(mips_mips_opt_value) String(" name ") Value(" value ")"
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print ""
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}
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}
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# The logic for matching CPU name variants should be the same as in GAS.
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# Write an entry for a single string accepted as a -march= argument,
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# plus any variant with a final "000" replaced by "k".
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function write_arch_value_maybe_k(name, value, flags)
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{
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write_one_arch_value(name, value, flags)
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if (name ~ "000$") {
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sub("000$", "k", name)
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write_one_arch_value(name, value, "")
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}
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}
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# Write all the entries for a -march= argument. In addition to
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# replacement of a final "000" with "k", an argument starting with
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# "vr", "rm" or "r" followed by a number, or just a plain number,
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# matches a plain number or "r" followed by a plain number.
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function write_all_arch_values(name, value)
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{
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write_arch_value_maybe_k(name, value, " Canonical")
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cname = name
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if (cname ~ "^vr") {
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sub("^vr", "", cname)
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} else if (cname ~ "^rm") {
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sub("^rm", "", cname)
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} else if (cname ~ "^r") {
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sub("^r", "", cname)
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}
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if (cname ~ "^[0-9]") {
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if (cname != name)
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write_arch_value_maybe_k(cname, value, "")
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rname = "r" cname
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if (rname != name)
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write_arch_value_maybe_k(rname, value, "")
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}
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}
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/^MIPS_CPU/ {
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name = $2
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gsub("\"", "", name)
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write_all_arch_values(name, value)
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value++
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}' $1/mips-cpus.def
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147
gcc/config/mips/mips-cpus.def
Normal file
147
gcc/config/mips/mips-cpus.def
Normal file
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@ -0,0 +1,147 @@
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/* MIPS CPU names.
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Copyright (C) 1989, 1990, 1991, 1993, 1994, 1995, 1996, 1997, 1998,
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1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010,
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2011
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Free Software Foundation, Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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/* A table describing all the processors GCC knows about. The first
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mention of an ISA level is taken as the canonical name for that
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ISA.
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To ease comparison, please keep this table in the same order
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as GAS's mips_cpu_info_table. Please also make sure that
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MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
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options correctly.
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Before including this file, define a macro:
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MIPS_CPU (NAME, CPU, ISA, FLAGS)
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where the arguments are the fields of struct mips_cpu_info. */
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/* Entries for generic ISAs. */
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MIPS_CPU ("mips1", PROCESSOR_R3000, 1, 0)
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MIPS_CPU ("mips2", PROCESSOR_R6000, 2, 0)
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MIPS_CPU ("mips3", PROCESSOR_R4000, 3, 0)
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MIPS_CPU ("mips4", PROCESSOR_R8000, 4, 0)
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/* Prefer not to use branch-likely instructions for generic MIPS32rX
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and MIPS64rX code. The instructions were officially deprecated
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in revisions 2 and earlier, but revision 3 is likely to downgrade
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that to a recommendation to avoid the instructions in code that
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isn't tuned to a specific processor. */
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MIPS_CPU ("mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY)
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MIPS_CPU ("mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY)
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MIPS_CPU ("mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY)
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/* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
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MIPS_CPU ("mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY)
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/* MIPS I processors. */
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MIPS_CPU ("r3000", PROCESSOR_R3000, 1, 0)
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MIPS_CPU ("r2000", PROCESSOR_R3000, 1, 0)
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MIPS_CPU ("r3900", PROCESSOR_R3900, 1, 0)
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/* MIPS II processors. */
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MIPS_CPU ("r6000", PROCESSOR_R6000, 2, 0)
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/* MIPS III processors. */
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MIPS_CPU ("r4000", PROCESSOR_R4000, 3, 0)
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MIPS_CPU ("vr4100", PROCESSOR_R4100, 3, 0)
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MIPS_CPU ("vr4111", PROCESSOR_R4111, 3, 0)
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MIPS_CPU ("vr4120", PROCESSOR_R4120, 3, 0)
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MIPS_CPU ("vr4130", PROCESSOR_R4130, 3, 0)
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MIPS_CPU ("vr4300", PROCESSOR_R4300, 3, 0)
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MIPS_CPU ("r4400", PROCESSOR_R4000, 3, 0)
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MIPS_CPU ("r4600", PROCESSOR_R4600, 3, 0)
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MIPS_CPU ("orion", PROCESSOR_R4600, 3, 0)
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MIPS_CPU ("r4650", PROCESSOR_R4650, 3, 0)
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/* ST Loongson 2E/2F processors. */
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MIPS_CPU ("loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY)
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MIPS_CPU ("loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY)
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/* MIPS IV processors. */
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MIPS_CPU ("r8000", PROCESSOR_R8000, 4, 0)
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MIPS_CPU ("r10000", PROCESSOR_R10000, 4, 0)
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MIPS_CPU ("r12000", PROCESSOR_R10000, 4, 0)
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MIPS_CPU ("r14000", PROCESSOR_R10000, 4, 0)
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MIPS_CPU ("r16000", PROCESSOR_R10000, 4, 0)
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MIPS_CPU ("vr5000", PROCESSOR_R5000, 4, 0)
|
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MIPS_CPU ("vr5400", PROCESSOR_R5400, 4, 0)
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MIPS_CPU ("vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY)
|
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MIPS_CPU ("rm7000", PROCESSOR_R7000, 4, 0)
|
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MIPS_CPU ("rm9000", PROCESSOR_R9000, 4, 0)
|
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|
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/* MIPS32 processors. */
|
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MIPS_CPU ("4kc", PROCESSOR_4KC, 32, 0)
|
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MIPS_CPU ("4km", PROCESSOR_4KC, 32, 0)
|
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MIPS_CPU ("4kp", PROCESSOR_4KP, 32, 0)
|
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MIPS_CPU ("4ksc", PROCESSOR_4KC, 32, 0)
|
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|
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/* MIPS32 Release 2 processors. */
|
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MIPS_CPU ("m4k", PROCESSOR_M4K, 33, 0)
|
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MIPS_CPU ("4kec", PROCESSOR_4KC, 33, 0)
|
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MIPS_CPU ("4kem", PROCESSOR_4KC, 33, 0)
|
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MIPS_CPU ("4kep", PROCESSOR_4KP, 33, 0)
|
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MIPS_CPU ("4ksd", PROCESSOR_4KC, 33, 0)
|
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|
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MIPS_CPU ("24kc", PROCESSOR_24KC, 33, 0)
|
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MIPS_CPU ("24kf2_1", PROCESSOR_24KF2_1, 33, 0)
|
||||
MIPS_CPU ("24kf", PROCESSOR_24KF2_1, 33, 0)
|
||||
MIPS_CPU ("24kf1_1", PROCESSOR_24KF1_1, 33, 0)
|
||||
MIPS_CPU ("24kfx", PROCESSOR_24KF1_1, 33, 0)
|
||||
MIPS_CPU ("24kx", PROCESSOR_24KF1_1, 33, 0)
|
||||
|
||||
MIPS_CPU ("24kec", PROCESSOR_24KC, 33, 0) /* 24K with DSP. */
|
||||
MIPS_CPU ("24kef2_1", PROCESSOR_24KF2_1, 33, 0)
|
||||
MIPS_CPU ("24kef", PROCESSOR_24KF2_1, 33, 0)
|
||||
MIPS_CPU ("24kef1_1", PROCESSOR_24KF1_1, 33, 0)
|
||||
MIPS_CPU ("24kefx", PROCESSOR_24KF1_1, 33, 0)
|
||||
MIPS_CPU ("24kex", PROCESSOR_24KF1_1, 33, 0)
|
||||
|
||||
MIPS_CPU ("34kc", PROCESSOR_24KC, 33, 0) /* 34K with MT/DSP. */
|
||||
MIPS_CPU ("34kf2_1", PROCESSOR_24KF2_1, 33, 0)
|
||||
MIPS_CPU ("34kf", PROCESSOR_24KF2_1, 33, 0)
|
||||
MIPS_CPU ("34kf1_1", PROCESSOR_24KF1_1, 33, 0)
|
||||
MIPS_CPU ("34kfx", PROCESSOR_24KF1_1, 33, 0)
|
||||
MIPS_CPU ("34kx", PROCESSOR_24KF1_1, 33, 0)
|
||||
|
||||
MIPS_CPU ("74kc", PROCESSOR_74KC, 33, 0) /* 74K with DSPr2. */
|
||||
MIPS_CPU ("74kf2_1", PROCESSOR_74KF2_1, 33, 0)
|
||||
MIPS_CPU ("74kf", PROCESSOR_74KF2_1, 33, 0)
|
||||
MIPS_CPU ("74kf1_1", PROCESSOR_74KF1_1, 33, 0)
|
||||
MIPS_CPU ("74kfx", PROCESSOR_74KF1_1, 33, 0)
|
||||
MIPS_CPU ("74kx", PROCESSOR_74KF1_1, 33, 0)
|
||||
MIPS_CPU ("74kf3_2", PROCESSOR_74KF3_2, 33, 0)
|
||||
|
||||
MIPS_CPU ("1004kc", PROCESSOR_24KC, 33, 0) /* 1004K with MT/DSP. */
|
||||
MIPS_CPU ("1004kf2_1", PROCESSOR_24KF2_1, 33, 0)
|
||||
MIPS_CPU ("1004kf", PROCESSOR_24KF2_1, 33, 0)
|
||||
MIPS_CPU ("1004kf1_1", PROCESSOR_24KF1_1, 33, 0)
|
||||
|
||||
/* MIPS64 processors. */
|
||||
MIPS_CPU ("5kc", PROCESSOR_5KC, 64, 0)
|
||||
MIPS_CPU ("5kf", PROCESSOR_5KF, 64, 0)
|
||||
MIPS_CPU ("20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY)
|
||||
MIPS_CPU ("sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY)
|
||||
MIPS_CPU ("sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY)
|
||||
MIPS_CPU ("sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY)
|
||||
MIPS_CPU ("xlr", PROCESSOR_XLR, 64, 0)
|
||||
MIPS_CPU ("loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY)
|
||||
|
||||
/* MIPS64 Release 2 processors. */
|
||||
MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY)
|
||||
|
|
@ -36,4 +36,10 @@ enum mips_r10k_cache_barrier_setting {
|
|||
R10K_CACHE_BARRIER_LOAD_STORE
|
||||
};
|
||||
|
||||
/* No enumeration is defined to index the -march= values (entries in
|
||||
mips_cpu_info_table), with the type int being used instead, but we
|
||||
need to distinguish the special "from-abi" and "native" values. */
|
||||
#define MIPS_ARCH_OPTION_FROM_ABI -1
|
||||
#define MIPS_ARCH_OPTION_NATIVE -2
|
||||
|
||||
#endif
|
||||
|
|
|
|||
605
gcc/config/mips/mips-tables.opt
Normal file
605
gcc/config/mips/mips-tables.opt
Normal file
|
|
@ -0,0 +1,605 @@
|
|||
; -*- buffer-read-only: t -*-
|
||||
; Generated automatically by genopt.sh from mips-cpus.def.
|
||||
|
||||
; Copyright (C) 2011 Free Software Foundation, Inc.
|
||||
;
|
||||
; This file is part of GCC.
|
||||
;
|
||||
; GCC is free software; you can redistribute it and/or modify it under
|
||||
; the terms of the GNU General Public License as published by the Free
|
||||
; Software Foundation; either version 3, or (at your option) any later
|
||||
; version.
|
||||
;
|
||||
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
; for more details.
|
||||
;
|
||||
; You should have received a copy of the GNU General Public License
|
||||
; along with GCC; see the file COPYING3. If not see
|
||||
; <http://www.gnu.org/licenses/>.
|
||||
|
||||
Enum
|
||||
Name(mips_arch_opt_value) Type(int)
|
||||
Known MIPS CPUs (for use with the -march= and -mtune= options):
|
||||
|
||||
Enum
|
||||
Name(mips_mips_opt_value) Type(int)
|
||||
Known MIPS ISA levels (for use with the -mips option):
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(from-abi) Value(MIPS_ARCH_OPTION_FROM_ABI)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(native) Value(MIPS_ARCH_OPTION_NATIVE) DriverOnly
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(mips1) Value(0) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_mips_opt_value) String(1) Value(0)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(mips2) Value(1) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_mips_opt_value) String(2) Value(1)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(mips3) Value(2) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_mips_opt_value) String(3) Value(2)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(mips4) Value(3) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_mips_opt_value) String(4) Value(3)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(mips32) Value(4) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_mips_opt_value) String(32) Value(4)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(mips32r2) Value(5) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_mips_opt_value) String(32r2) Value(5)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(mips64) Value(6) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_mips_opt_value) String(64) Value(6)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(mips64r2) Value(7) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_mips_opt_value) String(64r2) Value(7)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r3000) Value(8) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r3k) Value(8)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(3000) Value(8)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(3k) Value(8)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r2000) Value(9) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r2k) Value(9)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(2000) Value(9)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(2k) Value(9)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r3900) Value(10) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(3900) Value(10)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r6000) Value(11) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r6k) Value(11)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(6000) Value(11)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(6k) Value(11)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r4000) Value(12) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r4k) Value(12)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(4000) Value(12)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(4k) Value(12)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(vr4100) Value(13) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(4100) Value(13)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r4100) Value(13)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(vr4111) Value(14) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(4111) Value(14)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r4111) Value(14)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(vr4120) Value(15) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(4120) Value(15)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r4120) Value(15)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(vr4130) Value(16) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(4130) Value(16)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r4130) Value(16)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(vr4300) Value(17) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(4300) Value(17)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r4300) Value(17)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r4400) Value(18) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(4400) Value(18)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r4600) Value(19) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(4600) Value(19)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(orion) Value(20) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r4650) Value(21) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(4650) Value(21)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(loongson2e) Value(22) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(loongson2f) Value(23) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r8000) Value(24) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r8k) Value(24)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(8000) Value(24)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(8k) Value(24)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r10000) Value(25) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r10k) Value(25)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(10000) Value(25)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(10k) Value(25)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r12000) Value(26) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r12k) Value(26)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(12000) Value(26)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(12k) Value(26)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r14000) Value(27) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r14k) Value(27)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(14000) Value(27)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(14k) Value(27)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r16000) Value(28) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r16k) Value(28)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(16000) Value(28)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(16k) Value(28)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(vr5000) Value(29) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(vr5k) Value(29)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(5000) Value(29)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(5k) Value(29)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r5000) Value(29)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r5k) Value(29)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(vr5400) Value(30) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(5400) Value(30)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r5400) Value(30)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(vr5500) Value(31) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(5500) Value(31)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r5500) Value(31)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(rm7000) Value(32) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(rm7k) Value(32)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(7000) Value(32)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(7k) Value(32)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r7000) Value(32)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r7k) Value(32)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(rm9000) Value(33) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(rm9k) Value(33)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(9000) Value(33)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(9k) Value(33)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r9000) Value(33)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r9k) Value(33)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(4kc) Value(34) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r4kc) Value(34)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(4km) Value(35) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r4km) Value(35)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(4kp) Value(36) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r4kp) Value(36)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(4ksc) Value(37) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r4ksc) Value(37)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(m4k) Value(38) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(4kec) Value(39) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r4kec) Value(39)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(4kem) Value(40) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r4kem) Value(40)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(4kep) Value(41) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r4kep) Value(41)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(4ksd) Value(42) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r4ksd) Value(42)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kc) Value(43) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kc) Value(43)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kf2_1) Value(44) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kf2_1) Value(44)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kf) Value(45) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kf) Value(45)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kf1_1) Value(46) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kf1_1) Value(46)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kfx) Value(47) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kfx) Value(47)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kx) Value(48) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kx) Value(48)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kec) Value(49) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kec) Value(49)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kef2_1) Value(50) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kef2_1) Value(50)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kef) Value(51) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kef) Value(51)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kef1_1) Value(52) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kef1_1) Value(52)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kefx) Value(53) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kefx) Value(53)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(24kex) Value(54) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r24kex) Value(54)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(34kc) Value(55) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r34kc) Value(55)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(34kf2_1) Value(56) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r34kf2_1) Value(56)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(34kf) Value(57) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r34kf) Value(57)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(34kf1_1) Value(58) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r34kf1_1) Value(58)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(34kfx) Value(59) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r34kfx) Value(59)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(34kx) Value(60) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r34kx) Value(60)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(74kc) Value(61) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r74kc) Value(61)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(74kf2_1) Value(62) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r74kf2_1) Value(62)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(74kf) Value(63) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r74kf) Value(63)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(74kf1_1) Value(64) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r74kf1_1) Value(64)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(74kfx) Value(65) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r74kfx) Value(65)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(74kx) Value(66) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r74kx) Value(66)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(74kf3_2) Value(67) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r74kf3_2) Value(67)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(1004kc) Value(68) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r1004kc) Value(68)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(1004kf2_1) Value(69) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r1004kf2_1) Value(69)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(1004kf) Value(70) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r1004kf) Value(70)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(1004kf1_1) Value(71) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r1004kf1_1) Value(71)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(5kc) Value(72) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r5kc) Value(72)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(5kf) Value(73) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r5kf) Value(73)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(20kc) Value(74) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(r20kc) Value(74)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(sb1) Value(75) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(sb1a) Value(76) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(sr71000) Value(77) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(sr71k) Value(77)
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(xlr) Value(78) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(loongson3a) Value(79) Canonical
|
||||
|
||||
EnumValue
|
||||
Enum(mips_arch_opt_value) String(octeon) Value(80) Canonical
|
||||
|
||||
|
|
@ -645,125 +645,13 @@ static const struct attribute_spec mips_attribute_table[] = {
|
|||
{ NULL, 0, 0, false, false, false, NULL, false }
|
||||
};
|
||||
|
||||
/* A table describing all the processors GCC knows about. Names are
|
||||
matched in the order listed. The first mention of an ISA level is
|
||||
taken as the canonical name for that ISA.
|
||||
|
||||
To ease comparison, please keep this table in the same order
|
||||
as GAS's mips_cpu_info_table. Please also make sure that
|
||||
MIPS_ISA_LEVEL_SPEC and MIPS_ARCH_FLOAT_SPEC handle all -march
|
||||
options correctly. */
|
||||
/* A table describing all the processors GCC knows about; see
|
||||
mips-cpus.def for details. */
|
||||
static const struct mips_cpu_info mips_cpu_info_table[] = {
|
||||
/* Entries for generic ISAs. */
|
||||
{ "mips1", PROCESSOR_R3000, 1, 0 },
|
||||
{ "mips2", PROCESSOR_R6000, 2, 0 },
|
||||
{ "mips3", PROCESSOR_R4000, 3, 0 },
|
||||
{ "mips4", PROCESSOR_R8000, 4, 0 },
|
||||
/* Prefer not to use branch-likely instructions for generic MIPS32rX
|
||||
and MIPS64rX code. The instructions were officially deprecated
|
||||
in revisions 2 and earlier, but revision 3 is likely to downgrade
|
||||
that to a recommendation to avoid the instructions in code that
|
||||
isn't tuned to a specific processor. */
|
||||
{ "mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY },
|
||||
{ "mips32r2", PROCESSOR_M4K, 33, PTF_AVOID_BRANCHLIKELY },
|
||||
{ "mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY },
|
||||
/* ??? For now just tune the generic MIPS64r2 for 5KC as well. */
|
||||
{ "mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY },
|
||||
|
||||
/* MIPS I processors. */
|
||||
{ "r3000", PROCESSOR_R3000, 1, 0 },
|
||||
{ "r2000", PROCESSOR_R3000, 1, 0 },
|
||||
{ "r3900", PROCESSOR_R3900, 1, 0 },
|
||||
|
||||
/* MIPS II processors. */
|
||||
{ "r6000", PROCESSOR_R6000, 2, 0 },
|
||||
|
||||
/* MIPS III processors. */
|
||||
{ "r4000", PROCESSOR_R4000, 3, 0 },
|
||||
{ "vr4100", PROCESSOR_R4100, 3, 0 },
|
||||
{ "vr4111", PROCESSOR_R4111, 3, 0 },
|
||||
{ "vr4120", PROCESSOR_R4120, 3, 0 },
|
||||
{ "vr4130", PROCESSOR_R4130, 3, 0 },
|
||||
{ "vr4300", PROCESSOR_R4300, 3, 0 },
|
||||
{ "r4400", PROCESSOR_R4000, 3, 0 },
|
||||
{ "r4600", PROCESSOR_R4600, 3, 0 },
|
||||
{ "orion", PROCESSOR_R4600, 3, 0 },
|
||||
{ "r4650", PROCESSOR_R4650, 3, 0 },
|
||||
/* ST Loongson 2E/2F processors. */
|
||||
{ "loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY },
|
||||
{ "loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY },
|
||||
|
||||
/* MIPS IV processors. */
|
||||
{ "r8000", PROCESSOR_R8000, 4, 0 },
|
||||
{ "r10000", PROCESSOR_R10000, 4, 0 },
|
||||
{ "r12000", PROCESSOR_R10000, 4, 0 },
|
||||
{ "r14000", PROCESSOR_R10000, 4, 0 },
|
||||
{ "r16000", PROCESSOR_R10000, 4, 0 },
|
||||
{ "vr5000", PROCESSOR_R5000, 4, 0 },
|
||||
{ "vr5400", PROCESSOR_R5400, 4, 0 },
|
||||
{ "vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY },
|
||||
{ "rm7000", PROCESSOR_R7000, 4, 0 },
|
||||
{ "rm9000", PROCESSOR_R9000, 4, 0 },
|
||||
|
||||
/* MIPS32 processors. */
|
||||
{ "4kc", PROCESSOR_4KC, 32, 0 },
|
||||
{ "4km", PROCESSOR_4KC, 32, 0 },
|
||||
{ "4kp", PROCESSOR_4KP, 32, 0 },
|
||||
{ "4ksc", PROCESSOR_4KC, 32, 0 },
|
||||
|
||||
/* MIPS32 Release 2 processors. */
|
||||
{ "m4k", PROCESSOR_M4K, 33, 0 },
|
||||
{ "4kec", PROCESSOR_4KC, 33, 0 },
|
||||
{ "4kem", PROCESSOR_4KC, 33, 0 },
|
||||
{ "4kep", PROCESSOR_4KP, 33, 0 },
|
||||
{ "4ksd", PROCESSOR_4KC, 33, 0 },
|
||||
|
||||
{ "24kc", PROCESSOR_24KC, 33, 0 },
|
||||
{ "24kf2_1", PROCESSOR_24KF2_1, 33, 0 },
|
||||
{ "24kf", PROCESSOR_24KF2_1, 33, 0 },
|
||||
{ "24kf1_1", PROCESSOR_24KF1_1, 33, 0 },
|
||||
{ "24kfx", PROCESSOR_24KF1_1, 33, 0 },
|
||||
{ "24kx", PROCESSOR_24KF1_1, 33, 0 },
|
||||
|
||||
{ "24kec", PROCESSOR_24KC, 33, 0 }, /* 24K with DSP. */
|
||||
{ "24kef2_1", PROCESSOR_24KF2_1, 33, 0 },
|
||||
{ "24kef", PROCESSOR_24KF2_1, 33, 0 },
|
||||
{ "24kef1_1", PROCESSOR_24KF1_1, 33, 0 },
|
||||
{ "24kefx", PROCESSOR_24KF1_1, 33, 0 },
|
||||
{ "24kex", PROCESSOR_24KF1_1, 33, 0 },
|
||||
|
||||
{ "34kc", PROCESSOR_24KC, 33, 0 }, /* 34K with MT/DSP. */
|
||||
{ "34kf2_1", PROCESSOR_24KF2_1, 33, 0 },
|
||||
{ "34kf", PROCESSOR_24KF2_1, 33, 0 },
|
||||
{ "34kf1_1", PROCESSOR_24KF1_1, 33, 0 },
|
||||
{ "34kfx", PROCESSOR_24KF1_1, 33, 0 },
|
||||
{ "34kx", PROCESSOR_24KF1_1, 33, 0 },
|
||||
|
||||
{ "74kc", PROCESSOR_74KC, 33, 0 }, /* 74K with DSPr2. */
|
||||
{ "74kf2_1", PROCESSOR_74KF2_1, 33, 0 },
|
||||
{ "74kf", PROCESSOR_74KF2_1, 33, 0 },
|
||||
{ "74kf1_1", PROCESSOR_74KF1_1, 33, 0 },
|
||||
{ "74kfx", PROCESSOR_74KF1_1, 33, 0 },
|
||||
{ "74kx", PROCESSOR_74KF1_1, 33, 0 },
|
||||
{ "74kf3_2", PROCESSOR_74KF3_2, 33, 0 },
|
||||
|
||||
{ "1004kc", PROCESSOR_24KC, 33, 0 }, /* 1004K with MT/DSP. */
|
||||
{ "1004kf2_1", PROCESSOR_24KF2_1, 33, 0 },
|
||||
{ "1004kf", PROCESSOR_24KF2_1, 33, 0 },
|
||||
{ "1004kf1_1", PROCESSOR_24KF1_1, 33, 0 },
|
||||
|
||||
/* MIPS64 processors. */
|
||||
{ "5kc", PROCESSOR_5KC, 64, 0 },
|
||||
{ "5kf", PROCESSOR_5KF, 64, 0 },
|
||||
{ "20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY },
|
||||
{ "sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY },
|
||||
{ "sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY },
|
||||
{ "sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY },
|
||||
{ "xlr", PROCESSOR_XLR, 64, 0 },
|
||||
{ "loongson3a", PROCESSOR_LOONGSON_3A, 64, PTF_AVOID_BRANCHLIKELY },
|
||||
|
||||
/* MIPS64 Release 2 processors. */
|
||||
{ "octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY }
|
||||
#define MIPS_CPU(NAME, CPU, ISA, FLAGS) \
|
||||
{ NAME, CPU, ISA, FLAGS },
|
||||
#include "mips-cpus.def"
|
||||
#undef MIPS_CPU
|
||||
};
|
||||
|
||||
/* Default costs. If these are used for a processor we should look
|
||||
|
|
@ -15320,91 +15208,48 @@ mips_cpu_info_from_isa (int isa)
|
|||
return NULL;
|
||||
}
|
||||
|
||||
/* Return true if GIVEN is the same as CANONICAL, or if it is CANONICAL
|
||||
with a final "000" replaced by "k". Ignore case.
|
||||
|
||||
Note: this function is shared between GCC and GAS. */
|
||||
|
||||
static bool
|
||||
mips_strict_matching_cpu_name_p (const char *canonical, const char *given)
|
||||
{
|
||||
while (*given != 0 && TOLOWER (*given) == TOLOWER (*canonical))
|
||||
given++, canonical++;
|
||||
|
||||
return ((*given == 0 && *canonical == 0)
|
||||
|| (strcmp (canonical, "000") == 0 && strcasecmp (given, "k") == 0));
|
||||
}
|
||||
|
||||
/* Return true if GIVEN matches CANONICAL, where GIVEN is a user-supplied
|
||||
CPU name. We've traditionally allowed a lot of variation here.
|
||||
|
||||
Note: this function is shared between GCC and GAS. */
|
||||
|
||||
static bool
|
||||
mips_matching_cpu_name_p (const char *canonical, const char *given)
|
||||
{
|
||||
/* First see if the name matches exactly, or with a final "000"
|
||||
turned into "k". */
|
||||
if (mips_strict_matching_cpu_name_p (canonical, given))
|
||||
return true;
|
||||
|
||||
/* If not, try comparing based on numerical designation alone.
|
||||
See if GIVEN is an unadorned number, or 'r' followed by a number. */
|
||||
if (TOLOWER (*given) == 'r')
|
||||
given++;
|
||||
if (!ISDIGIT (*given))
|
||||
return false;
|
||||
|
||||
/* Skip over some well-known prefixes in the canonical name,
|
||||
hoping to find a number there too. */
|
||||
if (TOLOWER (canonical[0]) == 'v' && TOLOWER (canonical[1]) == 'r')
|
||||
canonical += 2;
|
||||
else if (TOLOWER (canonical[0]) == 'r' && TOLOWER (canonical[1]) == 'm')
|
||||
canonical += 2;
|
||||
else if (TOLOWER (canonical[0]) == 'r')
|
||||
canonical += 1;
|
||||
|
||||
return mips_strict_matching_cpu_name_p (canonical, given);
|
||||
}
|
||||
|
||||
/* Return the mips_cpu_info entry for the processor or ISA given
|
||||
by CPU_STRING. Return null if the string isn't recognized.
|
||||
|
||||
A similar function exists in GAS. */
|
||||
/* Return a mips_cpu_info entry determined by an option valued
|
||||
OPT. */
|
||||
|
||||
static const struct mips_cpu_info *
|
||||
mips_parse_cpu (const char *cpu_string)
|
||||
mips_cpu_info_from_opt (int opt)
|
||||
{
|
||||
switch (opt)
|
||||
{
|
||||
case MIPS_ARCH_OPTION_FROM_ABI:
|
||||
/* 'from-abi' selects the most compatible architecture for the
|
||||
given ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit
|
||||
ABIs. For the EABIs, we have to decide whether we're using
|
||||
the 32-bit or 64-bit version. */
|
||||
return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
|
||||
: ABI_NEEDS_64BIT_REGS ? 3
|
||||
: (TARGET_64BIT ? 3 : 1));
|
||||
|
||||
case MIPS_ARCH_OPTION_NATIVE:
|
||||
gcc_unreachable ();
|
||||
|
||||
default:
|
||||
return &mips_cpu_info_table[opt];
|
||||
}
|
||||
}
|
||||
|
||||
/* Return a default mips_cpu_info entry, given that no -march= option
|
||||
was explicitly specified. */
|
||||
|
||||
static const struct mips_cpu_info *
|
||||
mips_default_arch (void)
|
||||
{
|
||||
#ifdef MIPS_CPU_STRING_DEFAULT
|
||||
unsigned int i;
|
||||
const char *s;
|
||||
|
||||
/* In the past, we allowed upper-case CPU names, but it doesn't
|
||||
work well with the multilib machinery. */
|
||||
for (s = cpu_string; *s != 0; s++)
|
||||
if (ISUPPER (*s))
|
||||
{
|
||||
warning (0, "CPU names must be lower case");
|
||||
break;
|
||||
}
|
||||
|
||||
/* 'from-abi' selects the most compatible architecture for the given
|
||||
ABI: MIPS I for 32-bit ABIs and MIPS III for 64-bit ABIs. For the
|
||||
EABIs, we have to decide whether we're using the 32-bit or 64-bit
|
||||
version. */
|
||||
if (strcasecmp (cpu_string, "from-abi") == 0)
|
||||
return mips_cpu_info_from_isa (ABI_NEEDS_32BIT_REGS ? 1
|
||||
: ABI_NEEDS_64BIT_REGS ? 3
|
||||
: (TARGET_64BIT ? 3 : 1));
|
||||
|
||||
/* 'default' has traditionally been a no-op. Probably not very useful. */
|
||||
if (strcasecmp (cpu_string, "default") == 0)
|
||||
return NULL;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE (mips_cpu_info_table); i++)
|
||||
if (mips_matching_cpu_name_p (mips_cpu_info_table[i].name, cpu_string))
|
||||
if (strcmp (mips_cpu_info_table[i].name, MIPS_CPU_STRING_DEFAULT) == 0)
|
||||
return mips_cpu_info_table + i;
|
||||
|
||||
return NULL;
|
||||
gcc_unreachable ();
|
||||
#else
|
||||
/* 'from-abi' makes a good default: you get whatever the ABI
|
||||
requires. */
|
||||
return mips_cpu_info_from_opt (MIPS_ARCH_OPTION_FROM_ABI);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Set up globals to generate code for the ISA or processor
|
||||
|
|
@ -15436,26 +15281,16 @@ mips_set_tune (const struct mips_cpu_info *info)
|
|||
/* Implement TARGET_HANDLE_OPTION. */
|
||||
|
||||
static bool
|
||||
mips_handle_option (struct gcc_options *opts, struct gcc_options *opts_set,
|
||||
mips_handle_option (struct gcc_options *opts,
|
||||
struct gcc_options *opts_set ATTRIBUTE_UNUSED,
|
||||
const struct cl_decoded_option *decoded,
|
||||
location_t loc ATTRIBUTE_UNUSED)
|
||||
{
|
||||
size_t code = decoded->opt_index;
|
||||
const char *arg = decoded->arg;
|
||||
|
||||
gcc_assert (opts == &global_options);
|
||||
gcc_assert (opts_set == &global_options_set);
|
||||
|
||||
switch (code)
|
||||
{
|
||||
case OPT_march_:
|
||||
case OPT_mtune_:
|
||||
return mips_parse_cpu (arg) != 0;
|
||||
|
||||
case OPT_mips:
|
||||
mips_isa_option_info = mips_parse_cpu (ACONCAT (("mips", arg, NULL)));
|
||||
return mips_isa_option_info != 0;
|
||||
|
||||
case OPT_mno_flush_func:
|
||||
opts->x_mips_cache_flush_func = NULL;
|
||||
return true;
|
||||
|
|
@ -15472,6 +15307,9 @@ mips_option_override (void)
|
|||
{
|
||||
int i, start, regno, mode;
|
||||
|
||||
if (global_options_set.x_mips_isa_option)
|
||||
mips_isa_option_info = &mips_cpu_info_table[mips_isa_option];
|
||||
|
||||
/* Process flags as though we were generating non-MIPS16 code. */
|
||||
mips_base_mips16 = TARGET_MIPS16;
|
||||
target_flags &= ~MASK_MIPS16;
|
||||
|
|
@ -15499,8 +15337,8 @@ mips_option_override (void)
|
|||
Similar code was added to GAS 2.14 (see tc-mips.c:md_after_parse_args()).
|
||||
The GAS and GCC code should be kept in sync as much as possible. */
|
||||
|
||||
if (mips_arch_string != 0)
|
||||
mips_set_architecture (mips_parse_cpu (mips_arch_string));
|
||||
if (global_options_set.x_mips_arch_option)
|
||||
mips_set_architecture (mips_cpu_info_from_opt (mips_arch_option));
|
||||
|
||||
if (mips_isa_option_info != 0)
|
||||
{
|
||||
|
|
@ -15514,21 +15352,15 @@ mips_option_override (void)
|
|||
}
|
||||
|
||||
if (mips_arch_info == 0)
|
||||
{
|
||||
#ifdef MIPS_CPU_STRING_DEFAULT
|
||||
mips_set_architecture (mips_parse_cpu (MIPS_CPU_STRING_DEFAULT));
|
||||
#else
|
||||
mips_set_architecture (mips_cpu_info_from_isa (MIPS_ISA_DEFAULT));
|
||||
#endif
|
||||
}
|
||||
mips_set_architecture (mips_default_arch ());
|
||||
|
||||
if (ABI_NEEDS_64BIT_REGS && !ISA_HAS_64BIT_REGS)
|
||||
error ("%<-march=%s%> is not compatible with the selected ABI",
|
||||
mips_arch_info->name);
|
||||
|
||||
/* Optimize for mips_arch, unless -mtune selects a different processor. */
|
||||
if (mips_tune_string != 0)
|
||||
mips_set_tune (mips_parse_cpu (mips_tune_string));
|
||||
if (global_options_set.x_mips_tune_option)
|
||||
mips_set_tune (mips_cpu_info_from_opt (mips_tune_option));
|
||||
|
||||
if (mips_tune_info == 0)
|
||||
mips_set_tune (mips_arch_info);
|
||||
|
|
@ -15788,19 +15620,19 @@ mips_option_override (void)
|
|||
/* Default to working around R4000 errata only if the processor
|
||||
was selected explicitly. */
|
||||
if ((target_flags_explicit & MASK_FIX_R4000) == 0
|
||||
&& mips_matching_cpu_name_p (mips_arch_info->name, "r4000"))
|
||||
&& strcmp (mips_arch_info->name, "r4000") == 0)
|
||||
target_flags |= MASK_FIX_R4000;
|
||||
|
||||
/* Default to working around R4400 errata only if the processor
|
||||
was selected explicitly. */
|
||||
if ((target_flags_explicit & MASK_FIX_R4400) == 0
|
||||
&& mips_matching_cpu_name_p (mips_arch_info->name, "r4400"))
|
||||
&& strcmp (mips_arch_info->name, "r4400") == 0)
|
||||
target_flags |= MASK_FIX_R4400;
|
||||
|
||||
/* Default to working around R10000 errata only if the processor
|
||||
was selected explicitly. */
|
||||
if ((target_flags_explicit & MASK_FIX_R10000) == 0
|
||||
&& mips_matching_cpu_name_p (mips_arch_info->name, "r10000"))
|
||||
&& strcmp (mips_arch_info->name, "r10000") == 0)
|
||||
target_flags |= MASK_FIX_R10000;
|
||||
|
||||
/* Make sure that branch-likely instructions available when using
|
||||
|
|
|
|||
|
|
@ -572,13 +572,6 @@ struct mips_cpu_info {
|
|||
#define TARGET_FP_EXCEPTIONS_DEFAULT MASK_FP_EXCEPTIONS
|
||||
#endif
|
||||
|
||||
/* 'from-abi' makes a good default: you get whatever the ABI requires. */
|
||||
#ifndef MIPS_ISA_DEFAULT
|
||||
#ifndef MIPS_CPU_STRING_DEFAULT
|
||||
#define MIPS_CPU_STRING_DEFAULT "from-abi"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef IN_LIBGCC2
|
||||
#undef TARGET_64BIT
|
||||
/* Make this compile time constant for libgcc2 */
|
||||
|
|
|
|||
|
|
@ -59,7 +59,7 @@ Target Report Var(TARGET_MAD)
|
|||
Use PMC-style 'mad' instructions
|
||||
|
||||
march=
|
||||
Target RejectNegative Joined Var(mips_arch_string)
|
||||
Target RejectNegative Joined Var(mips_arch_option) ToLower Enum(mips_arch_opt_value)
|
||||
-march=ISA Generate code for the given ISA
|
||||
|
||||
mbranch-cost=
|
||||
|
|
@ -222,7 +222,7 @@ Target Report Var(TARGET_INTERLINK_MIPS16) Init(0)
|
|||
Generate code that can be safely linked with MIPS16 code.
|
||||
|
||||
mips
|
||||
Target RejectNegative Joined
|
||||
Target RejectNegative Joined ToLower Enum(mips_mips_opt_value) Var(mips_isa_option)
|
||||
-mipsN Generate code for ISA level N
|
||||
|
||||
mips16
|
||||
|
|
@ -339,7 +339,7 @@ Target Report Mask(SYNCI)
|
|||
Use synci instruction to invalidate i-cache
|
||||
|
||||
mtune=
|
||||
Target RejectNegative Joined Var(mips_tune_string)
|
||||
Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_value)
|
||||
-mtune=PROCESSOR Optimize the output for PROCESSOR
|
||||
|
||||
muninit-const-in-rodata
|
||||
|
|
|
|||
|
|
@ -1,4 +1,4 @@
|
|||
# Copyright (C) 2002, 2003, 2006 Free Software Foundation, Inc.
|
||||
# Copyright (C) 2002, 2003, 2006, 2011 Free Software Foundation, Inc.
|
||||
#
|
||||
# This file is part of GCC.
|
||||
#
|
||||
|
|
@ -39,3 +39,8 @@ fp-bit.c: $(srcdir)/config/fp-bit.c
|
|||
cat $(srcdir)/config/fp-bit.c >> fp-bit.c
|
||||
|
||||
LIB2_SIDITI_CONV_FUNCS=yes
|
||||
|
||||
$(srcdir)/config/mips/mips-tables.opt: $(srcdir)/config/mips/genopt.sh \
|
||||
$(srcdir)/config/mips/mips-cpus.def
|
||||
$(SHELL) $(srcdir)/config/mips/genopt.sh $(srcdir)/config/mips > \
|
||||
$(srcdir)/config/mips/mips-tables.opt
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue