rs6000.opt (no-fp-in-toc): Use Var not Mask.
* config/rs6000/rs6000.opt (no-fp-in-toc): Use Var not Mask.
(no-sum-in-toc): Same.
* config/rs6000/rs6000.c (rs6000_handle_option): Use new
variables.
* config/rs6000/sysv4.h (SUBTARGET_OVERRIDE_OPTIONS): Set
NO_FP_IN_TOC for -fPIC instead of mask.
* config/rs6000/t-aix43 (T_ADAFLAGS): Delete.
(BOOT_LDFLAGS): Delete.
(LDFLAGS): Delete.
* config/rs6000/t-aix52: Same.
* config/rs6000/rs6000.md (store_multiple_power): Delete.
(stmsi[345678]_power): New.
From-SVN: r112215
This commit is contained in:
David Edelsohn
David Edelsohn
parent
79a495f101
commit
d2894ab516
7 changed files with 139 additions and 34 deletions
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@ -1,3 +1,20 @@
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2006-03-19 David Edelsohn <edelsohn@gnu.org>
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* config/rs6000/rs6000.opt (no-fp-in-toc): Use Var not Mask.
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(no-sum-in-toc): Same.
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* config/rs6000/rs6000.c (rs6000_handle_option): Use new
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variables.
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* config/rs6000/sysv4.h (SUBTARGET_OVERRIDE_OPTIONS): Set
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NO_FP_IN_TOC for -fPIC instead of mask.
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* config/rs6000/t-aix43 (T_ADAFLAGS): Delete.
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(BOOT_LDFLAGS): Delete.
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(LDFLAGS): Delete.
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* config/rs6000/t-aix52: Same.
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* config/rs6000/rs6000.md (store_multiple_power): Delete.
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(stmsi[345678]_power): New.
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2006-03-17 Steve Ellcey <sje@cup.hp.com>
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* config/ia64/ia64.opt: Add empty line to end of file.
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@ -1635,10 +1635,10 @@ rs6000_handle_option (size_t code, const char *arg, int value)
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| MASK_PPC_GFXOPT | MASK_POWERPC64);
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break;
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case OPT_mfull_toc:
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target_flags &= ~(MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
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| MASK_NO_SUM_IN_TOC);
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target_flags_explicit |= (MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC
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| MASK_NO_SUM_IN_TOC);
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target_flags &= ~MASK_MINIMAL_TOC;
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TARGET_NO_FP_IN_TOC = 0;
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TARGET_NO_SUM_IN_TOC = 0;
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target_flags_explicit |= MASK_MINIMAL_TOC;
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#ifdef TARGET_USES_SYSV4_OPT
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/* Note, V.4 no longer uses a normal TOC, so make -mfull-toc, be
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just the same as -mminimal-toc. */
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@ -1681,8 +1681,8 @@ rs6000_handle_option (size_t code, const char *arg, int value)
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case OPT_mminimal_toc:
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if (value == 1)
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{
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target_flags &= ~(MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
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target_flags_explicit |= (MASK_NO_FP_IN_TOC | MASK_NO_SUM_IN_TOC);
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TARGET_NO_FP_IN_TOC = 0;
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TARGET_NO_SUM_IN_TOC = 0;
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}
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break;
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@ -8989,15 +8989,6 @@
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gen_rtx_REG (SImode, regno + i));
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}")
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(define_insn "*store_multiple_power"
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[(match_parallel 0 "store_multiple_operation"
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[(set (match_operand:SI 1 "indirect_operand" "=Q")
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(match_operand:SI 2 "gpc_reg_operand" "r"))
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(clobber (match_scratch:SI 3 "=q"))])]
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"TARGET_STRING && TARGET_POWER"
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"{stsi|stswi} %2,%P1,%O0"
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[(set_attr "type" "store")])
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(define_insn "*stmsi8"
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[(match_parallel 0 "store_multiple_operation"
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[(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
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@ -9105,6 +9096,114 @@
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"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
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"{stsi|stswi} %2,%1,%O0"
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[(set_attr "type" "store_ux")])
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(define_insn "*stmsi8_power"
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[(match_parallel 0 "store_multiple_operation"
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[(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
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(match_operand:SI 2 "gpc_reg_operand" "r"))
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(clobber (match_scratch:SI 3 "q"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
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(match_operand:SI 4 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
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(match_operand:SI 5 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
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(match_operand:SI 6 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
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(match_operand:SI 7 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
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(match_operand:SI 8 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
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(match_operand:SI 9 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 28)))
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(match_operand:SI 10 "gpc_reg_operand" "r"))])]
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"TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 9"
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"{stsi|stswi} %2,%1,%O0"
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[(set_attr "type" "store_ux")])
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(define_insn "*stmsi7_power"
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[(match_parallel 0 "store_multiple_operation"
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[(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
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(match_operand:SI 2 "gpc_reg_operand" "r"))
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(clobber (match_scratch:SI 3 "q"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
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(match_operand:SI 4 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
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(match_operand:SI 5 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
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(match_operand:SI 6 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
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(match_operand:SI 7 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
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(match_operand:SI 8 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 24)))
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(match_operand:SI 9 "gpc_reg_operand" "r"))])]
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"TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 8"
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"{stsi|stswi} %2,%1,%O0"
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[(set_attr "type" "store_ux")])
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(define_insn "*stmsi6_power"
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[(match_parallel 0 "store_multiple_operation"
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[(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
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(match_operand:SI 2 "gpc_reg_operand" "r"))
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(clobber (match_scratch:SI 3 "q"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
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(match_operand:SI 4 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
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(match_operand:SI 5 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
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(match_operand:SI 6 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
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(match_operand:SI 7 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 20)))
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(match_operand:SI 8 "gpc_reg_operand" "r"))])]
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"TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 7"
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"{stsi|stswi} %2,%1,%O0"
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[(set_attr "type" "store_ux")])
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(define_insn "*stmsi5_power"
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[(match_parallel 0 "store_multiple_operation"
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[(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
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(match_operand:SI 2 "gpc_reg_operand" "r"))
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(clobber (match_scratch:SI 3 "q"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
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(match_operand:SI 4 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
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(match_operand:SI 5 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
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(match_operand:SI 6 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 16)))
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(match_operand:SI 7 "gpc_reg_operand" "r"))])]
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"TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 6"
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"{stsi|stswi} %2,%1,%O0"
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[(set_attr "type" "store_ux")])
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(define_insn "*stmsi4_power"
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[(match_parallel 0 "store_multiple_operation"
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[(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
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(match_operand:SI 2 "gpc_reg_operand" "r"))
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(clobber (match_scratch:SI 3 "q"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
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(match_operand:SI 4 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
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(match_operand:SI 5 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 12)))
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(match_operand:SI 6 "gpc_reg_operand" "r"))])]
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"TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 5"
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"{stsi|stswi} %2,%1,%O0"
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[(set_attr "type" "store_ux")])
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(define_insn "*stmsi3_power"
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[(match_parallel 0 "store_multiple_operation"
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[(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))
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(match_operand:SI 2 "gpc_reg_operand" "r"))
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(clobber (match_scratch:SI 3 "q"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 4)))
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(match_operand:SI 4 "gpc_reg_operand" "r"))
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(set (mem:SI (plus:SI (match_dup 1) (const_int 8)))
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(match_operand:SI 5 "gpc_reg_operand" "r"))])]
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"TARGET_STRING && TARGET_POWER && XVECLEN (operands[0], 0) == 4"
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"{stsi|stswi} %2,%1,%O0"
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[(set_attr "type" "store_ux")])
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(define_expand "setmemsi"
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[(parallel [(set (match_operand:BLK 0 "" "")
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@ -140,19 +140,19 @@ Target Report Var(swdiv)
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Generate software floating point divide for better throughput
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mno-fp-in-toc
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Target Report RejectNegative Mask(NO_FP_IN_TOC)
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Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC)
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Do not place floating point constants in TOC
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mfp-in-toc
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Target Report RejectNegative InverseMask(NO_FP_IN_TOC)
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Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) VarExists
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Place floating point constants in TOC
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mno-sum-in-toc
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Target RejectNegative Mask(NO_SUM_IN_TOC)
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Target RejectNegative Var(TARGET_NO_SUM_IN_TOC)
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Do not place symbol+offset constants in TOC
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msum-in-toc
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Target RejectNegative InverseMask(NO_SUM_IN_TOC)
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Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) VarExists
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Place symbol+offset constants in TOC
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; Output only one TOC entry per module. Normally linking fails if
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@ -221,7 +221,10 @@ do { \
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\
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/* Treat -fPIC the same as -mrelocatable. */ \
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if (flag_pic > 1 && DEFAULT_ABI != ABI_AIX) \
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target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC | MASK_NO_FP_IN_TOC; \
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{ \
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target_flags |= MASK_RELOCATABLE | MASK_MINIMAL_TOC; \
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TARGET_NO_FP_IN_TOC = 1; \
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} \
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\
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else if (TARGET_RELOCATABLE) \
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flag_pic = 2; \
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@ -74,10 +74,3 @@ TARGET_LIBGCC2_CFLAGS = -mlong-double-128
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# Either 32-bit and 64-bit objects in archives.
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AR_FLAGS_FOR_TARGET = -X32_64
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# Compile Ada files with minimal-toc. The primary focus is gnatlib, so
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# that the library does not use nearly the entire TOC of applications
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# until gnatlib is built as a shared library on AIX. Compiling the
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# compiler with -mminimal-toc does not cause any harm.
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T_ADAFLAGS = -mminimal-toc
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BOOT_LDFLAGS = -Wl,-bbigtoc
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LDFLAGS = `case $(CC) in *gcc*) echo -Wl,-bbigtoc ;; esac;`
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@ -55,10 +55,3 @@ TARGET_LIBGCC2_CFLAGS = -mlong-double-128
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# Either 32-bit and 64-bit objects in archives.
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AR_FLAGS_FOR_TARGET = -X32_64
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# Compile Ada files with minimal-toc. The primary focus is gnatlib, so
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# that the library does not use nearly the entire TOC of applications
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# until gnatlib is built as a shared library on AIX. Compiling the
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# compiler with -mminimal-toc does not cause any harm.
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T_ADAFLAGS = -mminimal-toc
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BOOT_LDFLAGS = -Wl,-bbigtoc
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LDFLAGS = `case $(CC) in *gcc*) echo -Wl,-bbigtoc ;; esac;`
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