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i386.h (enum reg_class): Rename MASK_REGS to ALL_MASK_REGS and MASK_EVEX_REGS to MASK_REGS.

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* config/i386/i386.h (enum reg_class): Rename MASK_REGS to
	ALL_MASK_REGS and MASK_EVEX_REGS to MASK_REGS.
	(MASK_CLASS_P): Update for rename.
	(MAYBE_MASK_CLASS_P): Ditto.
	(REG_CLASS_NAMES): Update.
	(REG_CLASS_CONTENT): Update.
	* config/i386/i386.c (regclass_map): Update for MASK_REG
	and ALL_MASK_REGS rename.
	* config/i386/constraints.md (Yk): Update for rename.
	(k): Ditto.

	* config/i386/i386.h (enum reg_class): Remove
	EVEX_SSE_REGS and MOD4_SSE_REGS.
	(REG_CLASS_NAMES): Update.
	(REG_CLASS_CONTENT): Update.
	* config/i386/i386.c (regclass_map): Declare AVX-512 SSE
	registers as ALL_SSE_REGS.
	(ix86_additional_allocno_class_p): Remove.
	(TARGET_ADDITIONAL_ALLOCNO_CLASS_P): Remove.
	(ix86_register_priority): Lower priority of EVEX SSE registers.
	Use IN_RANGE macro where appropriate.
	(ix86_hard_regno_mode_ok): Merge AVX-5124FMAPS and
	AVX-5124VNNIW checks.
	(ix86_modes_tieable_p): Tie 512-bit SSE modes.
	* config/i386/sse.md (avx5124fmaddps_4fmaddps)
	(avx5124fmaddps_4fmaddps_mask, avx5124fmaddps_4fmaddps_maskz)
	(avx5124fmaddps_4fmaddss, avx5124fmaddps_4fmaddss_mask)
	(avx5124fmaddps_4fmaddss_maskz, avx5124fmaddps_4fnmaddps)
	(avx5124fmaddps_4fnmaddps_mask, avx5124fmaddps_4fnmaddps_maskz)
	(avx5124fmaddps_4fnmaddss, avx5124fmaddps_4fnmaddss_mask)
	(avx5124fmaddps_4fnmaddss_maskz, avx5124vnniw_vp4dpwssd)
	(avx5124vnniw_vp4dpwssd_mask, avx5124vnniw_vp4dpwssd_maskz)
	(avx5124vnniw_vp4dpwssds, avx5124vnniw_vp4dpwssds_mask)
	(avx5124vnniw_vp4dpwssds_maskz): Use "v" instead of "Yh" constraint.
	* config/i386/constraints.md (Yh): Remove.

	* config/i386/i386.c (regclass_map): Declare integer REX registers
        as GENERAL_REGS.

From-SVN: r264516
This commit is contained in:
Uros Bizjak 2018-09-23 17:37:30 +02:00
parent 839837b036
commit d18cbbf677
5 changed files with 137 additions and 113 deletions
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57
gcc/ChangeLog
View file

@ -1,3 +1,48 @@
2018-09-23 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.h (enum reg_class): Rename MASK_REGS to
ALL_MASK_REGS and MASK_EVEX_REGS to MASK_REGS.
(MASK_CLASS_P): Update for rename.
(MAYBE_MASK_CLASS_P): Ditto.
(REG_CLASS_NAMES): Update.
(REG_CLASS_CONTENT): Update.
* config/i386/i386.c (regclass_map): Update for MASK_REG
and ALL_MASK_REGS rename.
* config/i386/constraints.md (Yk): Update for rename.
(k): Ditto.
2018-09-23 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.h (enum reg_class): Remove
EVEX_SSE_REGS and MOD4_SSE_REGS.
(REG_CLASS_NAMES): Update.
(REG_CLASS_CONTENT): Update.
* config/i386/i386.c (regclass_map): Declare AVX-512 SSE
registers as ALL_SSE_REGS.
(ix86_additional_allocno_class_p): Remove.
(TARGET_ADDITIONAL_ALLOCNO_CLASS_P): Remove.
(ix86_register_priority): Lower priority of EVEX SSE registers.
Use IN_RANGE macro where appropriate.
(ix86_hard_regno_mode_ok): Merge AVX-5124FMAPS and
AVX-5124VNNIW checks.
(ix86_modes_tieable_p): Tie 512-bit SSE modes.
* config/i386/sse.md (avx5124fmaddps_4fmaddps)
(avx5124fmaddps_4fmaddps_mask, avx5124fmaddps_4fmaddps_maskz)
(avx5124fmaddps_4fmaddss, avx5124fmaddps_4fmaddss_mask)
(avx5124fmaddps_4fmaddss_maskz, avx5124fmaddps_4fnmaddps)
(avx5124fmaddps_4fnmaddps_mask, avx5124fmaddps_4fnmaddps_maskz)
(avx5124fmaddps_4fnmaddss, avx5124fmaddps_4fnmaddss_mask)
(avx5124fmaddps_4fnmaddss_maskz, avx5124vnniw_vp4dpwssd)
(avx5124vnniw_vp4dpwssd_mask, avx5124vnniw_vp4dpwssd_maskz)
(avx5124vnniw_vp4dpwssds, avx5124vnniw_vp4dpwssds_mask)
(avx5124vnniw_vp4dpwssds_maskz): Use "v" instead of "Yh" constraint.
* config/i386/constraints.md (Yh): Remove.
2018-09-23 Uros Bizjak <ubizjak@gmail.com>
* config/i386/i386.c (regclass_map): Declare integer REX registers
as GENERAL_REGS.
2018-09-23 Gerald Pfeifer <gerald@pfeifer.com>
* doc/service.texi (Service): Switch the fsf.org link to https.
@ -25,7 +70,7 @@
to_update_switch_stmts into vr_values class member functions.
* tree-vrp.h (switch_update, to_remove_edges): Remove declarations.
(to_update_switch_stmts): Likewise.
* vr-values.c: Include cfghooks.h.
* vr-values.c: Include cfghooks.h.
(vr_values::vr_values): Initialize to_remove_edges and
to_update_switch_stmts.
(vr_values::~vr_values): Verify to_remove_edges and
@ -776,7 +821,7 @@
* config/aarch64/aarch64.h (TARGET_COMPUTE_FRAME_LAYOUT): Define.
* config/aarch64/aarch64.c (aarch64_expand_prologue): Remove
aarch64_layout_frame call.
aarch64_layout_frame call.
(aarch64_expand_epilogue): Likewise.
(aarch64_initial_elimination_offset): Likewise.
(aarch64_get_separate_components): Likewise.
@ -1329,7 +1374,8 @@
* bb-reorder.c (edge_order): Convert to C-qsort-style
tri-state comparator.
(reorder_basic_blocks_simple): Change std::stable_sort to gcc_stablesort.
(reorder_basic_blocks_simple): Change std::stable_sort to
gcc_stablesort.
2018-09-03 Alexander Monakov <amonakov@ispras.ru>
@ -1927,7 +1973,8 @@
* gimple-fold.c (gimple_fold_stmt_to_constant_1): Likewise.
* gimple-low.c (lower_stmt): Likewise.
* gimple-pretty-print.c (dump_gimple_call): Likewise.
* gimple-ssa-warn-restrict.c (wrestrict_dom_walker::check_call): Likewise.
* gimple-ssa-warn-restrict.c (wrestrict_dom_walker::check_call):
Likewise.
* gimple.c (gimple_build_call_from_tree): Likewise.
(gimple_call_builtin_p): Likewise.
(gimple_call_combined_fn): Likewise.
@ -2495,7 +2542,7 @@
* config/darwin10.h (LINK_GCC_C_SEQUENCE_SPEC): Adjust to use the
Darwin10-specific unwinder-shim.
* config/darwin12.h (LINK_GCC_C_SEQUENCE_SPEC): Remove.
* config/rs6000/darwin.h (DARWIN_CRT1_SPEC, DARWIN_DYLIB1_SPEC):
* config/rs6000/darwin.h (DARWIN_CRT1_SPEC, DARWIN_DYLIB1_SPEC):
New to cater for Darwin10 Rosetta.
2018-08-22 Iain Sandoe <iain@sandoe.co.uk>

7
gcc/config/i386/constraints.md
View file

@ -78,10 +78,10 @@
"TARGET_80387 || TARGET_FLOAT_RETURNS_IN_80387 ? FP_SECOND_REG : NO_REGS"
"Second from top of 80387 floating-point stack (@code{%st(1)}).")
(define_register_constraint "Yk" "TARGET_AVX512F ? MASK_EVEX_REGS : NO_REGS"
(define_register_constraint "Yk" "TARGET_AVX512F ? MASK_REGS : NO_REGS"
"@internal Any mask register that can be used as predicate, i.e. k1-k7.")
(define_register_constraint "k" "TARGET_AVX512F ? MASK_REGS : NO_REGS"
(define_register_constraint "k" "TARGET_AVX512F ? ALL_MASK_REGS : NO_REGS"
"@internal Any mask register.")
;; Vector registers (also used for plain floating point nowadays).
@ -146,9 +146,6 @@
"TARGET_AVX512VL ? ALL_SSE_REGS : TARGET_SSE ? SSE_REGS : NO_REGS"
"@internal For AVX512VL, any EVEX encodable SSE register (@code{%xmm0-%xmm31}), otherwise any SSE register.")
(define_register_constraint "Yh" "TARGET_AVX512F ? MOD4_SSE_REGS : NO_REGS"
"@internal Any EVEX encodable SSE register, which has number factor of four.")
;; We use the B prefix to denote any number of internal operands:
;; f FLAGS_REG
;; g GOT memory operand.

63
gcc/config/i386/i386.c
View file

@ -244,25 +244,25 @@ enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
/* flags, fpsr, fpcr, frame */
NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
/* SSE registers */
SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
SSE_REGS, SSE_REGS,
SSE_FIRST_REG, SSE_REGS, SSE_REGS, SSE_REGS,
SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
/* MMX registers */
MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
MMX_REGS, MMX_REGS,
MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
/* REX registers */
NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
NON_Q_REGS, NON_Q_REGS, NON_Q_REGS, NON_Q_REGS,
GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
GENERAL_REGS, GENERAL_REGS, GENERAL_REGS, GENERAL_REGS,
/* SSE REX registers */
SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
SSE_REGS, SSE_REGS,
SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
/* AVX-512 SSE registers */
EVEX_SSE_REGS, EVEX_SSE_REGS, EVEX_SSE_REGS, EVEX_SSE_REGS,
EVEX_SSE_REGS, EVEX_SSE_REGS, EVEX_SSE_REGS, EVEX_SSE_REGS,
EVEX_SSE_REGS, EVEX_SSE_REGS, EVEX_SSE_REGS, EVEX_SSE_REGS,
EVEX_SSE_REGS, EVEX_SSE_REGS, EVEX_SSE_REGS, EVEX_SSE_REGS,
ALL_SSE_REGS, ALL_SSE_REGS, ALL_SSE_REGS, ALL_SSE_REGS,
ALL_SSE_REGS, ALL_SSE_REGS, ALL_SSE_REGS, ALL_SSE_REGS,
ALL_SSE_REGS, ALL_SSE_REGS, ALL_SSE_REGS, ALL_SSE_REGS,
ALL_SSE_REGS, ALL_SSE_REGS, ALL_SSE_REGS, ALL_SSE_REGS,
/* Mask registers. */
MASK_REGS, MASK_EVEX_REGS, MASK_EVEX_REGS, MASK_EVEX_REGS,
MASK_EVEX_REGS, MASK_EVEX_REGS, MASK_EVEX_REGS, MASK_EVEX_REGS
ALL_MASK_REGS, MASK_REGS, MASK_REGS, MASK_REGS,
MASK_REGS, MASK_REGS, MASK_REGS, MASK_REGS
};
/* The "default" register map used in 32bit mode. */
@ -10858,15 +10858,6 @@ ix86_hard_regno_scratch_ok (unsigned int regno)
&& df_regs_ever_live_p (regno)));
}
/* Return true if register class CL should be an additional allocno
class. */
static bool
ix86_additional_allocno_class_p (reg_class_t cl)
{
return cl == MOD4_SSE_REGS;
}
/* Return TRUE if we need to save REGNO. */
static bool
@ -39017,12 +39008,14 @@ ix86_register_priority (int hard_regno)
return 1;
/* New x86-64 int registers result in bigger code size. Discourage
them. */
if (FIRST_REX_INT_REG <= hard_regno && hard_regno <= LAST_REX_INT_REG)
if (IN_RANGE (hard_regno, FIRST_REX_INT_REG, LAST_REX_INT_REG))
return 2;
/* New x86-64 SSE registers result in bigger code size. Discourage
them. */
if (FIRST_REX_SSE_REG <= hard_regno && hard_regno <= LAST_REX_SSE_REG)
if (IN_RANGE (hard_regno, FIRST_REX_SSE_REG, LAST_REX_SSE_REG))
return 2;
if (IN_RANGE (hard_regno, FIRST_EXT_REX_SSE_REG, LAST_EXT_REX_SSE_REG))
return 1;
/* Usage of AX register results in smaller code. Prefer it. */
if (hard_regno == AX_REG)
return 4;
@ -39659,16 +39652,11 @@ ix86_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
|| VALID_AVX512F_SCALAR_MODE (mode)))
return true;
/* For AVX-5124FMAPS allow V64SFmode for special regnos. */
/* For AVX-5124FMAPS or AVX-5124VNNIW
allow V64SF and V64SI modes for special regnos. */
if ((TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW)
&& MOD4_SSE_REGNO_P (regno)
&& mode == V64SFmode)
return true;
/* For AVX-5124VNNIW allow V64SImode for special regnos. */
if ((TARGET_AVX5124FMAPS || TARGET_AVX5124VNNIW)
&& MOD4_SSE_REGNO_P (regno)
&& mode == V64SImode)
&& (mode == V64SFmode || mode == V64SImode)
&& MOD4_SSE_REGNO_P (regno))
return true;
/* TODO check for QI/HI scalars. */
@ -39796,6 +39784,10 @@ ix86_modes_tieable_p (machine_mode mode1, machine_mode mode2)
/* If MODE2 is only appropriate for an SSE register, then tie with
any other mode acceptable to SSE registers. */
if (GET_MODE_SIZE (mode2) == 64
&& ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
return (GET_MODE_SIZE (mode1) == 64
&& ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode1));
if (GET_MODE_SIZE (mode2) == 32
&& ix86_hard_regno_mode_ok (FIRST_SSE_REG, mode2))
return (GET_MODE_SIZE (mode1) == 32
@ -51113,9 +51105,6 @@ ix86_run_selftests (void)
#undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS
#define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1
#undef TARGET_ADDITIONAL_ALLOCNO_CLASS_P
#define TARGET_ADDITIONAL_ALLOCNO_CLASS_P ix86_additional_allocno_class_p
#undef TARGET_ADDR_SPACE_ZERO_ADDRESS_VALID
#define TARGET_ADDR_SPACE_ZERO_ADDRESS_VALID ix86_addr_space_zero_address_valid

87
gcc/config/i386/i386.h
View file

@ -1315,10 +1315,6 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
For any two classes, it is very desirable that there be another
class that represents their union.
It might seem that class BREG is unnecessary, since no useful 386
opcode needs reg %ebx. But some systems pass args to the OS in ebx,
and the "b" register constraint is useful in asms for syscalls.
The flags, fpsr and fpcr registers are in no class. */
enum reg_class
@ -1339,7 +1335,6 @@ enum reg_class
SSE_FIRST_REG,
NO_REX_SSE_REGS,
SSE_REGS,
EVEX_SSE_REGS,
ALL_SSE_REGS,
MMX_REGS,
FP_TOP_SSE_REGS,
@ -1348,10 +1343,10 @@ enum reg_class
FLOAT_INT_REGS,
INT_SSE_REGS,
FLOAT_INT_SSE_REGS,
MASK_EVEX_REGS,
MASK_REGS,
MOD4_SSE_REGS,
ALL_REGS, LIM_REG_CLASSES
ALL_MASK_REGS,
ALL_REGS,
LIM_REG_CLASSES
};
#define N_REG_CLASSES ((int) LIM_REG_CLASSES)
@ -1365,7 +1360,7 @@ enum reg_class
#define MMX_CLASS_P(CLASS) \
((CLASS) == MMX_REGS)
#define MASK_CLASS_P(CLASS) \
reg_class_subset_p ((CLASS), MASK_REGS)
reg_class_subset_p ((CLASS), ALL_MASK_REGS)
#define MAYBE_INTEGER_CLASS_P(CLASS) \
reg_classes_intersect_p ((CLASS), GENERAL_REGS)
#define MAYBE_FLOAT_CLASS_P(CLASS) \
@ -1375,7 +1370,7 @@ enum reg_class
#define MAYBE_MMX_CLASS_P(CLASS) \
reg_classes_intersect_p ((CLASS), MMX_REGS)
#define MAYBE_MASK_CLASS_P(CLASS) \
reg_classes_intersect_p ((CLASS), MASK_REGS)
reg_classes_intersect_p ((CLASS), ALL_MASK_REGS)
#define Q_CLASS_P(CLASS) \
reg_class_subset_p ((CLASS), Q_REGS)
@ -1401,7 +1396,6 @@ enum reg_class
"SSE_FIRST_REG", \
"NO_REX_SSE_REGS", \
"SSE_REGS", \
"EVEX_SSE_REGS", \
"ALL_SSE_REGS", \
"MMX_REGS", \
"FP_TOP_SSE_REGS", \
@ -1410,9 +1404,8 @@ enum reg_class
"FLOAT_INT_REGS", \
"INT_SSE_REGS", \
"FLOAT_INT_SSE_REGS", \
"MASK_EVEX_REGS", \
"MASK_REGS", \
"MOD4_SSE_REGS", \
"ALL_MASK_REGS", \
"ALL_REGS" }
/* Define which registers fit in which classes. This is an initializer
@ -1421,41 +1414,39 @@ enum reg_class
Note that CLOBBERED_REGS are calculated by
TARGET_CONDITIONAL_REGISTER_USAGE. */
#define REG_CLASS_CONTENTS \
{ { 0x00, 0x0, 0x0 }, \
{ 0x01, 0x0, 0x0 }, /* AREG */ \
{ 0x02, 0x0, 0x0 }, /* DREG */ \
{ 0x04, 0x0, 0x0 }, /* CREG */ \
{ 0x08, 0x0, 0x0 }, /* BREG */ \
{ 0x10, 0x0, 0x0 }, /* SIREG */ \
{ 0x20, 0x0, 0x0 }, /* DIREG */ \
{ 0x03, 0x0, 0x0 }, /* AD_REGS */ \
{ 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \
{ 0x0f, 0x0, 0x0 }, /* Q_REGS */ \
{ 0x1100f0, 0x1fe0, 0x0 }, /* NON_Q_REGS */ \
{ 0x7e, 0x1fe0, 0x0 }, /* TLS_GOTBASE_REGS */ \
{ 0x7f, 0x1fe0, 0x0 }, /* INDEX_REGS */ \
{ 0x1100ff, 0x0, 0x0 }, /* LEGACY_REGS */ \
{ 0x1100ff, 0x1fe0, 0x0 }, /* GENERAL_REGS */ \
{ 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \
{ 0x0200, 0x0, 0x0 }, /* FP_SECOND_REG */ \
{ 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \
{ 0x200000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \
{ 0x1fe00000, 0x000000, 0x0 }, /* NO_REX_SSE_REGS */ \
{ 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \
{ 0x0,0xffe00000, 0x1f }, /* EVEX_SSE_REGS */ \
{ 0x1fe00000,0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \
{ 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \
{ 0x1fe00100,0xffffe000, 0x1f }, /* FP_TOP_SSE_REG */ \
{ 0x1fe00200,0xffffe000, 0x1f }, /* FP_SECOND_SSE_REG */ \
{ 0x1fe0ff00,0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \
{ 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \
{ 0x1ff100ff,0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \
{ 0x1ff1ffff,0xffffffe0, 0x1f }, /* FLOAT_INT_SSE_REGS */ \
{ 0x0, 0x0, 0x1fc0 }, /* MASK_EVEX_REGS */ \
{ 0x0, 0x0, 0x1fe0 }, /* MASK_REGS */ \
{ 0x1fe00000,0xffffe000, 0x1f }, /* MOD4_SSE_REGS */ \
{ 0xffffffff,0xffffffff,0x1ffff } \
#define REG_CLASS_CONTENTS \
{ { 0x0, 0x0, 0x0 }, /* NO_REGS */ \
{ 0x01, 0x0, 0x0 }, /* AREG */ \
{ 0x02, 0x0, 0x0 }, /* DREG */ \
{ 0x04, 0x0, 0x0 }, /* CREG */ \
{ 0x08, 0x0, 0x0 }, /* BREG */ \
{ 0x10, 0x0, 0x0 }, /* SIREG */ \
{ 0x20, 0x0, 0x0 }, /* DIREG */ \
{ 0x03, 0x0, 0x0 }, /* AD_REGS */ \
{ 0x07, 0x0, 0x0 }, /* CLOBBERED_REGS */ \
{ 0x0f, 0x0, 0x0 }, /* Q_REGS */ \
{ 0x1100f0, 0x0, 0x0 }, /* NON_Q_REGS */ \
{ 0x7e, 0x1fe0, 0x0 }, /* TLS_GOTBASE_REGS */ \
{ 0x7f, 0x1fe0, 0x0 }, /* INDEX_REGS */ \
{ 0x1100ff, 0x0, 0x0 }, /* LEGACY_REGS */ \
{ 0x1100ff, 0x1fe0, 0x0 }, /* GENERAL_REGS */ \
{ 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \
{ 0x0200, 0x0, 0x0 }, /* FP_SECOND_REG */ \
{ 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \
{ 0x200000, 0x0, 0x0 }, /* SSE_FIRST_REG */ \
{ 0x1fe00000, 0x0, 0x0 }, /* NO_REX_SSE_REGS */ \
{ 0x1fe00000, 0x1fe000, 0x0 }, /* SSE_REGS */ \
{ 0x1fe00000, 0xffffe000, 0x1f }, /* ALL_SSE_REGS */ \
{ 0xe0000000, 0x1f, 0x0 }, /* MMX_REGS */ \
{ 0x1fe00100, 0xffffe000, 0x1f }, /* FP_TOP_SSE_REG */ \
{ 0x1fe00200, 0xffffe000, 0x1f }, /* FP_SECOND_SSE_REG */ \
{ 0x1fe0ff00, 0xffffe000, 0x1f }, /* FLOAT_SSE_REGS */ \
{ 0x11ffff, 0x1fe0, 0x0 }, /* FLOAT_INT_REGS */ \
{ 0x1ff100ff, 0xffffffe0, 0x1f }, /* INT_SSE_REGS */ \
{ 0x1ff1ffff, 0xffffffe0, 0x1f }, /* FLOAT_INT_SSE_REGS */ \
{ 0x0, 0x0, 0x1fc0 }, /* MASK_REGS */ \
{ 0x0, 0x0, 0x1fe0 }, /* ALL_MASK_REGS */ \
{ 0xffffffff, 0xffffffff, 0x1fff } /* ALL_REGS */ \
}
/* The same information, inverted:

36
gcc/config/i386/sse.md
View file

@ -19951,7 +19951,7 @@
[(set (match_operand:V16SF 0 "register_operand" "=v")
(unspec:V16SF
[(match_operand:V16SF 1 "register_operand" "0")
(match_operand:V64SF 2 "register_operand" "Yh")
(match_operand:V64SF 2 "register_operand" "v")
(match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FMADD))]
"TARGET_AVX5124FMAPS"
"v4fmaddps\t{%3, %g2, %0|%0, %g2, %3}"
@ -19963,7 +19963,7 @@
[(set (match_operand:V16SF 0 "register_operand" "=v")
(vec_merge:V16SF
(unspec:V16SF
[(match_operand:V64SF 1 "register_operand" "Yh")
[(match_operand:V64SF 1 "register_operand" "v")
(match_operand:V4SF 2 "memory_operand" "m")] UNSPEC_VP4FMADD)
(match_operand:V16SF 3 "register_operand" "0")
(match_operand:HI 4 "register_operand" "Yk")))]
@ -19978,7 +19978,7 @@
(vec_merge:V16SF
(unspec:V16SF
[(match_operand:V16SF 1 "register_operand" "0")
(match_operand:V64SF 2 "register_operand" "Yh")
(match_operand:V64SF 2 "register_operand" "v")
(match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FMADD)
(match_operand:V16SF 4 "const0_operand" "C")
(match_operand:HI 5 "register_operand" "Yk")))]
@ -19992,7 +19992,7 @@
[(set (match_operand:V4SF 0 "register_operand" "=v")
(unspec:V4SF
[(match_operand:V4SF 1 "register_operand" "0")
(match_operand:V64SF 2 "register_operand" "Yh")
(match_operand:V64SF 2 "register_operand" "v")
(match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FMADD))]
"TARGET_AVX5124FMAPS"
"v4fmaddss\t{%3, %x2, %0|%0, %x2, %3}"
@ -20004,7 +20004,7 @@
[(set (match_operand:V4SF 0 "register_operand" "=v")
(vec_merge:V4SF
(unspec:V4SF
[(match_operand:V64SF 1 "register_operand" "Yh")
[(match_operand:V64SF 1 "register_operand" "v")
(match_operand:V4SF 2 "memory_operand" "m")] UNSPEC_VP4FMADD)
(match_operand:V4SF 3 "register_operand" "0")
(match_operand:QI 4 "register_operand" "Yk")))]
@ -20019,7 +20019,7 @@
(vec_merge:V4SF
(unspec:V4SF
[(match_operand:V4SF 1 "register_operand" "0")
(match_operand:V64SF 2 "register_operand" "Yh")
(match_operand:V64SF 2 "register_operand" "v")
(match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FMADD)
(match_operand:V4SF 4 "const0_operand" "C")
(match_operand:QI 5 "register_operand" "Yk")))]
@ -20033,7 +20033,7 @@
[(set (match_operand:V16SF 0 "register_operand" "=v")
(unspec:V16SF
[(match_operand:V16SF 1 "register_operand" "0")
(match_operand:V64SF 2 "register_operand" "Yh")
(match_operand:V64SF 2 "register_operand" "v")
(match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FNMADD))]
"TARGET_AVX5124FMAPS"
"v4fnmaddps\t{%3, %g2, %0|%0, %g2, %3}"
@ -20045,7 +20045,7 @@
[(set (match_operand:V16SF 0 "register_operand" "=v")
(vec_merge:V16SF
(unspec:V16SF
[(match_operand:V64SF 1 "register_operand" "Yh")
[(match_operand:V64SF 1 "register_operand" "v")
(match_operand:V4SF 2 "memory_operand" "m")] UNSPEC_VP4FNMADD)
(match_operand:V16SF 3 "register_operand" "0")
(match_operand:HI 4 "register_operand" "Yk")))]
@ -20060,7 +20060,7 @@
(vec_merge:V16SF
(unspec:V16SF
[(match_operand:V16SF 1 "register_operand" "0")
(match_operand:V64SF 2 "register_operand" "Yh")
(match_operand:V64SF 2 "register_operand" "v")
(match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FNMADD)
(match_operand:V16SF 4 "const0_operand" "C")
(match_operand:HI 5 "register_operand" "Yk")))]
@ -20074,7 +20074,7 @@
[(set (match_operand:V4SF 0 "register_operand" "=v")
(unspec:V4SF
[(match_operand:V4SF 1 "register_operand" "0")
(match_operand:V64SF 2 "register_operand" "Yh")
(match_operand:V64SF 2 "register_operand" "v")
(match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FNMADD))]
"TARGET_AVX5124FMAPS"
"v4fnmaddss\t{%3, %x2, %0|%0, %x2, %3}"
@ -20086,7 +20086,7 @@
[(set (match_operand:V4SF 0 "register_operand" "=v")
(vec_merge:V4SF
(unspec:V4SF
[(match_operand:V64SF 1 "register_operand" "Yh")
[(match_operand:V64SF 1 "register_operand" "v")
(match_operand:V4SF 2 "memory_operand" "m")] UNSPEC_VP4FNMADD)
(match_operand:V4SF 3 "register_operand" "0")
(match_operand:QI 4 "register_operand" "Yk")))]
@ -20101,7 +20101,7 @@
(vec_merge:V4SF
(unspec:V4SF
[(match_operand:V4SF 1 "register_operand" "0")
(match_operand:V64SF 2 "register_operand" "Yh")
(match_operand:V64SF 2 "register_operand" "v")
(match_operand:V4SF 3 "memory_operand" "m")] UNSPEC_VP4FNMADD)
(match_operand:V4SF 4 "const0_operand" "C")
(match_operand:QI 5 "register_operand" "Yk")))]
@ -20115,7 +20115,7 @@
[(set (match_operand:V16SI 0 "register_operand" "=v")
(unspec:V16SI
[(match_operand:V16SI 1 "register_operand" "0")
(match_operand:V64SI 2 "register_operand" "Yh")
(match_operand:V64SI 2 "register_operand" "v")
(match_operand:V4SI 3 "memory_operand" "m")] UNSPEC_VP4DPWSSD))]
"TARGET_AVX5124VNNIW"
"vp4dpwssd\t{%3, %g2, %0|%0, %g2, %3}"
@ -20127,7 +20127,7 @@
[(set (match_operand:V16SI 0 "register_operand" "=v")
(vec_merge:V16SI
(unspec:V16SI
[(match_operand:V64SI 1 "register_operand" "Yh")
[(match_operand:V64SI 1 "register_operand" "v")
(match_operand:V4SI 2 "memory_operand" "m")] UNSPEC_VP4DPWSSD)
(match_operand:V16SI 3 "register_operand" "0")
(match_operand:HI 4 "register_operand" "Yk")))]
@ -20142,7 +20142,7 @@
(vec_merge:V16SI
(unspec:V16SI
[(match_operand:V16SI 1 "register_operand" "0")
(match_operand:V64SI 2 "register_operand" "Yh")
(match_operand:V64SI 2 "register_operand" "v")
(match_operand:V4SI 3 "memory_operand" "m")] UNSPEC_VP4DPWSSD)
(match_operand:V16SI 4 "const0_operand" "C")
(match_operand:HI 5 "register_operand" "Yk")))]
@ -20156,7 +20156,7 @@
[(set (match_operand:V16SI 0 "register_operand" "=v")
(unspec:V16SI
[(match_operand:V16SI 1 "register_operand" "0")
(match_operand:V64SI 2 "register_operand" "Yh")
(match_operand:V64SI 2 "register_operand" "v")
(match_operand:V4SI 3 "memory_operand" "m")] UNSPEC_VP4DPWSSDS))]
"TARGET_AVX5124VNNIW"
"vp4dpwssds\t{%3, %g2, %0|%0, %g2, %3}"
@ -20168,7 +20168,7 @@
[(set (match_operand:V16SI 0 "register_operand" "=v")
(vec_merge:V16SI
(unspec:V16SI
[(match_operand:V64SI 1 "register_operand" "Yh")
[(match_operand:V64SI 1 "register_operand" "v")
(match_operand:V4SI 2 "memory_operand" "m")] UNSPEC_VP4DPWSSDS)
(match_operand:V16SI 3 "register_operand" "0")
(match_operand:HI 4 "register_operand" "Yk")))]
@ -20183,7 +20183,7 @@
(vec_merge:V16SI
(unspec:V16SI
[(match_operand:V16SI 1 "register_operand" "0")
(match_operand:V64SI 2 "register_operand" "Yh")
(match_operand:V64SI 2 "register_operand" "v")
(match_operand:V4SI 3 "memory_operand" "m")] UNSPEC_VP4DPWSSDS)
(match_operand:V16SI 4 "const0_operand" "C")
(match_operand:HI 5 "register_operand" "Yk")))]