arm: MVE: Factorize all vcmp* integer patterns
After removing the signed and unsigned suffixes in the previous patches, we can now factorize the vcmp* patterns: there is no longer an asymmetry where operators do not have the same set of signed and unsigned variants. The will make maintenance easier. MVE has a different set of vector comparison operators than Neon, so we have to introduce dedicated iterators. 2021-05-10 Christophe Lyon <christophe.lyon@linaro.org> gcc/ * config/arm/iterators.md (MVE_COMPARISONS): New. (mve_cmp_op): New. (mve_cmp_type): New. * config/arm/mve.md (mve_vcmp<mve_cmp_op>q_<mode>): New, merge all mve_vcmp patterns. (mve_vcmpneq_<mode>, mve_vcmpcsq_n_<mode>, mve_vcmpcsq_<mode>) (mve_vcmpeqq_n_<mode>, mve_vcmpeqq_<mode>, mve_vcmpgeq_n_<mode>) (mve_vcmpgeq_<mode>, mve_vcmpgtq_n_<mode>, mve_vcmpgtq_<mode>) (mve_vcmphiq_n_<mode>, mve_vcmphiq_<mode>, mve_vcmpleq_n_<mode>) (mve_vcmpleq_<mode>, mve_vcmpltq_n_<mode>, mve_vcmpltq_<mode>) (mve_vcmpneq_n_<mode>, mve_vcmpltq_n_<mode>, mve_vcmpltq_<mode>) (mve_vcmpneq_n_<mode>): Remove.
This commit is contained in:
Christophe Lyon
parent
929056a768
commit
d083fbf72d
2 changed files with 27 additions and 231 deletions
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@ -285,6 +285,8 @@
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;; Comparisons for vc<cmp>
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(define_code_iterator COMPARISONS [eq gt ge le lt])
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;; Comparisons for MVE
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(define_code_iterator MVE_COMPARISONS [eq ge geu gt gtu le lt ne])
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;; A list of ...
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(define_code_iterator IOR_XOR [ior xor])
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@ -336,8 +338,14 @@
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(define_code_attr cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le")
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(gtu "gt") (geu "ge")])
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(define_code_attr mve_cmp_op [(eq "eq") (gt "gt") (ge "ge") (lt "lt") (le "le")
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(gtu "hi") (geu "cs") (ne "ne")])
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(define_code_attr cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")])
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(define_code_attr mve_cmp_type [(eq "i") (gt "s") (ge "s") (lt "s") (le "s")
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(gtu "u") (geu "u") (ne "i")])
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(define_code_attr vfml_op [(plus "a") (minus "s")])
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(define_code_attr ss_op [(ss_plus "qadd") (ss_minus "qsub")])
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@ -811,17 +811,30 @@
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(set_attr "length""8")])
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;;
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;; [vcmpneq_])
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;; [vcmpneq_, vcmpcsq_, vcmpeqq_, vcmpgeq_, vcmpgtq_, vcmphiq_, vcmpleq_, vcmpltq_])
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;;
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(define_insn "mve_vcmpneq_<mode>"
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(define_insn "mve_vcmp<mve_cmp_op>q_<mode>"
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[
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(set (match_operand:HI 0 "vpr_register_operand" "=Up")
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(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:MVE_2 2 "s_register_operand" "w")]
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VCMPNEQ))
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(MVE_COMPARISONS:HI (match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:MVE_2 2 "s_register_operand" "w")))
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]
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"TARGET_HAVE_MVE"
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"vcmp.i%#<V_sz_elem> ne, %q1, %q2"
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"vcmp.<mve_cmp_type>%#<V_sz_elem> <mve_cmp_op>, %q1, %q2"
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[(set_attr "type" "mve_move")
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])
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;;
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;; [vcmpcsq_n_, vcmpeqq_n_, vcmpgeq_n_, vcmpgtq_n_, vcmphiq_n_, vcmpleq_n_, vcmpltq_n_, vcmpneq_n_])
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;;
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(define_insn "mve_vcmp<mve_cmp_op>q_n_<mode>"
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[
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(set (match_operand:HI 0 "vpr_register_operand" "=Up")
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(MVE_COMPARISONS:HI (match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:<V_elem> 2 "s_register_operand" "r")))
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]
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"TARGET_HAVE_MVE"
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"vcmp.<mve_cmp_type>%#<V_sz_elem> <mve_cmp_op>, %q1, %2"
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[(set_attr "type" "mve_move")
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])
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@ -979,231 +992,6 @@
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"TARGET_HAVE_MVE && !BYTES_BIG_ENDIAN"
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)
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;;
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;; [vcmpcsq_n_])
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;;
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(define_insn "mve_vcmpcsq_n_<mode>"
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[
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(set (match_operand:HI 0 "vpr_register_operand" "=Up")
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(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:<V_elem> 2 "s_register_operand" "r")]
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VCMPCSQ_N_U))
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]
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"TARGET_HAVE_MVE"
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"vcmp.u%#<V_sz_elem> cs, %q1, %2"
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[(set_attr "type" "mve_move")
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])
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;;
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;; [vcmpcsq_])
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;;
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(define_insn "mve_vcmpcsq_<mode>"
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[
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(set (match_operand:HI 0 "vpr_register_operand" "=Up")
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(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:MVE_2 2 "s_register_operand" "w")]
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VCMPCSQ_U))
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]
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"TARGET_HAVE_MVE"
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"vcmp.u%#<V_sz_elem> cs, %q1, %q2"
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[(set_attr "type" "mve_move")
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])
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;;
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;; [vcmpeqq_n_])
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;;
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(define_insn "mve_vcmpeqq_n_<mode>"
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[
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(set (match_operand:HI 0 "vpr_register_operand" "=Up")
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(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:<V_elem> 2 "s_register_operand" "r")]
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VCMPEQQ_N))
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]
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"TARGET_HAVE_MVE"
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"vcmp.i%#<V_sz_elem> eq, %q1, %2"
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[(set_attr "type" "mve_move")
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])
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;;
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;; [vcmpeqq_])
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;;
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(define_insn "mve_vcmpeqq_<mode>"
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[
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(set (match_operand:HI 0 "vpr_register_operand" "=Up")
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(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:MVE_2 2 "s_register_operand" "w")]
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VCMPEQQ))
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]
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"TARGET_HAVE_MVE"
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"vcmp.i%#<V_sz_elem> eq, %q1, %q2"
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[(set_attr "type" "mve_move")
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])
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;;
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;; [vcmpgeq_n_])
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;;
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(define_insn "mve_vcmpgeq_n_<mode>"
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[
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(set (match_operand:HI 0 "vpr_register_operand" "=Up")
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(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:<V_elem> 2 "s_register_operand" "r")]
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VCMPGEQ_N_S))
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]
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"TARGET_HAVE_MVE"
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"vcmp.s%#<V_sz_elem> ge, %q1, %2"
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[(set_attr "type" "mve_move")
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])
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;;
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;; [vcmpgeq_])
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;;
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(define_insn "mve_vcmpgeq_<mode>"
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[
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(set (match_operand:HI 0 "vpr_register_operand" "=Up")
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(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:MVE_2 2 "s_register_operand" "w")]
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VCMPGEQ_S))
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]
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"TARGET_HAVE_MVE"
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"vcmp.s%#<V_sz_elem> ge, %q1, %q2"
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[(set_attr "type" "mve_move")
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])
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;;
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;; [vcmpgtq_n_])
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;;
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(define_insn "mve_vcmpgtq_n_<mode>"
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[
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(set (match_operand:HI 0 "vpr_register_operand" "=Up")
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(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:<V_elem> 2 "s_register_operand" "r")]
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VCMPGTQ_N_S))
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]
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"TARGET_HAVE_MVE"
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"vcmp.s%#<V_sz_elem> gt, %q1, %2"
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[(set_attr "type" "mve_move")
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])
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;;
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;; [vcmpgtq_])
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;;
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(define_insn "mve_vcmpgtq_<mode>"
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[
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(set (match_operand:HI 0 "vpr_register_operand" "=Up")
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(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:MVE_2 2 "s_register_operand" "w")]
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VCMPGTQ_S))
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]
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"TARGET_HAVE_MVE"
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"vcmp.s%#<V_sz_elem> gt, %q1, %q2"
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[(set_attr "type" "mve_move")
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])
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;;
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;; [vcmphiq_n_])
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;;
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(define_insn "mve_vcmphiq_n_<mode>"
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[
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(set (match_operand:HI 0 "vpr_register_operand" "=Up")
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(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:<V_elem> 2 "s_register_operand" "r")]
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VCMPHIQ_N_U))
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]
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"TARGET_HAVE_MVE"
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"vcmp.u%#<V_sz_elem> hi, %q1, %2"
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[(set_attr "type" "mve_move")
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])
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;;
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;; [vcmphiq_])
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;;
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(define_insn "mve_vcmphiq_<mode>"
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[
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(set (match_operand:HI 0 "vpr_register_operand" "=Up")
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(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:MVE_2 2 "s_register_operand" "w")]
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VCMPHIQ_U))
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]
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"TARGET_HAVE_MVE"
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"vcmp.u%#<V_sz_elem> hi, %q1, %q2"
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[(set_attr "type" "mve_move")
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])
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;;
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;; [vcmpleq_n_])
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;;
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(define_insn "mve_vcmpleq_n_<mode>"
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[
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(set (match_operand:HI 0 "vpr_register_operand" "=Up")
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(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:<V_elem> 2 "s_register_operand" "r")]
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VCMPLEQ_N_S))
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]
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"TARGET_HAVE_MVE"
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"vcmp.s%#<V_sz_elem> le, %q1, %2"
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[(set_attr "type" "mve_move")
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])
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;;
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;; [vcmpleq_])
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;;
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(define_insn "mve_vcmpleq_<mode>"
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[
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(set (match_operand:HI 0 "vpr_register_operand" "=Up")
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(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:MVE_2 2 "s_register_operand" "w")]
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VCMPLEQ_S))
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]
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"TARGET_HAVE_MVE"
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"vcmp.s%#<V_sz_elem> le, %q1, %q2"
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[(set_attr "type" "mve_move")
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])
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;;
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;; [vcmpltq_n_])
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;;
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(define_insn "mve_vcmpltq_n_<mode>"
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[
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(set (match_operand:HI 0 "vpr_register_operand" "=Up")
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(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:<V_elem> 2 "s_register_operand" "r")]
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VCMPLTQ_N_S))
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]
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"TARGET_HAVE_MVE"
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"vcmp.s%#<V_sz_elem> lt, %q1, %2"
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[(set_attr "type" "mve_move")
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])
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;;
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;; [vcmpltq_])
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;;
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(define_insn "mve_vcmpltq_<mode>"
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[
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(set (match_operand:HI 0 "vpr_register_operand" "=Up")
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(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:MVE_2 2 "s_register_operand" "w")]
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VCMPLTQ_S))
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]
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"TARGET_HAVE_MVE"
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"vcmp.s%#<V_sz_elem> lt, %q1, %q2"
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[(set_attr "type" "mve_move")
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])
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;;
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;; [vcmpneq_n_])
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;;
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(define_insn "mve_vcmpneq_n_<mode>"
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[
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(set (match_operand:HI 0 "vpr_register_operand" "=Up")
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(unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w")
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(match_operand:<V_elem> 2 "s_register_operand" "r")]
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VCMPNEQ_N))
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]
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"TARGET_HAVE_MVE"
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"vcmp.i%#<V_sz_elem> ne, %q1, %2"
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[(set_attr "type" "mve_move")
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])
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;;
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;; [veorq_u, veorq_s])
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;;
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