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testsuite/s390: Fix risbg-ll-3.c f2_cconly test.

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Instead of selecting bits 62 to (wraparound) 59 from r2 and inserting them
into r3, we select bits 60 to 62 from r3 and insert them into r2
nowadays.  Adjust the test accordingly.

gcc/testsuite/ChangeLog:

	* gcc.target/s390/risbg-ll-3.c: Change match pattern.
This commit is contained in:
Robin Dapp 2021-05-11 09:50:44 +02:00
parent 15e6b45c9a
commit cf43636a74
1 changed files with 1 additions and 1 deletions
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2
gcc/testsuite/gcc.target/s390/risbg-ll-3.c
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@ -37,7 +37,7 @@ i64 f2 (i64 v_a, i64 v_b)
void f2_bar ();
void f2_cconly (i64 v_a, i64 v_b)
{
/* { dg-final { scan-assembler "f2_cconly:\n\trisbg\t%r3,%r2,63,59,0\n\tber\t%r14\n\tjg\tf2_bar\n" { target { lp64 } } } } */
/* { dg-final { scan-assembler "f2_cconly:\n\trisbg\t%r2,%r3,60,62,0\n\tber\t%r14\n\tjg\tf2_bar\n" { target { lp64 } } } } */
/* { dg-final { scan-assembler "f2_cconly:\n\trisbgn\t%r3,%r2,0,0\\\+32-1,64-0-32\n\trisbg\t%r3,%r5,60,62,0\n\tber\t%r14\n\tjg\tf2_bar\n" { target { ! lp64 } } } } */
if ((v_a & -15) | (v_b & 14))
f2_bar();