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[ARC] Add and refurbish the builtins related functions.

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gcc/
2015-12-21  Claudiu Zissulescu  <claziss@synopsys.com>

	* config/arc/builtins.def: New file.
	* config/arc/arc.c (arc_init_simd_builtins): Remove.
	(arc_builtins): Likewise.
	(TARGET_BUILTIN_DECL): Define.
	(arc_builtin_id): New enum.
	(arc_builtin_description): New structure.
	(arc_bdesc): New variable.
	(arc_tolower): New function.
	(def_mbuiltin): Remove.
	(arc_builtin_decl): New function.
	(arc_expand_builtin_aligned ): Likewise.
	(apply_GEN_FCN): Likewise.
	(arc_init_builtins): Refurbish.
	(arc_expand_builtin): Likewise.
	(simd_insn_args_type): Remove.
	(builtin_description): Likewise
	(arc_simd_builtin_desc_list): Likewise.
	(arc_expand_simd_builtin): Likewise.
	(arc_process_double_reg_moves): Use the new builtin name format.
	* config/arc/arc.md (unspec): New builtin function UNSPEC codes.
	(vunspec): New builtin function VUNSPEC codes.
	(UNSPEC_SWAP, UNSPEC_MUL64, UNSPEC_MULU64, UNSPEC_DIVAW)
	(UNSPEC_DIRECT, UNSPEC_LP, UNSPEC_CASESI, VUNSPEC_RTIE)
	(VUNSPEC_SYNC, VUNSPEC_BRK, VUNSPEC_FLAG, VUNSPEC_SLEEP)
	(VUNSPEC_SWI, VUNSPEC_CORE_READ, VUNSPEC_CORE_WRITE, VUNSPEC_LR)
	(VUNSPEC_SR, VUNSPEC_TRAP_S, VUNSPEC_UNIMP_S, VUNSPEC_NOP)
	(UNSPEC_ARC_MEMBAR,VUNSPEC_ARC_CAS, VUNSPEC_ARC_LL)
	(VUNSPEC_ARC_SC, VUNSPEC_ARC_EX, VUNSPEC_DEXCL)
	(VUNSPEC_DEXCL_NORES, VUNSPEC_LR_HIGH): Remove.
	(mul64, mulu64): Remove patterns.
	(store_direct, *movdf_insn_nolrsr, casesi, casesi_load)
	(casesi_compact_jump, nopv, swap, divaw, flag, brk, rtie, sync)
	(swi, sleep, core_read, core_write, lr, sr, trap_s, unimp_s)
	(doloop_begin_i): Use new builtin function code naming.
	(kflag, clri, ffs, ffs_f, ffssi2, fls, seti): New patterns.
	* config/arc/builtins.def: New file.
	* config/arc/fpx.md: Use new builtin function code naming.
	* config/arc/simdext.md: New SIMD builtin function UNSPEC
	codes. Use them in the SIMD patterns.

gcc/testsuite
2015-12-21  Claudiu Zissulescu  <claziss@synopsys.com>

	* gcc.target/arc/builtin_general.c: New test.
	* gcc.target/arc/builtin_simd.c: Likewise.
	* gcc.target/arc/builtin_special.c: Likewise.

From-SVN: r231874
This commit is contained in:
Claudiu Zissulescu 2015-12-21 10:53:01 +01:00 • committed by Claudiu Zissulescu
parent f8e663301f
commit c69899f097
10 changed files with 1357 additions and 1529 deletions
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42
gcc/ChangeLog
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@ -1,3 +1,45 @@
2015-12-21 Claudiu Zissulescu <claziss@synopsys.com>
* config/arc/builtins.def: New file.
* config/arc/arc.c (arc_init_simd_builtins): Remove.
(arc_builtins): Likewise.
(TARGET_BUILTIN_DECL): Define.
(arc_builtin_id): New enum.
(arc_builtin_description): New structure.
(arc_bdesc): New variable.
(arc_tolower): New function.
(def_mbuiltin): Remove.
(arc_builtin_decl): New function.
(arc_expand_builtin_aligned ): Likewise.
(apply_GEN_FCN): Likewise.
(arc_init_builtins): Refurbish.
(arc_expand_builtin): Likewise.
(simd_insn_args_type): Remove.
(builtin_description): Likewise
(arc_simd_builtin_desc_list): Likewise.
(arc_expand_simd_builtin): Likewise.
(arc_process_double_reg_moves): Use the new builtin name format.
* config/arc/arc.md (unspec): New builtin function UNSPEC codes.
(vunspec): New builtin function VUNSPEC codes.
(UNSPEC_SWAP, UNSPEC_MUL64, UNSPEC_MULU64, UNSPEC_DIVAW)
(UNSPEC_DIRECT, UNSPEC_LP, UNSPEC_CASESI, VUNSPEC_RTIE)
(VUNSPEC_SYNC, VUNSPEC_BRK, VUNSPEC_FLAG, VUNSPEC_SLEEP)
(VUNSPEC_SWI, VUNSPEC_CORE_READ, VUNSPEC_CORE_WRITE, VUNSPEC_LR)
(VUNSPEC_SR, VUNSPEC_TRAP_S, VUNSPEC_UNIMP_S, VUNSPEC_NOP)
(UNSPEC_ARC_MEMBAR,VUNSPEC_ARC_CAS, VUNSPEC_ARC_LL)
(VUNSPEC_ARC_SC, VUNSPEC_ARC_EX, VUNSPEC_DEXCL)
(VUNSPEC_DEXCL_NORES, VUNSPEC_LR_HIGH): Remove.
(mul64, mulu64): Remove patterns.
(store_direct, *movdf_insn_nolrsr, casesi, casesi_load)
(casesi_compact_jump, nopv, swap, divaw, flag, brk, rtie, sync)
(swi, sleep, core_read, core_write, lr, sr, trap_s, unimp_s)
(doloop_begin_i): Use new builtin function code naming.
(kflag, clri, ffs, ffs_f, ffssi2, fls, seti): New patterns.
* config/arc/builtins.def: New file.
* config/arc/fpx.md: Use new builtin function code naming.
* config/arc/simdext.md: New SIMD builtin function UNSPEC
codes. Use them in the SIMD patterns.
2015-12-21 Sujoy Saraswati <sujoy.saraswati@hpe.com>
PR tree-optimization/61441

1897
gcc/config/arc/arc.c
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File diff suppressed because it is too large Load diff

252
gcc/config/arc/arc.md
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@ -104,35 +104,66 @@
;; GOTBASE.(Referenced as @GOTOFF)
;; ----------------------------------------------------------------------------
(define_c_enum "unspec" [
DUMMY_0
DUMMY_1
DUMMY_2
ARC_UNSPEC_PLT
ARC_UNSPEC_GOT
ARC_UNSPEC_GOTOFF
UNSPEC_ARC_NORM
UNSPEC_ARC_NORMW
UNSPEC_ARC_SWAP
UNSPEC_ARC_DIVAW
UNSPEC_ARC_DIRECT
UNSPEC_ARC_LP
UNSPEC_ARC_CASESI
UNSPEC_ARC_FFS
UNSPEC_ARC_FLS
UNSPEC_ARC_MEMBAR
UNSPEC_ARC_DMACH
UNSPEC_ARC_DMACHU
UNSPEC_ARC_DMACWH
UNSPEC_ARC_DMACWHU
UNSPEC_ARC_QMACH
UNSPEC_ARC_QMACHU
UNSPEC_ARC_QMPYH
UNSPEC_ARC_QMPYHU
UNSPEC_ARC_VMAC2H
UNSPEC_ARC_VMAC2HU
UNSPEC_ARC_VMPY2H
UNSPEC_ARC_VMPY2HU
])
(define_c_enum "vunspec" [
VUNSPEC_ARC_RTIE
VUNSPEC_ARC_SYNC
VUNSPEC_ARC_BRK
VUNSPEC_ARC_FLAG
VUNSPEC_ARC_SLEEP
VUNSPEC_ARC_SWI
VUNSPEC_ARC_CORE_READ
VUNSPEC_ARC_CORE_WRITE
VUNSPEC_ARC_LR
VUNSPEC_ARC_SR
VUNSPEC_ARC_TRAP_S
VUNSPEC_ARC_UNIMP_S
VUNSPEC_ARC_KFLAG
VUNSPEC_ARC_CLRI
VUNSPEC_ARC_SETI
VUNSPEC_ARC_NOP
VUNSPEC_ARC_STACK_IRQ
VUNSPEC_ARC_DEXCL
VUNSPEC_ARC_DEXCL_NORES
VUNSPEC_ARC_LR_HIGH
VUNSPEC_ARC_EX
VUNSPEC_ARC_CAS
VUNSPEC_ARC_SC
VUNSPEC_ARC_LL
])
(define_constants
[(UNSPEC_SWAP 13) ; swap generation through builtins. candidate for scheduling
(UNSPEC_MUL64 14) ; mul64 generation through builtins. candidate for scheduling
(UNSPEC_MULU64 15) ; mulu64 generation through builtins. candidate for scheduling
(UNSPEC_DIVAW 16) ; divaw generation through builtins. candidate for scheduling
(UNSPEC_DIRECT 17)
(UNSPEC_PROF 18) ; profile callgraph counter
(UNSPEC_LP 19) ; to set LP_END
(UNSPEC_CASESI 20)
(VUNSPEC_RTIE 17) ; blockage insn for rtie generation
(VUNSPEC_SYNC 18) ; blockage insn for sync generation
(VUNSPEC_BRK 19) ; blockage insn for brk generation
(VUNSPEC_FLAG 20) ; blockage insn for flag generation
(VUNSPEC_SLEEP 21) ; blockage insn for sleep generation
(VUNSPEC_SWI 22) ; blockage insn for swi generation
(VUNSPEC_CORE_READ 23) ; blockage insn for reading a core register
(VUNSPEC_CORE_WRITE 24) ; blockage insn for writing to a core register
(VUNSPEC_LR 25) ; blockage insn for reading an auxiliary register
(VUNSPEC_SR 26) ; blockage insn for writing to an auxiliary register
(VUNSPEC_TRAP_S 27) ; blockage insn for trap_s generation
(VUNSPEC_UNIMP_S 28) ; blockage insn for unimp_s generation
(VUNSPEC_NOP 29) ; volatile NOP
(UNSPEC_ARC_MEMBAR 30)
(VUNSPEC_ARC_CAS 31)
(VUNSPEC_ARC_LL 32)
(VUNSPEC_ARC_SC 33)
(VUNSPEC_ARC_EX 34)
[(UNSPEC_PROF 18) ; profile callgraph counter
(R0_REG 0)
(R1_REG 1)
@ -145,10 +176,6 @@
(RETURN_ADDR_REGNUM 31)
(MUL64_OUT_REG 58)
(VUNSPEC_DEXCL 32) ; blockage insn for reading an auxiliary register without LR support
(VUNSPEC_DEXCL_NORES 33) ; blockage insn for reading an auxiliary register without LR support
(VUNSPEC_LR_HIGH 34) ; blockage insn for reading an auxiliary register
(LP_COUNT 60)
(CC_REG 61)
(LP_START 144)
@ -716,7 +743,7 @@
(define_insn "store_direct"
[(set (match_operand:SI 0 "move_dest_operand" "=m")
(unspec:SI [(match_operand:SI 1 "register_operand" "c")]
UNSPEC_DIRECT))]
UNSPEC_ARC_DIRECT))]
""
"st%U0 %1,%0\;st%U0.di %1,%0"
[(set_attr "type" "store")])
@ -1083,10 +1110,10 @@
; dexcl2 r0, r1, r0
(set (match_dup 4) ; aka r0result
; aka DF, r1, r0
(unspec_volatile:SI [(match_dup 1) (match_dup 5) (match_dup 4)] VUNSPEC_DEXCL ))
(unspec_volatile:SI [(match_dup 1) (match_dup 5) (match_dup 4)] VUNSPEC_ARC_DEXCL ))
; Generate the second, which makes sure operand5 and operand4 values
; are put back in the Dx register properly.
(unspec_volatile:SI [(match_dup 1) (match_dup 5) (match_dup 4)] VUNSPEC_DEXCL_NORES )
(unspec_volatile:SI [(match_dup 1) (match_dup 5) (match_dup 4)] VUNSPEC_ARC_DEXCL_NORES )
; Note: we cannot use a (clobber (match_scratch)) here because
; the combine pass will end up replacing uses of it with 0
@ -3646,7 +3673,7 @@
(pc)))
(set (match_dup 6)
(unspec:SI [(match_operand 3 "" "")
(match_dup 5) (match_dup 7)] UNSPEC_CASESI))
(match_dup 5) (match_dup 7)] UNSPEC_ARC_CASESI))
(parallel [(set (pc) (match_dup 6)) (use (match_dup 7))])]
""
"
@ -3684,7 +3711,7 @@
[(set (match_operand:SI 0 "register_operand" "=Rcq,r,r")
(unspec:SI [(match_operand:SI 1 "nonmemory_operand" "Rcq,c,Cal")
(match_operand:SI 2 "register_operand" "Rcq,c,c")
(label_ref (match_operand 3 "" ""))] UNSPEC_CASESI))]
(label_ref (match_operand 3 "" ""))] UNSPEC_ARC_CASESI))]
""
"*
{
@ -3749,7 +3776,7 @@
(define_insn "casesi_compact_jump"
[(set (pc)
(unspec:SI [(match_operand:SI 0 "register_operand" "c,q")]
UNSPEC_CASESI))
UNSPEC_ARC_CASESI))
(use (label_ref (match_operand 1 "" "")))
(clobber (match_scratch:SI 2 "=q,0"))]
"TARGET_COMPACT_CASESI"
@ -4000,7 +4027,7 @@
(set_attr "length" "2")])
(define_insn "nopv"
[(unspec_volatile [(const_int 0)] VUNSPEC_NOP)]
[(unspec_volatile [(const_int 0)] VUNSPEC_ARC_NOP)]
""
"nop%?"
[(set_attr "type" "misc")
@ -4245,7 +4272,7 @@
(define_insn "swap"
[(set (match_operand:SI 0 "dest_reg_operand" "=w,w,w")
(unspec:SI [(match_operand:SI 1 "general_operand" "L,Cal,c")]
UNSPEC_SWAP))]
UNSPEC_ARC_SWAP))]
"TARGET_SWAP"
"@
swap \t%0, %1
@ -4254,41 +4281,11 @@
[(set_attr "length" "4,8,4")
(set_attr "type" "two_cycle_core,two_cycle_core,two_cycle_core")])
;; FIXME: an intrinsic for multiply is daft. Can we remove this?
(define_insn "mul64"
[(unspec [(match_operand:SI 0 "general_operand" "%q,r,r,r")
(match_operand:SI 1 "general_operand" "q,rL,I,Cal")]
UNSPEC_MUL64)]
"TARGET_MUL64_SET"
"@
mul64%? \t0, %0, %1%&
mul64%? \t0, %0, %1
mul64 \t0, %0, %1
mul64%? \t0, %0, %S1"
[(set_attr "length" "2,4,4,8")
(set_attr "iscompact" "true,false,false,false")
(set_attr "type" "binary,binary,binary,binary")
(set_attr "cond" "canuse,canuse, nocond, canuse")])
(define_insn "mulu64"
[(unspec [(match_operand:SI 0 "general_operand" "%r,r,r,r")
(match_operand:SI 1 "general_operand" "rL,I,r,Cal")]
UNSPEC_MULU64)]
"TARGET_MUL64_SET"
"@
mulu64%? \t0, %0, %1
mulu64 \t0, %0, %1
mulu64 \t0, %0, %1
mulu64%? \t0, %0, %S1"
[(set_attr "length" "4,4,4,8")
(set_attr "type" "binary,binary,binary,binary")
(set_attr "cond" "canuse,nocond,nocond,canuse")])
(define_insn "divaw"
[(set (match_operand:SI 0 "dest_reg_operand" "=&w,&w,&w")
(unspec:SI [(div:SI (match_operand:SI 1 "general_operand" "r,Cal,r")
(match_operand:SI 2 "general_operand" "r,r,Cal"))]
UNSPEC_DIVAW))]
UNSPEC_ARC_DIVAW))]
"TARGET_ARC700 || TARGET_EA_SET"
"@
divaw \t%0, %1, %2
@ -4299,7 +4296,7 @@
(define_insn "flag"
[(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "rL,I,Cal")]
VUNSPEC_FLAG)]
VUNSPEC_ARC_FLAG)]
""
"@
flag%? %0
@ -4312,7 +4309,7 @@
(define_insn "brk"
[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "N")]
VUNSPEC_BRK)]
VUNSPEC_ARC_BRK)]
""
"brk"
[(set_attr "length" "4")
@ -4320,7 +4317,7 @@
(define_insn "rtie"
[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "N")]
VUNSPEC_RTIE)]
VUNSPEC_ARC_RTIE)]
""
"rtie"
[(set_attr "length" "4")
@ -4329,7 +4326,7 @@
(define_insn "sync"
[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "N")]
VUNSPEC_SYNC)]
VUNSPEC_ARC_SYNC)]
""
"sync"
[(set_attr "length" "4")
@ -4337,7 +4334,7 @@
(define_insn "swi"
[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "N")]
VUNSPEC_SWI)]
VUNSPEC_ARC_SWI)]
""
"*
{
@ -4352,7 +4349,7 @@
(define_insn "sleep"
[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "L")]
VUNSPEC_SLEEP)]
VUNSPEC_ARC_SLEEP)]
"check_if_valid_sleep_operand(operands,0)"
"sleep %0"
[(set_attr "length" "4")
@ -4361,7 +4358,7 @@
(define_insn "core_read"
[(set (match_operand:SI 0 "dest_reg_operand" "=r,r")
(unspec_volatile:SI [(match_operand:SI 1 "general_operand" "Hn,!r")]
VUNSPEC_CORE_READ))]
VUNSPEC_ARC_CORE_READ))]
""
"*
if (check_if_valid_regno_const (operands, 1))
@ -4374,7 +4371,7 @@
(define_insn "core_write"
[(unspec_volatile [(match_operand:SI 0 "general_operand" "r,r")
(match_operand:SI 1 "general_operand" "Hn,!r")]
VUNSPEC_CORE_WRITE)]
VUNSPEC_ARC_CORE_WRITE)]
""
"*
if (check_if_valid_regno_const (operands, 1))
@ -4387,7 +4384,7 @@
(define_insn "lr"
[(set (match_operand:SI 0 "dest_reg_operand" "=r,r,r,r")
(unspec_volatile:SI [(match_operand:SI 1 "general_operand" "I,HCal,r,D")]
VUNSPEC_LR))]
VUNSPEC_ARC_LR))]
""
"lr\t%0, [%1]"
[(set_attr "length" "4,8,4,8")
@ -4396,7 +4393,7 @@
(define_insn "sr"
[(unspec_volatile [(match_operand:SI 0 "general_operand" "Cal,r,r,r")
(match_operand:SI 1 "general_operand" "Ir,I,HCal,r")]
VUNSPEC_SR)]
VUNSPEC_ARC_SR)]
""
"sr\t%S0, [%1]"
[(set_attr "length" "8,4,8,4")
@ -4404,8 +4401,8 @@
(define_insn "trap_s"
[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "L,Cal")]
VUNSPEC_TRAP_S)]
"TARGET_ARC700"
VUNSPEC_ARC_TRAP_S)]
"!TARGET_ARC600_FAMILY"
{
if (which_alternative == 0)
{
@ -4423,8 +4420,8 @@
(define_insn "unimp_s"
[(unspec_volatile [(match_operand:SI 0 "immediate_operand" "N")]
VUNSPEC_UNIMP_S)]
"TARGET_ARC700"
VUNSPEC_ARC_UNIMP_S)]
"!TARGET_ARC600_FAMILY"
"unimp_s"
[(set_attr "length" "4")
(set_attr "type" "misc")])
@ -4867,7 +4864,7 @@
; hoist the SETs.
;(define_insn "doloop_begin_i"
; [(set (reg:SI LP_START) (pc))
; (set (reg:SI LP_END) (unspec:SI [(pc)] UNSPEC_LP))
; (set (reg:SI LP_END) (unspec:SI [(pc)] UNSPEC_ARC_LP))
; (use (match_operand 0 "const_int_operand" "n"))]
; ""
; "lp .L__GCC__LP%0"
@ -4881,7 +4878,7 @@
;
; N in XVECEXP PATTERN (lp, 0 N)
; V rtl purpose
; 0 unspec UNSPEC_LP identify pattern
; 0 unspec UNSPEC_ARC_LP identify pattern
; 1 clobber LP_START show LP_START is set
; 2 clobber LP_END show LP_END is set
; 3 use operand0 loop count pseudo register
@ -4896,7 +4893,7 @@
; There is no point is reloading this insn - then lp_count would still not
; be available for the loop end.
(define_insn "doloop_begin_i"
[(unspec:SI [(pc)] UNSPEC_LP)
[(unspec:SI [(pc)] UNSPEC_ARC_LP)
(clobber (reg:SI LP_START))
(clobber (reg:SI LP_END))
(use (match_operand:SI 0 "register_operand" "l,l,????*X"))
@ -5533,6 +5530,87 @@
(set_attr "predicable" "yes,no,no,yes,no")
(set_attr "cond" "canuse,nocond,nocond,canuse,nocond")])
(define_insn "kflag"
[(unspec_volatile [(match_operand:SI 0 "nonmemory_operand" "rL,I,Cal")]
VUNSPEC_ARC_KFLAG)]
"TARGET_V2"
"@
kflag%? %0
kflag %0
kflag%? %S0"
[(set_attr "length" "4,4,8")
(set_attr "type" "misc,misc,misc")
(set_attr "predicable" "yes,no,yes")
(set_attr "cond" "clob,clob,clob")])
(define_insn "clri"
[(set (match_operand:SI 0 "dest_reg_operand" "=r")
(unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "N")]
VUNSPEC_ARC_CLRI))]
"TARGET_V2"
"clri %0"
[(set_attr "length" "4")
(set_attr "type" "misc")])
(define_insn "ffs"
[(set (match_operand:SI 0 "dest_reg_operand" "=w,w")
(unspec:SI [(match_operand:SI 1 "general_operand" "cL,Cal")]
UNSPEC_ARC_FFS))]
"TARGET_NORM && TARGET_V2"
"@
ffs \t%0, %1
ffs \t%0, %S1"
[(set_attr "length" "4,8")
(set_attr "type" "two_cycle_core,two_cycle_core")])
(define_insn "ffs_f"
[(set (match_operand:SI 0 "dest_reg_operand" "=w,w")
(unspec:SI [(match_operand:SI 1 "general_operand" "cL,Cal")]
UNSPEC_ARC_FFS))
(set (reg:CC_ZN CC_REG)
(compare:CC_ZN (match_dup 1) (const_int 0)))]
"TARGET_NORM && TARGET_V2"
"@
ffs.f\t%0, %1
ffs.f\t%0, %S1"
[(set_attr "length" "4,8")
(set_attr "type" "two_cycle_core,two_cycle_core")])
(define_expand "ffssi2"
[(parallel [(set (match_dup 2)
(unspec:SI [(match_operand:SI 1 "register_operand" "")]
UNSPEC_ARC_FFS))
(set (reg:CC_ZN CC_REG)
(compare:CC_ZN (match_dup 1) (const_int 0)))])
(set (match_dup 2) (plus:SI (match_dup 2) (const_int 1)))
(set (match_operand:SI 0 "dest_reg_operand" "")
(if_then_else:SI (eq:SI (reg:CC_ZN CC_REG) (const_int 0))
(const_int 0)
(match_dup 2)))]
"TARGET_NORM && TARGET_V2"
{
operands[2] = gen_reg_rtx (SImode);
})
(define_insn "fls"
[(set (match_operand:SI 0 "dest_reg_operand" "=w,w")
(unspec:SI [(match_operand:SI 1 "general_operand" "cL,Cal")]
UNSPEC_ARC_FLS))]
"TARGET_NORM && TARGET_V2"
"@
fls \t%0, %1
fls \t%0, %S1"
[(set_attr "length" "4,8")
(set_attr "type" "two_cycle_core,two_cycle_core")])
(define_insn "seti"
[(unspec_volatile:SI [(match_operand:SI 0 "general_operand" "rL")]
VUNSPEC_ARC_SETI)]
"TARGET_V2"
"seti %0"
[(set_attr "length" "4")
(set_attr "type" "misc")])
;; include the arc-FPX instructions
(include "fpx.md")

195
gcc/config/arc/builtins.def Normal file
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@ -0,0 +1,195 @@
/* Copyright (C) 2015 Free Software Foundation, Inc.
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License as published by the Free
Software Foundation; either version 3, or (at your option) any later
version.
GCC is distributed in the hope that it will be useful, but WITHOUT ANY
WARRANTY; without even the implied warranty of MERCHANTABILITY or
FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
/* This file contains the definitions and documentation for the
builtins defined in the ARC part of the GNU compiler. Before
including this file, define a macro
DEF_BUILTIN(NAME, N_ARGS, TYPE, ICODE, MASK)
NAME: `__builtin_arc_name' will be the user-level name of the builtin.
`ARC_BUILTIN_NAME' will be the internal builtin's id.
N_ARGS: Number of input arguments. If special treatment is needed,
set to -1 and handle it by hand, see arc.c:arc_expand_builtin().
TYPE: A tree node describing the prototype of the built-in.
ICODE: Name of attached insn or expander. If special treatment in arc.c
is needed to expand the built-in, use `nothing'.
MASK: CPU selector mask. */
/* Special builtins. */
DEF_BUILTIN (NOP, 0, void_ftype_void, nothing, 1)
DEF_BUILTIN (RTIE, 0, void_ftype_void, rtie, 1)
DEF_BUILTIN (SYNC, 0, void_ftype_void, sync, TARGET_ARC700)
DEF_BUILTIN (BRK, 0, void_ftype_void, brk, 1)
DEF_BUILTIN (SWI, 0, void_ftype_void, swi, 1)
DEF_BUILTIN (UNIMP_S, 0, void_ftype_void, unimp_s, !TARGET_ARC600_FAMILY)
DEF_BUILTIN (TRAP_S, 1, void_ftype_usint, trap_s, !TARGET_ARC600_FAMILY)
DEF_BUILTIN (ALIGNED, 2, int_ftype_pcvoid_int, nothing, 1)
DEF_BUILTIN (CLRI, 0, int_ftype_void, clri, TARGET_V2)
DEF_BUILTIN (SLEEP, 1, void_ftype_usint, sleep, 1)
DEF_BUILTIN (FLAG, 1, void_ftype_usint, flag, 1)
DEF_BUILTIN (SR, 2, void_ftype_usint_usint, sr, 1)
DEF_BUILTIN (KFLAG, 1, void_ftype_usint, kflag, TARGET_V2)
DEF_BUILTIN (CORE_WRITE, 2, void_ftype_usint_usint, core_write, 1)
DEF_BUILTIN (SETI, 1, void_ftype_int, seti, TARGET_V2)
/* Regular builtins. */
DEF_BUILTIN (NORM, 1, int_ftype_int, clrsbsi2, TARGET_NORM)
DEF_BUILTIN (NORMW, 1, int_ftype_short, normw, TARGET_NORM)
DEF_BUILTIN (SWAP, 1, int_ftype_int, swap, TARGET_SWAP)
DEF_BUILTIN (DIVAW, 2, int_ftype_int_int, divaw, TARGET_EA_SET)
DEF_BUILTIN (CORE_READ, 1, usint_ftype_usint, core_read, 1)
DEF_BUILTIN (LR, 1, usint_ftype_usint, lr, 1)
DEF_BUILTIN (FFS, 1, int_ftype_int, ffs, (TARGET_EM && TARGET_NORM) || TARGET_HS)
DEF_BUILTIN (FLS, 1, int_ftype_int, fls, (TARGET_EM && TARGET_NORM) || TARGET_HS)
/* ARC SIMD extenssion. */
/* BEGIN SIMD marker. */
DEF_BUILTIN (SIMD_BEGIN, 0, void_ftype_void, nothing, 0)
DEF_BUILTIN ( VADDAW, 2, v8hi_ftype_v8hi_v8hi, vaddaw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VADDW, 2, v8hi_ftype_v8hi_v8hi, vaddw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VAVB, 2, v8hi_ftype_v8hi_v8hi, vavb_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VAVRB, 2, v8hi_ftype_v8hi_v8hi, vavrb_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VDIFAW, 2, v8hi_ftype_v8hi_v8hi, vdifaw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VDIFW, 2, v8hi_ftype_v8hi_v8hi, vdifw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMAXAW, 2, v8hi_ftype_v8hi_v8hi, vmaxaw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMAXW, 2, v8hi_ftype_v8hi_v8hi, vmaxw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMINAW, 2, v8hi_ftype_v8hi_v8hi, vminaw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMINW, 2, v8hi_ftype_v8hi_v8hi, vminw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMULAW, 2, v8hi_ftype_v8hi_v8hi, vmulaw_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VMULFAW, 2, v8hi_ftype_v8hi_v8hi, vmulfaw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMULFW, 2, v8hi_ftype_v8hi_v8hi, vmulfw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMULW, 2, v8hi_ftype_v8hi_v8hi, vmulw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VSUBAW, 2, v8hi_ftype_v8hi_v8hi, vsubaw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VSUBW, 2, v8hi_ftype_v8hi_v8hi, vsubw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VSUMMW, 2, v8hi_ftype_v8hi_v8hi, vsummw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VAND, 2, v8hi_ftype_v8hi_v8hi, vand_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VANDAW, 2, v8hi_ftype_v8hi_v8hi, vandaw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VBIC, 2, v8hi_ftype_v8hi_v8hi, vbic_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VBICAW, 2, v8hi_ftype_v8hi_v8hi, vbicaw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VOR, 2, v8hi_ftype_v8hi_v8hi, vor_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VXOR, 2, v8hi_ftype_v8hi_v8hi, vxor_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VXORAW, 2, v8hi_ftype_v8hi_v8hi, vxoraw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VEQW, 2, v8hi_ftype_v8hi_v8hi, veqw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VLEW, 2, v8hi_ftype_v8hi_v8hi, vlew_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VLTW, 2, v8hi_ftype_v8hi_v8hi, vltw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VNEW, 2, v8hi_ftype_v8hi_v8hi, vnew_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMR1AW, 2, v8hi_ftype_v8hi_v8hi, vmr1aw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMR1W, 2, v8hi_ftype_v8hi_v8hi, vmr1w_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMR2AW, 2, v8hi_ftype_v8hi_v8hi, vmr2aw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMR2W, 2, v8hi_ftype_v8hi_v8hi, vmr2w_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMR3AW, 2, v8hi_ftype_v8hi_v8hi, vmr3aw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMR3W, 2, v8hi_ftype_v8hi_v8hi, vmr3w_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMR4AW, 2, v8hi_ftype_v8hi_v8hi, vmr4aw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMR4W, 2, v8hi_ftype_v8hi_v8hi, vmr4w_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMR5AW, 2, v8hi_ftype_v8hi_v8hi, vmr5aw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMR5W, 2, v8hi_ftype_v8hi_v8hi, vmr5w_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMR6AW, 2, v8hi_ftype_v8hi_v8hi, vmr6aw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMR6W, 2, v8hi_ftype_v8hi_v8hi, vmr6w_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMR7AW, 2, v8hi_ftype_v8hi_v8hi, vmr7aw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMR7W, 2, v8hi_ftype_v8hi_v8hi, vmr7w_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMRB, 2, v8hi_ftype_v8hi_v8hi, vmrb_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VH264F, 2, v8hi_ftype_v8hi_v8hi, vh264f_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VH264FT, 2, v8hi_ftype_v8hi_v8hi, vh264ft_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VH264FW, 2, v8hi_ftype_v8hi_v8hi, vh264fw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VVC1F, 2, v8hi_ftype_v8hi_v8hi, vvc1f_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VVC1FT, 2, v8hi_ftype_v8hi_v8hi, vvc1ft_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VBADDW, 2, v8hi_ftype_v8hi_int, vbaddw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VBMAXW, 2, v8hi_ftype_v8hi_int, vbmaxw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VBMINW, 2, v8hi_ftype_v8hi_int, vbminw_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VBMULAW, 2, v8hi_ftype_v8hi_int, vbmulaw_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VBMULFW, 2, v8hi_ftype_v8hi_int, vbmulfw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VBMULW, 2, v8hi_ftype_v8hi_int, vbmulw_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VBRSUBW, 2, v8hi_ftype_v8hi_int, vbrsubw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VBSUBW, 2, v8hi_ftype_v8hi_int, vbsubw_insn, TARGET_SIMD_SET)
/* Va, Vb, Ic instructions. */
DEF_BUILTIN ( VASRW, 2, v8hi_ftype_v8hi_int, vasrw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VSR8, 2, v8hi_ftype_v8hi_int, vsr8_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VSR8AW, 2, v8hi_ftype_v8hi_int, vsr8aw_insn, TARGET_SIMD_SET)
/* Va, Vb, u6 instructions. */
DEF_BUILTIN ( VASRRWi, 2, v8hi_ftype_v8hi_int, vasrrwi_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VASRSRWi, 2, v8hi_ftype_v8hi_int, vasrsrwi_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VASRWi, 2, v8hi_ftype_v8hi_int, vasrwi_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VASRPWBi, 2, v8hi_ftype_v8hi_int, vasrpwbi_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VASRRPWBi, 2, v8hi_ftype_v8hi_int, vasrrpwbi_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VSR8AWi, 2, v8hi_ftype_v8hi_int, vsr8awi_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VSR8i, 2, v8hi_ftype_v8hi_int, vsr8i_insn, TARGET_SIMD_SET)
/* Va, Vb, u8 (simm) instructions. */
DEF_BUILTIN ( VMVAW, 2, v8hi_ftype_v8hi_int, vmvaw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMVW, 2, v8hi_ftype_v8hi_int, vmvw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMVZW, 2, v8hi_ftype_v8hi_int, vmvzw_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VD6TAPF, 2, v8hi_ftype_v8hi_int, vd6tapf_insn, TARGET_SIMD_SET)
/* Va, rlimm, u8 (simm) instructions. */
DEF_BUILTIN (VMOVAW, 2, v8hi_ftype_int_int, vmovaw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VMOVW, 2, v8hi_ftype_int_int, vmovw_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VMOVZW, 2, v8hi_ftype_int_int, vmovzw_insn, TARGET_SIMD_SET)
/* Va, Vb instructions. */
DEF_BUILTIN ( VABSAW, 1, v8hi_ftype_v8hi, vabsaw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VABSW, 1, v8hi_ftype_v8hi, vabsw_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VADDSUW, 1, v8hi_ftype_v8hi, vaddsuw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VSIGNW, 1, v8hi_ftype_v8hi, vsignw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VEXCH1, 1, v8hi_ftype_v8hi, vexch1_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VEXCH2, 1, v8hi_ftype_v8hi, vexch2_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VEXCH4, 1, v8hi_ftype_v8hi, vexch4_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VUPBAW, 1, v8hi_ftype_v8hi, vupbaw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VUPBW, 1, v8hi_ftype_v8hi, vupbw_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VUPSBAW, 1, v8hi_ftype_v8hi, vupsbaw_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VUPSBW, 1, v8hi_ftype_v8hi, vupsbw_insn, TARGET_SIMD_SET)
/* SIMD special DIb, rlimm, rlimm instructions. */
DEF_BUILTIN (VDIRUN, 2, void_ftype_int_int, vdirun_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VDORUN, 2, void_ftype_int_int, vdorun_insn, TARGET_SIMD_SET)
/* SIMD special DIb, limm, rlimm instructions. */
DEF_BUILTIN (VDIWR, 2, void_ftype_int_int, vdiwr_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VDOWR, 2, void_ftype_int_int, vdowr_insn, TARGET_SIMD_SET)
/* rlimm instructions. */
DEF_BUILTIN ( VREC, 1, void_ftype_int, vrec_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VRUN, 1, void_ftype_int, vrun_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VRECRUN, 1, void_ftype_int, vrecrun_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VENDREC, 1, void_ftype_int, vendrec_insn, TARGET_SIMD_SET)
/* Va, [Ib,u8] instructions. */
DEF_BUILTIN (VLD32WH, 3, v8hi_ftype_v8hi_int_int, vld32wh_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VLD32WL, 3, v8hi_ftype_v8hi_int_int, vld32wl_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VLD64, 3, v8hi_ftype_v8hi_int_int, vld64_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VLD32, 3, v8hi_ftype_v8hi_int_int, vld32_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VLD64W, 2, v8hi_ftype_int_int, vld64w_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VLD128, 2, v8hi_ftype_int_int, vld128_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VST128, 3, void_ftype_v8hi_int_int, vst128_insn, TARGET_SIMD_SET)
DEF_BUILTIN ( VST64, 3, void_ftype_v8hi_int_int, vst64_insn, TARGET_SIMD_SET)
/* Va, [Ib, u8] instructions. */
DEF_BUILTIN (VST16_N, 4, void_ftype_v8hi_int_int_int, vst16_n_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VST32_N, 4, void_ftype_v8hi_int_int_int, vst32_n_insn, TARGET_SIMD_SET)
DEF_BUILTIN (VINTI, 1, void_ftype_int, vinti_insn, TARGET_SIMD_SET)
/* END SIMD marker. */
DEF_BUILTIN (SIMD_END, 0, void_ftype_void, nothing, 0)

19
gcc/config/arc/fpx.md
View file

@ -151,7 +151,7 @@
;; op0_reg = D1_reg.low
(define_insn "*lr_double_lower"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "D")] VUNSPEC_LR ))]
(unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "D")] VUNSPEC_ARC_LR ))]
"TARGET_DPFP && !TARGET_DPFP_DISABLE_LRSR"
"lr %0, [%1l] ; *lr_double_lower"
[(set_attr "length" "8")
@ -160,7 +160,8 @@
(define_insn "*lr_double_higher"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "D")] VUNSPEC_LR_HIGH ))]
(unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "D")]
VUNSPEC_ARC_LR_HIGH ))]
"TARGET_DPFP && !TARGET_DPFP_DISABLE_LRSR"
"lr %0, [%1h] ; *lr_double_higher"
[(set_attr "length" "8")
@ -174,7 +175,7 @@
(match_operand:DF 1 "arc_double_register_operand" "D")
(match_operand:SI 2 "shouldbe_register_operand" "r") ; r1
(match_operand:SI 3 "shouldbe_register_operand" "r") ; r0
] VUNSPEC_DEXCL ))
] VUNSPEC_ARC_DEXCL ))
]
"TARGET_DPFP"
"dexcl%F1 %0, %2, %3"
@ -188,7 +189,7 @@
(match_operand:DF 0 "arc_double_register_operand" "D")
(match_operand:SI 1 "shouldbe_register_operand" "r") ; r1
(match_operand:SI 2 "shouldbe_register_operand" "r") ; r0
] VUNSPEC_DEXCL_NORES )
] VUNSPEC_ARC_DEXCL_NORES )
]
"TARGET_DPFP"
"dexcl%F0 0, %1, %2"
@ -199,7 +200,7 @@
;; dexcl a,b,c pattern generated by the peephole2 above
(define_insn "*dexcl_3op_peep2_insn_lr"
[(parallel [(set (match_operand:SI 0 "register_operand" "=r")
(unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "=D")] VUNSPEC_LR ))
(unspec_volatile:SI [(match_operand:DF 1 "arc_double_register_operand" "=D")] VUNSPEC_ARC_LR ))
(set (match_dup 1) (match_operand:DF 2 "register_operand" "r"))]
)
]
@ -413,7 +414,7 @@
;; (parallel [
;; ;; (set (subreg:SI (match_dup 5) 0)
;; (set (match_dup 7)
;; (unspec_volatile [(match_dup 0)] VUNSPEC_LR ))
;; (unspec_volatile [(match_dup 0)] VUNSPEC_ARC_LR ))
;; (set (match_dup 0) (match_dup 6))]
;; )
;; ]
@ -472,7 +473,7 @@
(parallel [
;; (set (subreg:SI (match_dup 7) 0)
(set (match_dup 9)
(unspec_volatile:SI [(match_dup 0)] VUNSPEC_LR ))
(unspec_volatile:SI [(match_dup 0)] VUNSPEC_ARC_LR ))
(set (match_dup 0) (match_dup 8))]
)
]
@ -522,7 +523,7 @@
;; (match_dup 3)]))])
;; ; (set (subreg:SI (match_dup 5) 0)
;; (set (match_dup 6)
;; (unspec_volatile [(match_dup 0)] VUNSPEC_LR ))
;; (unspec_volatile [(match_dup 0)] VUNSPEC_ARC_LR ))
;; ]
;; "operands[6] = simplify_gen_subreg(SImode,operands[5],DFmode,0);"
;; )
@ -572,7 +573,7 @@
(match_dup 3)]))])
; (set (subreg:SI (match_dup 7) 0)
(set (match_dup 8)
(unspec_volatile:SI [(match_dup 0)] VUNSPEC_LR ))
(unspec_volatile:SI [(match_dup 0)] VUNSPEC_ARC_LR ))
]
"operands[8] = simplify_gen_subreg(SImode,operands[7],DFmode,0);"
)

226
gcc/config/arc/simdext.md
View file

@ -17,119 +17,117 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
(define_constants
[
(define_c_enum "unspec" [
;; Va, Vb, Vc builtins
(UNSPEC_ARC_SIMD_VADDAW 1000)
(UNSPEC_ARC_SIMD_VADDW 1001)
(UNSPEC_ARC_SIMD_VAVB 1002)
(UNSPEC_ARC_SIMD_VAVRB 1003)
(UNSPEC_ARC_SIMD_VDIFAW 1004)
(UNSPEC_ARC_SIMD_VDIFW 1005)
(UNSPEC_ARC_SIMD_VMAXAW 1006)
(UNSPEC_ARC_SIMD_VMAXW 1007)
(UNSPEC_ARC_SIMD_VMINAW 1008)
(UNSPEC_ARC_SIMD_VMINW 1009)
(UNSPEC_ARC_SIMD_VMULAW 1010)
(UNSPEC_ARC_SIMD_VMULFAW 1011)
(UNSPEC_ARC_SIMD_VMULFW 1012)
(UNSPEC_ARC_SIMD_VMULW 1013)
(UNSPEC_ARC_SIMD_VSUBAW 1014)
(UNSPEC_ARC_SIMD_VSUBW 1015)
(UNSPEC_ARC_SIMD_VSUMMW 1016)
(UNSPEC_ARC_SIMD_VAND 1017)
(UNSPEC_ARC_SIMD_VANDAW 1018)
(UNSPEC_ARC_SIMD_VBIC 1019)
(UNSPEC_ARC_SIMD_VBICAW 1020)
(UNSPEC_ARC_SIMD_VOR 1021)
(UNSPEC_ARC_SIMD_VXOR 1022)
(UNSPEC_ARC_SIMD_VXORAW 1023)
(UNSPEC_ARC_SIMD_VEQW 1024)
(UNSPEC_ARC_SIMD_VLEW 1025)
(UNSPEC_ARC_SIMD_VLTW 1026)
(UNSPEC_ARC_SIMD_VNEW 1027)
(UNSPEC_ARC_SIMD_VMR1AW 1028)
(UNSPEC_ARC_SIMD_VMR1W 1029)
(UNSPEC_ARC_SIMD_VMR2AW 1030)
(UNSPEC_ARC_SIMD_VMR2W 1031)
(UNSPEC_ARC_SIMD_VMR3AW 1032)
(UNSPEC_ARC_SIMD_VMR3W 1033)
(UNSPEC_ARC_SIMD_VMR4AW 1034)
(UNSPEC_ARC_SIMD_VMR4W 1035)
(UNSPEC_ARC_SIMD_VMR5AW 1036)
(UNSPEC_ARC_SIMD_VMR5W 1037)
(UNSPEC_ARC_SIMD_VMR6AW 1038)
(UNSPEC_ARC_SIMD_VMR6W 1039)
(UNSPEC_ARC_SIMD_VMR7AW 1040)
(UNSPEC_ARC_SIMD_VMR7W 1041)
(UNSPEC_ARC_SIMD_VMRB 1042)
(UNSPEC_ARC_SIMD_VH264F 1043)
(UNSPEC_ARC_SIMD_VH264FT 1044)
(UNSPEC_ARC_SIMD_VH264FW 1045)
(UNSPEC_ARC_SIMD_VVC1F 1046)
(UNSPEC_ARC_SIMD_VVC1FT 1047)
UNSPEC_ARC_SIMD_VADDAW
UNSPEC_ARC_SIMD_VADDW
UNSPEC_ARC_SIMD_VAVB
UNSPEC_ARC_SIMD_VAVRB
UNSPEC_ARC_SIMD_VDIFAW
UNSPEC_ARC_SIMD_VDIFW
UNSPEC_ARC_SIMD_VMAXAW
UNSPEC_ARC_SIMD_VMAXW
UNSPEC_ARC_SIMD_VMINAW
UNSPEC_ARC_SIMD_VMINW
UNSPEC_ARC_SIMD_VMULAW
UNSPEC_ARC_SIMD_VMULFAW
UNSPEC_ARC_SIMD_VMULFW
UNSPEC_ARC_SIMD_VMULW
UNSPEC_ARC_SIMD_VSUBAW
UNSPEC_ARC_SIMD_VSUBW
UNSPEC_ARC_SIMD_VSUMMW
UNSPEC_ARC_SIMD_VAND
UNSPEC_ARC_SIMD_VANDAW
UNSPEC_ARC_SIMD_VBIC
UNSPEC_ARC_SIMD_VBICAW
UNSPEC_ARC_SIMD_VOR
UNSPEC_ARC_SIMD_VXOR
UNSPEC_ARC_SIMD_VXORAW
UNSPEC_ARC_SIMD_VEQW
UNSPEC_ARC_SIMD_VLEW
UNSPEC_ARC_SIMD_VLTW
UNSPEC_ARC_SIMD_VNEW
UNSPEC_ARC_SIMD_VMR1AW
UNSPEC_ARC_SIMD_VMR1W
UNSPEC_ARC_SIMD_VMR2AW
UNSPEC_ARC_SIMD_VMR2W
UNSPEC_ARC_SIMD_VMR3AW
UNSPEC_ARC_SIMD_VMR3W
UNSPEC_ARC_SIMD_VMR4AW
UNSPEC_ARC_SIMD_VMR4W
UNSPEC_ARC_SIMD_VMR5AW
UNSPEC_ARC_SIMD_VMR5W
UNSPEC_ARC_SIMD_VMR6AW
UNSPEC_ARC_SIMD_VMR6W
UNSPEC_ARC_SIMD_VMR7AW
UNSPEC_ARC_SIMD_VMR7W
UNSPEC_ARC_SIMD_VMRB
UNSPEC_ARC_SIMD_VH264F
UNSPEC_ARC_SIMD_VH264FT
UNSPEC_ARC_SIMD_VH264FW
UNSPEC_ARC_SIMD_VVC1F
UNSPEC_ARC_SIMD_VVC1FT
;; Va, Vb, rc/limm builtins
(UNSPEC_ARC_SIMD_VBADDW 1050)
(UNSPEC_ARC_SIMD_VBMAXW 1051)
(UNSPEC_ARC_SIMD_VBMINW 1052)
(UNSPEC_ARC_SIMD_VBMULAW 1053)
(UNSPEC_ARC_SIMD_VBMULFW 1054)
(UNSPEC_ARC_SIMD_VBMULW 1055)
(UNSPEC_ARC_SIMD_VBRSUBW 1056)
(UNSPEC_ARC_SIMD_VBSUBW 1057)
UNSPEC_ARC_SIMD_VBADDW
UNSPEC_ARC_SIMD_VBMAXW
UNSPEC_ARC_SIMD_VBMINW
UNSPEC_ARC_SIMD_VBMULAW
UNSPEC_ARC_SIMD_VBMULFW
UNSPEC_ARC_SIMD_VBMULW
UNSPEC_ARC_SIMD_VBRSUBW
UNSPEC_ARC_SIMD_VBSUBW
;; Va, Vb, Ic builtins
(UNSPEC_ARC_SIMD_VASRW 1060)
(UNSPEC_ARC_SIMD_VSR8 1061)
(UNSPEC_ARC_SIMD_VSR8AW 1062)
UNSPEC_ARC_SIMD_VASRW
UNSPEC_ARC_SIMD_VSR8
UNSPEC_ARC_SIMD_VSR8AW
;; Va, Vb, Ic builtins
(UNSPEC_ARC_SIMD_VASRRWi 1065)
(UNSPEC_ARC_SIMD_VASRSRWi 1066)
(UNSPEC_ARC_SIMD_VASRWi 1067)
(UNSPEC_ARC_SIMD_VASRPWBi 1068)
(UNSPEC_ARC_SIMD_VASRRPWBi 1069)
(UNSPEC_ARC_SIMD_VSR8AWi 1070)
(UNSPEC_ARC_SIMD_VSR8i 1071)
UNSPEC_ARC_SIMD_VASRRWi
UNSPEC_ARC_SIMD_VASRSRWi
UNSPEC_ARC_SIMD_VASRWi
UNSPEC_ARC_SIMD_VASRPWBi
UNSPEC_ARC_SIMD_VASRRPWBi
UNSPEC_ARC_SIMD_VSR8AWi
UNSPEC_ARC_SIMD_VSR8i
;; Va, Vb, u8 (simm) builtins
(UNSPEC_ARC_SIMD_VMVAW 1075)
(UNSPEC_ARC_SIMD_VMVW 1076)
(UNSPEC_ARC_SIMD_VMVZW 1077)
(UNSPEC_ARC_SIMD_VD6TAPF 1078)
UNSPEC_ARC_SIMD_VMVAW
UNSPEC_ARC_SIMD_VMVW
UNSPEC_ARC_SIMD_VMVZW
UNSPEC_ARC_SIMD_VD6TAPF
;; Va, rlimm, u8 (simm) builtins
(UNSPEC_ARC_SIMD_VMOVAW 1080)
(UNSPEC_ARC_SIMD_VMOVW 1081)
(UNSPEC_ARC_SIMD_VMOVZW 1082)
UNSPEC_ARC_SIMD_VMOVAW
UNSPEC_ARC_SIMD_VMOVW
UNSPEC_ARC_SIMD_VMOVZW
;; Va, Vb builtins
(UNSPEC_ARC_SIMD_VABSAW 1085)
(UNSPEC_ARC_SIMD_VABSW 1086)
(UNSPEC_ARC_SIMD_VADDSUW 1087)
(UNSPEC_ARC_SIMD_VSIGNW 1088)
(UNSPEC_ARC_SIMD_VEXCH1 1089)
(UNSPEC_ARC_SIMD_VEXCH2 1090)
(UNSPEC_ARC_SIMD_VEXCH4 1091)
(UNSPEC_ARC_SIMD_VUPBAW 1092)
(UNSPEC_ARC_SIMD_VUPBW 1093)
(UNSPEC_ARC_SIMD_VUPSBAW 1094)
(UNSPEC_ARC_SIMD_VUPSBW 1095)
UNSPEC_ARC_SIMD_VABSAW
UNSPEC_ARC_SIMD_VABSW
UNSPEC_ARC_SIMD_VADDSUW
UNSPEC_ARC_SIMD_VSIGNW
UNSPEC_ARC_SIMD_VEXCH1
UNSPEC_ARC_SIMD_VEXCH2
UNSPEC_ARC_SIMD_VEXCH4
UNSPEC_ARC_SIMD_VUPBAW
UNSPEC_ARC_SIMD_VUPBW
UNSPEC_ARC_SIMD_VUPSBAW
UNSPEC_ARC_SIMD_VUPSBW
(UNSPEC_ARC_SIMD_VDIRUN 1100)
(UNSPEC_ARC_SIMD_VDORUN 1101)
(UNSPEC_ARC_SIMD_VDIWR 1102)
(UNSPEC_ARC_SIMD_VDOWR 1103)
UNSPEC_ARC_SIMD_VDIRUN
UNSPEC_ARC_SIMD_VDORUN
UNSPEC_ARC_SIMD_VDIWR
UNSPEC_ARC_SIMD_VDOWR
(UNSPEC_ARC_SIMD_VREC 1105)
(UNSPEC_ARC_SIMD_VRUN 1106)
(UNSPEC_ARC_SIMD_VRECRUN 1107)
(UNSPEC_ARC_SIMD_VENDREC 1108)
UNSPEC_ARC_SIMD_VREC
UNSPEC_ARC_SIMD_VRUN
UNSPEC_ARC_SIMD_VRECRUN
UNSPEC_ARC_SIMD_VENDREC
(UNSPEC_ARC_SIMD_VCAST 1200)
(UNSPEC_ARC_SIMD_VINTI 1201)
]
)
UNSPEC_ARC_SIMD_VCAST
UNSPEC_ARC_SIMD_VINTI
])
;; Scheduler descriptions for the simd instructions
(define_insn_reservation "simd_lat_0_insn" 1
@ -138,19 +136,19 @@
(define_insn_reservation "simd_lat_1_insn" 2
(eq_attr "type" "simd_vcompare, simd_vlogic,
simd_vmove_else_zero, simd_varith_1cycle")
simd_vmove_else_zero, simd_varith_1cycle")
"issue+simd_unit, nothing")
(define_insn_reservation "simd_lat_2_insn" 3
(eq_attr "type" "simd_valign, simd_vpermute,
simd_vpack, simd_varith_2cycle")
simd_vpack, simd_varith_2cycle")
"issue+simd_unit, nothing*2")
(define_insn_reservation "simd_lat_3_insn" 4
(eq_attr "type" "simd_valign_with_acc, simd_vpack_with_acc,
simd_vlogic_with_acc, simd_vload128,
simd_vmove_with_acc, simd_vspecial_3cycle,
simd_varith_with_acc")
simd_vlogic_with_acc, simd_vload128,
simd_vmove_with_acc, simd_vspecial_3cycle,
simd_varith_with_acc")
"issue+simd_unit, nothing*3")
(define_insn_reservation "simd_lat_4_insn" 5
@ -917,7 +915,7 @@
(define_insn "vmvaw_insn"
[(set (match_operand:V8HI 0 "vector_register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
(match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVAW))]
"TARGET_SIMD_SET"
"vmvaw %0, %1, %2"
@ -927,7 +925,7 @@
(define_insn "vmvw_insn"
[(set (match_operand:V8HI 0 "vector_register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
(match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVW))]
"TARGET_SIMD_SET"
"vmvw %0, %1, %2"
@ -937,7 +935,7 @@
(define_insn "vmvzw_insn"
[(set (match_operand:V8HI 0 "vector_register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
(match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMVZW))]
"TARGET_SIMD_SET"
"vmvzw %0, %1, %2"
@ -947,7 +945,7 @@
(define_insn "vd6tapf_insn"
[(set (match_operand:V8HI 0 "vector_register_operand" "=v")
(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
(unspec:V8HI [(match_operand:V8HI 1 "vector_register_operand" "v")
(match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VD6TAPF))]
"TARGET_SIMD_SET"
"vd6tapf %0, %1, %2"
@ -958,7 +956,7 @@
;; Va, rlimm, u8 (simm) insns
(define_insn "vmovaw_insn"
[(set (match_operand:V8HI 0 "vector_register_operand" "=v")
(unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r")
(unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r")
(match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVAW))]
"TARGET_SIMD_SET"
"vmovaw %0, %1, %2"
@ -968,7 +966,7 @@
(define_insn "vmovw_insn"
[(set (match_operand:V8HI 0 "vector_register_operand" "=v")
(unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r")
(unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r")
(match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVW))]
"TARGET_SIMD_SET"
"vmovw %0, %1, %2"
@ -978,7 +976,7 @@
(define_insn "vmovzw_insn"
[(set (match_operand:V8HI 0 "vector_register_operand" "=v")
(unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r")
(unspec:V8HI [(match_operand:SI 1 "nonmemory_operand" "r")
(match_operand:SI 2 "immediate_operand" "P")] UNSPEC_ARC_SIMD_VMOVZW))]
"TARGET_SIMD_SET"
"vmovzw %0, %1, %2"
@ -1123,7 +1121,7 @@
; DMA setup instructions
(define_insn "vdirun_insn"
[(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d")
(unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r")
(unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r")
(match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VDIRUN))]
"TARGET_SIMD_SET"
"vdirun %1, %2"
@ -1133,7 +1131,7 @@
(define_insn "vdorun_insn"
[(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d")
(unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r")
(unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r")
(match_operand:SI 2 "nonmemory_operand" "r")] UNSPEC_ARC_SIMD_VDORUN))]
"TARGET_SIMD_SET"
"vdorun %1, %2"
@ -1143,7 +1141,7 @@
(define_insn "vdiwr_insn"
[(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d,d")
(unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r,Cal")] UNSPEC_ARC_SIMD_VDIWR))]
(unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r,Cal")] UNSPEC_ARC_SIMD_VDIWR))]
"TARGET_SIMD_SET"
"vdiwr %0, %1"
[(set_attr "type" "simd_dma")
@ -1152,7 +1150,7 @@
(define_insn "vdowr_insn"
[(set (match_operand:SI 0 "arc_simd_dma_register_operand" "=d,d")
(unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r,Cal")] UNSPEC_ARC_SIMD_VDOWR))]
(unspec_volatile:SI [(match_operand:SI 1 "nonmemory_operand" "r,Cal")] UNSPEC_ARC_SIMD_VDOWR))]
"TARGET_SIMD_SET"
"vdowr %0, %1"
[(set_attr "type" "simd_dma")

6
gcc/testsuite/ChangeLog
View file

@ -1,3 +1,9 @@
2015-12-21 Claudiu Zissulescu <claziss@synopsys.com>
* gcc.target/arc/builtin_general.c: New test.
* gcc.target/arc/builtin_simd.c: Likewise.
* gcc.target/arc/builtin_special.c: Likewise.
2015-12-20 Jeff Law <law@redhat.com>
PR tree-optimization/64910

36
gcc/testsuite/gcc.target/arc/builtin_general.c Normal file
View file

@ -0,0 +1,36 @@
/* { dg-do compile } */
/* { dg-options "-O2 -Werror-implicit-function-declaration" } */
#define NORET1OP(name, op1type) \
void test_ ## name ## _0 (op1type a) \
{ \
__builtin_arc_ ## name (a); \
} \
void test_ ## name ## _1 (void) \
{ \
__builtin_arc_ ## name (0x10); \
}
#define RET1OP(name, rettype, op1type) \
rettype test_ ## name ## _0 (op1type a) \
{ \
return __builtin_arc_ ## name (a); \
} \
rettype test_ ## name ## _1 (void) \
{ \
return __builtin_arc_ ## name (0x10); \
}
NORET1OP (flag, unsigned int)
#if defined (__EM__) || defined (__HS__)
NORET1OP (kflag, unsigned int)
NORET1OP (seti, int)
#endif
#ifdef __ARC_NORM__
RET1OP (norm, int, int)
RET1OP (normw, int, short)
#endif

171
gcc/testsuite/gcc.target/arc/builtin_simd.c Normal file
View file

@ -0,0 +1,171 @@
/* { dg-do compile } */
/* { dg-options "-O2 -Werror-implicit-function-declaration -mARC700 -msimd" } */
#define STEST1(name, rettype, op1) \
rettype test_ ## name \
(void) \
{ \
return __builtin_arc_ ## name (op1); \
}
#define STEST2(name, rettype, op1, op2) \
rettype test_ ## name \
(void) \
{ \
return __builtin_arc_ ## name (op1, op2); \
}
#define STEST3(name, rettype, op1, op2, op3) \
rettype test_ ## name \
(void) \
{ \
return __builtin_arc_ ## name (op1, op2, op3); \
}
#define STEST4(name, rettype, op1, op2, op3, op4) \
rettype test_ ## name \
(void) \
{ \
return __builtin_arc_ ## name (op1, op2, op3, op4); \
}
typedef short v8hi __attribute__ ((vector_size (16)));
v8hi Va;
v8hi Vb;
v8hi Vc;
#define rlimm 0xf3eec0fe
#define Ic 0x02
#define Ib 0x02
#define u3 0x02
#define u6 0x1F
#define u8 0xB0
STEST2 ( vaddaw, v8hi, Vb, Vc)
STEST2 ( vaddw, v8hi, Vb, Vc)
STEST2 ( vavb, v8hi, Vb, Vc)
STEST2 ( vavrb, v8hi, Vb, Vc)
STEST2 ( vdifaw, v8hi, Vb, Vc)
STEST2 ( vdifw, v8hi, Vb, Vc)
STEST2 ( vmaxaw, v8hi, Vb, Vc)
STEST2 ( vmaxw, v8hi, Vb, Vc)
STEST2 ( vminaw, v8hi, Vb, Vc)
STEST2 ( vminw, v8hi, Vb, Vc)
STEST2 ( vmulaw, v8hi, Vb, Vc)
STEST2 (vmulfaw, v8hi, Vb, Vc)
STEST2 ( vmulfw, v8hi, Vb, Vc)
STEST2 ( vmulw, v8hi, Vb, Vc)
STEST2 ( vsubaw, v8hi, Vb, Vc)
STEST2 ( vsubw, v8hi, Vb, Vc)
STEST2 ( vsummw, v8hi, Vb, Vc)
STEST2 ( vand, v8hi, Vb, Vc)
STEST2 ( vandaw, v8hi, Vb, Vc)
STEST2 ( vbic, v8hi, Vb, Vc)
STEST2 ( vbicaw, v8hi, Vb, Vc)
STEST2 ( vor, v8hi, Vb, Vc)
STEST2 ( vxor, v8hi, Vb, Vc)
STEST2 ( vxoraw, v8hi, Vb, Vc)
STEST2 ( veqw, v8hi, Vb, Vc)
STEST2 ( vlew, v8hi, Vb, Vc)
STEST2 ( vltw, v8hi, Vb, Vc)
STEST2 ( vnew, v8hi, Vb, Vc)
STEST2 ( vmr1aw, v8hi, Vb, Vc)
STEST2 ( vmr1w, v8hi, Vb, Vc)
STEST2 ( vmr2aw, v8hi, Vb, Vc)
STEST2 ( vmr2w, v8hi, Vb, Vc)
STEST2 ( vmr3aw, v8hi, Vb, Vc)
STEST2 ( vmr3w, v8hi, Vb, Vc)
STEST2 ( vmr4aw, v8hi, Vb, Vc)
STEST2 ( vmr4w, v8hi, Vb, Vc)
STEST2 ( vmr5aw, v8hi, Vb, Vc)
STEST2 ( vmr5w, v8hi, Vb, Vc)
STEST2 ( vmr6aw, v8hi, Vb, Vc)
STEST2 ( vmr6w, v8hi, Vb, Vc)
STEST2 ( vmr7aw, v8hi, Vb, Vc)
STEST2 ( vmr7w, v8hi, Vb, Vc)
STEST2 ( vmrb, v8hi, Vb, Vc)
STEST2 ( vh264f, v8hi, Vb, Vc)
STEST2 (vh264ft, v8hi, Vb, Vc)
STEST2 (vh264fw, v8hi, Vb, Vc)
STEST2 ( vvc1f, v8hi, Vb, Vc)
STEST2 ( vvc1ft, v8hi, Vb, Vc)
STEST2 ( vbaddw, v8hi, Vb, rlimm)
STEST2 ( vbmaxw, v8hi, Vb, rlimm)
STEST2 ( vbminw, v8hi, Vb, rlimm)
STEST2 (vbmulaw, v8hi, Vb, rlimm)
STEST2 (vbmulfw, v8hi, Vb, rlimm)
STEST2 ( vbmulw, v8hi, Vb, rlimm)
STEST2 (vbrsubw, v8hi, Vb, rlimm)
STEST2 ( vbsubw, v8hi, Vb, rlimm)
/* Va, Vb, Ic instructions. */
STEST2 ( vasrw, v8hi, Vb, Ic)
STEST2 ( vsr8, v8hi, Vb, Ic)
STEST2 (vsr8aw, v8hi, Vb, Ic)
/* Va, Vb, u6 instructions. */
STEST2 ( vasrrwi, v8hi, Vb, u6)
STEST2 ( vasrsrwi, v8hi, Vb, u6)
STEST2 ( vasrwi, v8hi, Vb, u6)
STEST2 ( vasrpwbi, v8hi, Vb, u6)
STEST2 (vasrrpwbi, v8hi, Vb, u6)
STEST2 ( vsr8awi, v8hi, Vb, u6)
STEST2 ( vsr8i, v8hi, Vb, u6)
/* Va, Vb, u8 (simm) instructions. */
STEST2 ( vmvaw, v8hi, Vb, u8)
STEST2 ( vmvw, v8hi, Vb, u8)
STEST2 ( vmvzw, v8hi, Vb, u8)
STEST2 (vd6tapf, v8hi, Vb, u8)
/* Va, rlimm, u8 (simm) instructions. */
STEST2 (vmovaw, v8hi, rlimm, u8)
STEST2 ( vmovw, v8hi, rlimm, u8)
STEST2 (vmovzw, v8hi, rlimm, u8)
/* Va, Vb instructions. */
STEST1 ( vabsaw, v8hi, Vb)
STEST1 ( vabsw, v8hi, Vb)
STEST1 (vaddsuw, v8hi, Vb)
STEST1 ( vsignw, v8hi, Vb)
STEST1 ( vexch1, v8hi, Vb)
STEST1 ( vexch2, v8hi, Vb)
STEST1 ( vexch4, v8hi, Vb)
STEST1 ( vupbaw, v8hi, Vb)
STEST1 ( vupbw, v8hi, Vb)
STEST1 (vupsbaw, v8hi, Vb)
STEST1 ( vupsbw, v8hi, Vb)
/* DIb, rlimm, rlimm instructions. */
STEST2 (vdirun, void, rlimm, rlimm)
STEST2 (vdorun, void, rlimm, rlimm)
/* DIb, limm, rlimm instructions. */
STEST2 (vdiwr, void, u3, rlimm)
STEST2 (vdowr, void, u3, rlimm)
/* rlimm instructions. */
STEST1 ( vrec, void, rlimm)
STEST1 ( vrun, void, rlimm)
STEST1 (vrecrun, void, rlimm)
STEST1 (vendrec, void, rlimm)
/* Va, [Ib,u8] instructions. */
STEST3 (vld32wh, v8hi, Vb, Ic, u8)
STEST3 (vld32wl, v8hi, Vb, Ic, u8)
STEST3 ( vld64, v8hi, Vb, Ic, u8)
STEST3 ( vld32, v8hi, Vb, Ic, u8)
STEST2 (vld64w, v8hi, Ib, u8)
STEST2 (vld128, v8hi, Ib, u8)
STEST3 (vst128, void, Va, Ib, u8)
STEST3 ( vst64, void, Va, Ib, u8)
/* Va, [Ib, u8] instructions. */
STEST4 (vst16_n, void, Va, u3, Ib, u8)
STEST4 (vst32_n, void, Va, u3, Ib, u8)
STEST1 (vinti, void, u6)

42
gcc/testsuite/gcc.target/arc/builtin_special.c Normal file
View file

@ -0,0 +1,42 @@
/* { dg-do compile } */
/* { dg-options "-O2 -Werror-implicit-function-declaration" } */
#define NORET(name) \
void test_ ## name (void) \
{ \
__builtin_arc_ ## name (); \
}
#define RET(name, rettype) \
rettype test_ ## name (void) \
{ \
return __builtin_arc_ ## name (); \
}
#define NORET1OP(name, op1type) \
void test_ ## name ## _1 (void) \
{ \
__builtin_arc_ ## name (0x10); \
}
NORET (nop)
NORET (rtie)
#ifdef __A7__
NORET (sync)
#endif
NORET (brk)
NORET (swi)
NORET1OP (sleep, unsigned int)
#if defined (__A7__) || defined (__EM__) || defined (__HS__)
NORET1OP (trap_s, unsigned int)
NORET (unimp_s)
#endif
#if defined (__EM__) || defined (__HS__)
RET (clri, int)
#endif