From c1b361560f0785e02bb25d19de01cde3729dd35c Mon Sep 17 00:00:00 2001
From: Rohit Arul Raj <rohitarulraj@freescale.com>
Date: Mon, 4 Aug 2014 16:55:07 +0000
Subject: [PATCH] re PR middle-end/60102 (powerpc fp-bit ices at dwf_regno)

[gcc/testsuite]
2014-08-04  Rohit  <rohitarulraj@freescale.com>

	PR target/60102
	* gcc.target/powerpc/pr60102.c: New testcase.

From-SVN: r213598
---
 gcc/testsuite/ChangeLog                    |  5 +++++
 gcc/testsuite/gcc.target/powerpc/pr60102.c | 11 +++++++++++
 2 files changed, 16 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/powerpc/pr60102.c

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index e149043758a..efbb94dccfe 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2014-08-04  Rohit  <rohitarulraj@freescale.com>
+
+	PR target/60102
+	* gcc.target/powerpc/pr60102.c: New testcase.
+
 2014-08-04  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>
 
 	PR target/61713
diff --git a/gcc/testsuite/gcc.target/powerpc/pr60102.c b/gcc/testsuite/gcc.target/powerpc/pr60102.c
new file mode 100644
index 00000000000..d32e41d6873
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr60102.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-skip-if "not an SPE target" { ! powerpc_spe_nocache } { "*" } { "" } } */
+/* { dg-options "-mcpu=8548 -mspe -mabi=spe -g -mfloat-gprs=double" } */
+
+double
+pr60102 (double x, int m)
+{
+  double y;
+  y =  m % 2 ? x : 1;
+  return y;
+}