sync.md (sync_<optab>_12): Replace MIPS_SYNC_OP_12_NOT_NOP with MIPS_SYNC_OP_12_AND.
* config/mips/sync.md (sync_<optab>_12): Replace MIPS_SYNC_OP_12_NOT_NOP with MIPS_SYNC_OP_12_AND. (sync_old_<optab>_12): Remove third paramater to MIPS_SYNC_OLD_OP_12 macro, replace MIPS_SYNC_OLD_OP_12_NOT_NOP with MIPS_SYNC_OLD_OP_12_AND. (sync_new_<optab>_12): Replace MIPS_SYNC_NEW_OP_12_NOT_NOP with MIPS_SYNC_NEW_OP_12_AND. (sync_nand_12): Replace MIPS_SYNC_OP_12_NOT_NOT with MIPS_SYNC_OP_12_XOR, reduce length attribute to 40. (sync_old_nand_12): Remove third paramater to MIPS_SYNC_OLD_OP_12 macro, replace MIPS_SYNC_OLD_OP_12_NOT_NOT with MIPS_SYNC_OLD_OP_12_XOR and reduce length attribute to 40. (sync_new_nand_12): Replace MIPS_SYNC_NEW_OP_12_NOT_NOT with MIPS_SYNC_NEW_OP_12_XOR. * config/mips/mips.h (MIPS_SYNC_OP_12, MIPS_SYNC_OP_12_NOT_NOP, MIPS_SYNC_OP_12_NOT_NOT,MIPS_SYNC_OLD_OP_12_NOT_NOP, MIPS_SYNC_OLD_OP_12_NOT_NOT, MIPS_SYNC_NEW_OP_12, MIPS_SYNC_NEW_OP_12_NOT_NOP, MIPS_SYNC_NEW_OP_12_NOT_NOT, MIPS_SYNC_NAND, MIPS_SYNC_OLD_NAND, MIPS_SYNC_NEW_NAND): Rewritten to implement new __sync_nand semantics. (MIPS_SYNC_OLD_OP_12): Implement new __sync_nand semantics, and remove third parameter. (MIPS_SYNC_OLD_OP_12_NOT_NOP_REG, MIPS_SYNC_OLD_OP_12_NOT_NOT_REG): Removed. (MIPS_SYNC_OP_12_NOT_NOP): Renamed to MIPS_SYNC_OP_12_AND. (MIPS_SYNC_OP_12_NOT_NOT): Renamed to MIPS_SYNC_OP_12_XOR. (MIPS_SYNC_OLD_OP_12_NOT_NOP): Renamed to MIPS_SYNC_OLD_OP_12_AND. (MIPS_SYNC_OLD_OP_12_NOT_NOT): Renamed to MIPS_SYNC_OLD_OP_12_XOR. (MIPS_SYNC_NEW_OP_12_NOT_NOP): Renamed to MIPS_SYNC_NEW_OP_12_AND. (MIPS_SYNC_NEW_OP_12_NOT_NOT): Renamed to MIPS_SYNC_NEW_OP_12_XOR From-SVN: r142638
This commit is contained in:
David Daney
David Daney
parent
c34a77fd2f
commit
be3fbe5309
3 changed files with 78 additions and 49 deletions
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@ -1,3 +1,36 @@
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2008-12-09 David Daney <ddaney@caviumnetworks.com>
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* config/mips/sync.md (sync_<optab>_12): Replace
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MIPS_SYNC_OP_12_NOT_NOP with MIPS_SYNC_OP_12_AND.
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(sync_old_<optab>_12): Remove third paramater to
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MIPS_SYNC_OLD_OP_12 macro, replace MIPS_SYNC_OLD_OP_12_NOT_NOP
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with MIPS_SYNC_OLD_OP_12_AND.
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(sync_new_<optab>_12): Replace MIPS_SYNC_NEW_OP_12_NOT_NOP
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with MIPS_SYNC_NEW_OP_12_AND.
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(sync_nand_12): Replace MIPS_SYNC_OP_12_NOT_NOT with
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MIPS_SYNC_OP_12_XOR, reduce length attribute to 40.
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(sync_old_nand_12): Remove third paramater to MIPS_SYNC_OLD_OP_12
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macro, replace MIPS_SYNC_OLD_OP_12_NOT_NOT with
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MIPS_SYNC_OLD_OP_12_XOR and reduce length attribute to 40.
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(sync_new_nand_12): Replace MIPS_SYNC_NEW_OP_12_NOT_NOT with
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MIPS_SYNC_NEW_OP_12_XOR.
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* config/mips/mips.h (MIPS_SYNC_OP_12, MIPS_SYNC_OP_12_NOT_NOP,
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MIPS_SYNC_OP_12_NOT_NOT,MIPS_SYNC_OLD_OP_12_NOT_NOP,
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MIPS_SYNC_OLD_OP_12_NOT_NOT, MIPS_SYNC_NEW_OP_12,
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MIPS_SYNC_NEW_OP_12_NOT_NOP, MIPS_SYNC_NEW_OP_12_NOT_NOT,
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MIPS_SYNC_NAND, MIPS_SYNC_OLD_NAND, MIPS_SYNC_NEW_NAND): Rewritten
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to implement new __sync_nand semantics.
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(MIPS_SYNC_OLD_OP_12): Implement new __sync_nand semantics, and
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remove third parameter.
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(MIPS_SYNC_OLD_OP_12_NOT_NOP_REG,
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MIPS_SYNC_OLD_OP_12_NOT_NOT_REG): Removed.
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(MIPS_SYNC_OP_12_NOT_NOP): Renamed to MIPS_SYNC_OP_12_AND.
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(MIPS_SYNC_OP_12_NOT_NOT): Renamed to MIPS_SYNC_OP_12_XOR.
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(MIPS_SYNC_OLD_OP_12_NOT_NOP): Renamed to MIPS_SYNC_OLD_OP_12_AND.
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(MIPS_SYNC_OLD_OP_12_NOT_NOT): Renamed to MIPS_SYNC_OLD_OP_12_XOR.
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(MIPS_SYNC_NEW_OP_12_NOT_NOP): Renamed to MIPS_SYNC_NEW_OP_12_AND.
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(MIPS_SYNC_NEW_OP_12_NOT_NOT): Renamed to MIPS_SYNC_NEW_OP_12_XOR
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2008-12-09 Tobias Grosser <grosser@fim.uni-passau.de>
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* graphite.c (graphite_transform_loops): Always call find_transform ()
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@ -3183,24 +3183,25 @@ while (0)
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- Uses scratch register %4.
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NOT_OP are the optional instructions to do a bit-wise not
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operation in conjunction with an AND INSN to generate a sync_nand
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operation. */
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#define MIPS_SYNC_OP_12(INSN, NOT_OP) \
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AND_OP is an instruction done after INSN to mask INSN's result
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with the mask. For most operations, this is an AND with the
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inclusive mask (%1). For nand operations -- where the result of
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INSN is already correctly masked -- it instead performs a bitwise
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not. */
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#define MIPS_SYNC_OP_12(INSN, AND_OP) \
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"%(%<%[%|sync\n" \
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"1:\tll\t%4,%0\n" \
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"\tand\t%@,%4,%2\n" \
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NOT_OP \
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"\t" INSN "\t%4,%4,%z3\n" \
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"\tand\t%4,%4,%1\n" \
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AND_OP \
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"\tor\t%@,%@,%4\n" \
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"\tsc\t%@,%0\n" \
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"\tbeq%?\t%@,%.,1b\n" \
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"\tnop\n" \
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"\tsync%-%]%>%)"
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#define MIPS_SYNC_OP_12_NOT_NOP ""
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#define MIPS_SYNC_OP_12_NOT_NOT "\tnor\t%4,%4,%.\n"
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#define MIPS_SYNC_OP_12_AND "\tand\t%4,%4,%1\n"
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#define MIPS_SYNC_OP_12_XOR "\txor\t%4,%4,%1\n"
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/* Return an asm string that atomically:
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@ -3213,29 +3214,25 @@ while (0)
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- Uses scratch register %5.
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NOT_OP are the optional instructions to do a bit-wise not
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operation in conjunction with an AND INSN to generate a sync_nand
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operation.
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REG is used in conjunction with NOT_OP and is used to select the
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register operated on by the INSN. */
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#define MIPS_SYNC_OLD_OP_12(INSN, NOT_OP, REG) \
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AND_OP is an instruction done after INSN to mask INSN's result
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with the mask. For most operations, this is an AND with the
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inclusive mask (%1). For nand operations -- where the result of
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INSN is already correctly masked -- it instead performs a bitwise
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not. */
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#define MIPS_SYNC_OLD_OP_12(INSN, AND_OP) \
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"%(%<%[%|sync\n" \
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"1:\tll\t%0,%1\n" \
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"\tand\t%@,%0,%3\n" \
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NOT_OP \
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"\t" INSN "\t%5," REG ",%z4\n" \
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"\tand\t%5,%5,%2\n" \
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"\t" INSN "\t%5,%0,%z4\n" \
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AND_OP \
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"\tor\t%@,%@,%5\n" \
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"\tsc\t%@,%1\n" \
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"\tbeq%?\t%@,%.,1b\n" \
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"\tnop\n" \
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"\tsync%-%]%>%)"
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#define MIPS_SYNC_OLD_OP_12_NOT_NOP ""
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#define MIPS_SYNC_OLD_OP_12_NOT_NOP_REG "%0"
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#define MIPS_SYNC_OLD_OP_12_NOT_NOT "\tnor\t%5,%0,%.\n"
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#define MIPS_SYNC_OLD_OP_12_NOT_NOT_REG "%5"
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#define MIPS_SYNC_OLD_OP_12_AND "\tand\t%5,%5,%2\n"
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#define MIPS_SYNC_OLD_OP_12_XOR "\txor\t%5,%5,%2\n"
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/* Return an asm string that atomically:
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@ -3246,24 +3243,25 @@ while (0)
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- Sets %0 to the new value of %1.
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NOT_OP are the optional instructions to do a bit-wise not
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operation in conjunction with an AND INSN to generate a sync_nand
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operation. */
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#define MIPS_SYNC_NEW_OP_12(INSN, NOT_OP) \
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AND_OP is an instruction done after INSN to mask INSN's result
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with the mask. For most operations, this is an AND with the
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inclusive mask (%1). For nand operations -- where the result of
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INSN is already correctly masked -- it instead performs a bitwise
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not. */
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#define MIPS_SYNC_NEW_OP_12(INSN, AND_OP) \
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"%(%<%[%|sync\n" \
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"1:\tll\t%0,%1\n" \
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"\tand\t%@,%0,%3\n" \
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NOT_OP \
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"\t" INSN "\t%0,%0,%z4\n" \
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"\tand\t%0,%0,%2\n" \
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AND_OP \
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"\tor\t%@,%@,%0\n" \
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"\tsc\t%@,%1\n" \
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"\tbeq%?\t%@,%.,1b\n" \
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"\tnop\n" \
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"\tsync%-%]%>%)"
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#define MIPS_SYNC_NEW_OP_12_NOT_NOP ""
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#define MIPS_SYNC_NEW_OP_12_NOT_NOT "\tnor\t%0,%0,%.\n"
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#define MIPS_SYNC_NEW_OP_12_AND "\tand\t%0,%0,%2\n"
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#define MIPS_SYNC_NEW_OP_12_XOR "\txor\t%0,%0,%2\n"
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/* Return an asm string that atomically:
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@ -3301,7 +3299,7 @@ while (0)
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/* Return an asm string that atomically:
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- Sets memory reference %0 to ~%0 AND %1.
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- Sets memory reference %0 to ~(%0 AND %1).
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SUFFIX is the suffix that should be added to "ll" and "sc"
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instructions. INSN is the and instruction needed to and a register
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@ -3309,8 +3307,8 @@ while (0)
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#define MIPS_SYNC_NAND(SUFFIX, INSN) \
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"%(%<%[%|sync\n" \
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"1:\tll" SUFFIX "\t%@,%0\n" \
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"\tnor\t%@,%@,%.\n" \
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"\t" INSN "\t%@,%@,%1\n" \
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"\tnor\t%@,%@,%.\n" \
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"\tsc" SUFFIX "\t%@,%0\n" \
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"\tbeq%?\t%@,%.,1b\n" \
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"\tnop\n" \
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@ -3318,7 +3316,7 @@ while (0)
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/* Return an asm string that atomically:
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- Sets memory reference %1 to ~%1 AND %2.
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- Sets memory reference %1 to ~(%1 AND %2).
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- Sets register %0 to the old value of memory reference %1.
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@ -3328,8 +3326,8 @@ while (0)
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#define MIPS_SYNC_OLD_NAND(SUFFIX, INSN) \
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"%(%<%[%|sync\n" \
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"1:\tll" SUFFIX "\t%0,%1\n" \
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"\tnor\t%@,%0,%.\n" \
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"\t" INSN "\t%@,%@,%2\n" \
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"\t" INSN "\t%@,%0,%2\n" \
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"\tnor\t%@,%@,%.\n" \
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"\tsc" SUFFIX "\t%@,%1\n" \
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"\tbeq%?\t%@,%.,1b\n" \
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"\tnop\n" \
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@ -3337,7 +3335,7 @@ while (0)
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/* Return an asm string that atomically:
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- Sets memory reference %1 to ~%1 AND %2.
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- Sets memory reference %1 to ~(%1 AND %2).
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- Sets register %0 to the new value of memory reference %1.
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@ -3347,11 +3345,11 @@ while (0)
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#define MIPS_SYNC_NEW_NAND(SUFFIX, INSN) \
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"%(%<%[%|sync\n" \
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"1:\tll" SUFFIX "\t%0,%1\n" \
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"\tnor\t%0,%0,%.\n" \
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"\t" INSN "\t%@,%0,%2\n" \
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"\t" INSN "\t%0,%0,%2\n" \
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"\tnor\t%@,%0,%.\n" \
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"\tsc" SUFFIX "\t%@,%1\n" \
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"\tbeq%?\t%@,%.,1b%~\n" \
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"\t" INSN "\t%0,%0,%2\n" \
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"\tnor\t%0,%0,%.\n" \
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"\tsync%-%]%>%)"
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/* Return an asm string that atomically:
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@ -127,7 +127,7 @@
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"GENERATE_LL_SC"
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{
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return (mips_output_sync_loop
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(MIPS_SYNC_OP_12 ("<insn>", MIPS_SYNC_OP_12_NOT_NOP)));
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(MIPS_SYNC_OP_12 ("<insn>", MIPS_SYNC_OP_12_AND)));
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}
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[(set_attr "length" "40")])
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@ -164,8 +164,7 @@
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"GENERATE_LL_SC"
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{
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return (mips_output_sync_loop
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(MIPS_SYNC_OLD_OP_12 ("<insn>", MIPS_SYNC_OLD_OP_12_NOT_NOP,
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MIPS_SYNC_OLD_OP_12_NOT_NOP_REG)));
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(MIPS_SYNC_OLD_OP_12 ("<insn>", MIPS_SYNC_OLD_OP_12_AND)));
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}
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[(set_attr "length" "40")])
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@ -207,7 +206,7 @@
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"GENERATE_LL_SC"
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{
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return (mips_output_sync_loop
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(MIPS_SYNC_NEW_OP_12 ("<insn>", MIPS_SYNC_NEW_OP_12_NOT_NOP)));
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(MIPS_SYNC_NEW_OP_12 ("<insn>", MIPS_SYNC_NEW_OP_12_AND)));
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}
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[(set_attr "length" "40")])
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@ -239,9 +238,9 @@
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"GENERATE_LL_SC"
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{
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return (mips_output_sync_loop
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(MIPS_SYNC_OP_12 ("and", MIPS_SYNC_OP_12_NOT_NOT)));
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(MIPS_SYNC_OP_12 ("and", MIPS_SYNC_OP_12_XOR)));
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}
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[(set_attr "length" "44")])
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[(set_attr "length" "40")])
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(define_expand "sync_old_nand<mode>"
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[(parallel [
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@ -274,10 +273,9 @@
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"GENERATE_LL_SC"
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{
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return (mips_output_sync_loop
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(MIPS_SYNC_OLD_OP_12 ("and", MIPS_SYNC_OLD_OP_12_NOT_NOT,
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MIPS_SYNC_OLD_OP_12_NOT_NOT_REG)));
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(MIPS_SYNC_OLD_OP_12 ("and", MIPS_SYNC_OLD_OP_12_XOR)));
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}
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[(set_attr "length" "44")])
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[(set_attr "length" "40")])
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(define_expand "sync_new_nand<mode>"
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[(parallel [
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@ -315,7 +313,7 @@
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"GENERATE_LL_SC"
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{
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return (mips_output_sync_loop
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(MIPS_SYNC_NEW_OP_12 ("and", MIPS_SYNC_NEW_OP_12_NOT_NOT)));
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(MIPS_SYNC_NEW_OP_12 ("and", MIPS_SYNC_NEW_OP_12_XOR)));
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}
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[(set_attr "length" "40")])
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