invoke.texi (C6X Options): New section.
gcc/ * doc/invoke.texi (C6X Options): New section. * doc/md.texi (TI C6X family): New section. * config.gcc: Handle tic6x, in particular tic6x-*-elf and tic6x-*-uclinux. * longlong.h (add_ssaaaa, __umulsidi3, umul_ppmm, count_leading_zeros, count_trailing_zeros, UMUL_TIME, UDIV_TIME): Provide C6X definitions. * config/c6x/c6x.md: New file. * config/c6x/constraints.md: New file. * config/c6x/predicates.md: New file. * config/c6x/c6x-sched.md.in: New file. * config/c6x/c6x-sched.md: New file. * config/c6x/gensched.sh: New file. * config/c6x/c6x-mult.md.in: New file. * config/c6x/genmult.sh: New file. * config/c6x/c6x-mult.md: New file. * config/c6x/sync.md: New file. * config/c6x/c6x-protos.h: New file. * config/c6x/sfp-machine.h: New file. * config/c6x/c6x.c: New file. * config/c6x/c6x.h: New file. * config/c6x/crti.s: New file. * config/c6x/crtn.s: New file. * config/c6x/lib1funcs.asm: New file. * config/c6x/c6x-modes.def: New file. * config/c6x/genopt.sh: New file. * config/c6x/c6x.opt: New file. * config/c6x/c6x-tables.opt: New file. * config/c6x/c6x-opts.h: New file. * config/c6x/c6x-isas.def: New file. * config/c6x/elf.h: New file. * config/c6x/elf-common.h: New file. * config/c6x/uclinux-elf.h: New file. * config/c6x/t-c6x: New file. * config/c6x/t-c6x-elf: New file. * config/c6x/t-c6x-uclinux: New file. * config/c6x/t-c6x-softfp: New file. * config/c6x/gtd.c: New file. * config/c6x/gtf.c: New file. * config/c6x/ltd.c: New file. * config/c6x/ltf.c: New file. * config/c6x/ged.c: New file. * config/c6x/gef.c: New file. * config/c6x/led.c: New file. * config/c6x/lef.c: New file. * config/c6x/eqd.c: New file. * config/c6x/eqf.c: New file. * config/c6x/libgcc-c6xeabi.ver: New file. contrib/ * gcc_update: Add C6X generated files. * contrib/config-list.mk: Add c6x-elf and c6x-uclinux. libgcc/ * config.host: Handle tic6x-*-*. * config/c6x/c6x-abi.h: New file. From-SVN: r176308
This commit is contained in:
Bernd Schmidt
Bernd Schmidt
parent
9e36aa2367
commit
bcead286bf
56 changed files with 14796 additions and 4 deletions
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@ -1,3 +1,8 @@
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2011-07-15 Bernd Schmidt <bernds@codesourcery.com>
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* gcc_update: Add C6X generated files.
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* contrib/config-list.mk: Add c6x-elf and c6x-uclinux.
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2011-07-01 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
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* config-list.mk (LIST): Append OPT-enable-obsolete to
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@ -18,7 +18,7 @@ LIST = alpha-linux-gnu alpha-freebsd6 alpha-netbsd alpha-openbsd \
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arm-linux-androideabi arm-uclinux_eabi arm-ecos-elf arm-eabi \
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arm-symbianelf arm-rtems arm-elf arm-wince-pe avr-rtems avr-elf \
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bfin-elf bfin-uclinux bfin-linux-uclibc bfin-rtems bfin-openbsd \
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cris-elf cris-linux crisv32-elf crisv32-linux fido-elf \
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c6x-elf c6x-uclinux cris-elf cris-linux crisv32-elf crisv32-linux fido-elf \
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fr30-elf frv-elf frv-linux h8300-elf h8300-rtems hppa-linux-gnu \
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hppa-linux-gnuOPT-enable-sjlj-exceptions=yes hppa64-linux-gnu \
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hppa2.0-hpux10.1 hppa64-hpux11.3 \
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@ -82,6 +82,9 @@ gcc/fixinc/fixincl.x: gcc/fixinc/fixincl.tpl gcc/fixinc/inclhack.def
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gcc/config/arm/arm-tune.md: gcc/config/arm/arm-cores.def gcc/config/arm/gentune.sh
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gcc/config/arm/arm-tables.opt: gcc/config/arm/arm-arches.def gcc/config/arm/arm-cores.def gcc/config/arm/arm-fpus.def gcc/config/arm/genopt.sh
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gcc/config/avr/avr-tables.opt: gcc/config/avr/avr-mcus.def gcc/config/avr/genopt.sh
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gcc/config/c6x/c6x-tables.opt: gcc/config/c6x/c6x-isas.def gcc/config/c6x/genopt.sh
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gcc/config/c6x/c6x-sched.md: gcc/config/c6x/c6x-sched.md.in gcc/config/c6x/gensched.sh
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gcc/config/c6x/c6x-mult.md: gcc/config/c6x/c6x-mult.md.in gcc/config/c6x/genmult.sh
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gcc/config/m68k/m68k-tables.opt: gcc/config/m68k/m68k-devices.def gcc/config/m68k/m68k-isas.def gcc/config/m68k/m68k-microarchs.def gcc/config/m68k/genopt.sh
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gcc/config/mips/mips-tables.opt: gcc/config/mips/mips-cpus.def gcc/config/mips/genopt.sh
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gcc/config/rs6000/rs6000-tables.opt: gcc/config/rs6000/rs6000-cpus.def gcc/config/rs6000/genopt.sh
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@ -1,3 +1,54 @@
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2011-07-15 Bernd Schmidt <bernds@codesourcery.com>
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* doc/invoke.texi (C6X Options): New section.
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* doc/md.texi (TI C6X family): New section.
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* config.gcc: Handle tic6x, in particular tic6x-*-elf and
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tic6x-*-uclinux.
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* longlong.h (add_ssaaaa, __umulsidi3, umul_ppmm,
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count_leading_zeros, count_trailing_zeros, UMUL_TIME, UDIV_TIME):
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Provide C6X definitions.
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* config/c6x/c6x.md: New file.
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* config/c6x/constraints.md: New file.
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* config/c6x/predicates.md: New file.
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* config/c6x/c6x-sched.md.in: New file.
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* config/c6x/c6x-sched.md: New file.
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* config/c6x/gensched.sh: New file.
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* config/c6x/c6x-mult.md.in: New file.
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* config/c6x/genmult.sh: New file.
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* config/c6x/c6x-mult.md: New file.
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* config/c6x/sync.md: New file.
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* config/c6x/c6x-protos.h: New file.
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* config/c6x/sfp-machine.h: New file.
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* config/c6x/c6x.c: New file.
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* config/c6x/c6x.h: New file.
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* config/c6x/crti.s: New file.
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* config/c6x/crtn.s: New file.
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* config/c6x/lib1funcs.asm: New file.
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* config/c6x/c6x-modes.def: New file.
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* config/c6x/genopt.sh: New file.
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* config/c6x/c6x.opt: New file.
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* config/c6x/c6x-tables.opt: New file.
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* config/c6x/c6x-opts.h: New file.
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* config/c6x/c6x-isas.def: New file.
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* config/c6x/elf.h: New file.
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* config/c6x/elf-common.h: New file.
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* config/c6x/uclinux-elf.h: New file.
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* config/c6x/t-c6x: New file.
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* config/c6x/t-c6x-elf: New file.
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* config/c6x/t-c6x-uclinux: New file.
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* config/c6x/t-c6x-softfp: New file.
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* config/c6x/gtd.c: New file.
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* config/c6x/gtf.c: New file.
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* config/c6x/ltd.c: New file.
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* config/c6x/ltf.c: New file.
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* config/c6x/ged.c: New file.
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* config/c6x/gef.c: New file.
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* config/c6x/led.c: New file.
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* config/c6x/lef.c: New file.
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* config/c6x/eqd.c: New file.
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* config/c6x/eqf.c: New file.
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* config/c6x/libgcc-c6xeabi.ver: New file.
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2011-07-14 Andrew Pinski <pinskia@gmail.com>
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PR tree-opt/49309
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@ -437,6 +437,11 @@ sh[123456789lbe]*-*-* | sh-*-*)
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v850*-*-*)
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cpu_type=v850
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;;
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tic6x-*-*)
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cpu_type=c6x
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extra_headers="c6x_intrinsics.h"
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extra_options="${extra_options} c6x/c6x-tables.opt"
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;;
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xtensa*-*-*)
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extra_options="${extra_options} fused-madd.opt"
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;;
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@ -2561,7 +2566,24 @@ spu-*-elf*)
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c_target_objs="${c_target_objs} spu-c.o"
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cxx_target_objs="${cxx_target_objs} spu-c.o"
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;;
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tic6x-*-elf)
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tm_file="elfos.h ${tm_file} c6x/elf-common.h c6x/elf.h"
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tm_file="${tm_file} dbxelf.h tm-dwarf2.h newlib-stdint.h"
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libgcc_tm_file="${libgcc_tm_file} c6x/c6x-abi.h"
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tmake_file="c6x/t-c6x c6x/t-c6x-elf"
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tmake_file="${tmake_file} c6x/t-c6x-softfp soft-fp/t-softfp"
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use_collect2=no
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;;
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tic6x-*-uclinux)
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tm_file="elfos.h ${tm_file} gnu-user.h linux.h c6x/elf-common.h c6x/uclinux-elf.h"
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tm_file="${tm_file} dbxelf.h tm-dwarf2.h glibc-stdint.h"
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tm_file="${tm_file} ./sysroot-suffix.h"
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libgcc_tm_file="${libgcc_tm_file} c6x/c6x-abi.h"
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tmake_file="t-slibgcc-elf-ver t-sysroot-suffix"
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tmake_file="${tmake_file} c6x/t-c6x c6x/t-c6x-elf c6x/t-c6x-uclinux"
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tmake_file="${tmake_file} c6x/t-c6x-softfp soft-fp/t-softfp"
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use_collect2=no
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;;
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v850*-*-*)
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case ${target} in
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v850e2v3-*-*)
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@ -3500,6 +3522,20 @@ case "${target}" in
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done
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;;
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tic6x-*-*)
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supported_defaults="arch"
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case ${with_arch} in
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"" | c62x | c64x | c64x+ | c67x | c67x+ | c674x)
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# OK
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;;
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*)
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echo "Unknown arch used in --with-arch=$with_arch." 1>&2
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exit 1
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;;
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esac
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;;
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v850*-*-*)
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supported_defaults=cpu
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case ${with_cpu} in
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38
gcc/config/c6x/c6x-isas.def
Normal file
38
gcc/config/c6x/c6x-isas.def
Normal file
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@ -0,0 +1,38 @@
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/* C6X ISA names.
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Copyright (C) 2011
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Free Software Foundation, Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 3, or (at your option)
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any later version.
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GCC is distributed in the hope that it will be useful, but
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WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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/* Define ISAs for the -march option, used both in C6X.c and to
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generate c6x-tables.opt. Before including this file, define a
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macro:
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C6X_ISA (NAME, ENUM_VALUE, FLAGS)
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where NAME is the name for use with -march=, ENUM_VALUE is an enum
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corresponding to this arch, and FLAGS is a combination of flags
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that together specify the available instructions. */
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C6X_ISA("c62x", C6X_CPU_C62X, C6X_INSNS_C62X)
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C6X_ISA("c64x", C6X_CPU_C64X, C6X_INSNS_C62X | C6X_INSNS_C64X)
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C6X_ISA("c64x+", C6X_CPU_C64XP, C6X_INSNS_C62X | C6X_INSNS_C64X | C6X_INSNS_C64XP)
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C6X_ISA("c67x", C6X_CPU_C67X, C6X_INSNS_C62X | C6X_INSNS_C67X)
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C6X_ISA("c67x+", C6X_CPU_C67XP, C6X_INSNS_C62X | C6X_INSNS_C67X | C6X_INSNS_C67XP)
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C6X_ISA("c674x", C6X_CPU_C674X,
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(C6X_INSNS_C62X | C6X_INSNS_C64X | C6X_INSNS_C64XP | C6X_INSNS_C67X
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| C6X_INSNS_C67XP | C6X_INSNS_C674X))
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24
gcc/config/c6x/c6x-modes.def
Normal file
24
gcc/config/c6x/c6x-modes.def
Normal file
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@ -0,0 +1,24 @@
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/* Definitions of target machine for GNU compiler, for TI C6x.
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Copyright (C) 2010, 2011 Free Software Foundation, Inc.
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This file is part of GCC.
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GCC is free software; you can redistribute it and/or modify it
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||||
under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
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option) any later version.
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||||
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GCC is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
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||||
License for more details.
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||||
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||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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VECTOR_MODES (INT, 4); /* V4QI V2HI */
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VECTOR_MODES (INT, 8); /* V8QI V4HI V2SI */
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VECTOR_MODE (FRACT, SQ, 2); /* V2SQ. */
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VECTOR_MODE (FRACT, HQ, 2); /* V2HQ. */
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840
gcc/config/c6x/c6x-mult.md
Normal file
840
gcc/config/c6x/c6x-mult.md
Normal file
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@ -0,0 +1,840 @@
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;; -*- buffer-read-only: t -*-
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;; Generated automatically from c6x-mult.md.in by genmult.sh
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;; Multiplication patterns for TI C6X.
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;; This file is processed by genmult.sh to produce two variants of each
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;; pattern, a normal one and a real_mult variant for modulo scheduling.
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;; Copyright (C) 2010, 2011 Free Software Foundation, Inc.
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;; Contributed by Bernd Schmidt <bernds@codesourcery.com>
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;; Contributed by CodeSourcery.
|
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;;
|
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;; This file is part of GCC.
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;;
|
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;; GCC is free software; you can redistribute it and/or modify
|
||||
;; it under the terms of the GNU General Public License as published by
|
||||
;; the Free Software Foundation; either version 3, or (at your option)
|
||||
;; any later version.
|
||||
;;
|
||||
;; GCC is distributed in the hope that it will be useful,
|
||||
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
;; GNU General Public License for more details.
|
||||
;;
|
||||
;; You should have received a copy of the GNU General Public License
|
||||
;; along with GCC; see the file COPYING3. If not see
|
||||
;; <http://www.gnu.org/licenses/>.
|
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|
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;; -------------------------------------------------------------------------
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;; Miscellaneous insns that execute on the M units
|
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;; -------------------------------------------------------------------------
|
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|
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(define_insn "rotlsi3"
|
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[(set (match_operand:SI 0 "register_operand" "=a,b,a,b")
|
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(rotate:SI (match_operand:SI 1 "register_operand" "a,b,?b,?a")
|
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(match_operand:SI 2 "reg_or_ucst5_operand" "aIu5,bIu5,aIu5,bIu5")))]
|
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"TARGET_INSNS_64"
|
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"%|%.\\trotl\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "units" "m")
|
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(set_attr "type" "mpy2")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "bitrevsi2"
|
||||
[(set (match_operand:SI 0 "register_operand" "=a,a,b,b")
|
||||
(unspec:SI [(match_operand:SI 1 "register_operand" "a,?b,b,?a")]
|
||||
UNSPEC_BITREV))]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tbitr\\t%$\\t%1, %0"
|
||||
[(set_attr "units" "m")
|
||||
(set_attr "type" "mpy2")
|
||||
(set_attr "cross" "n,y,n,y")])
|
||||
|
||||
;; Vector average.
|
||||
|
||||
(define_insn "avgv2hi3"
|
||||
[(set (match_operand:V2HI 0 "register_operand" "=a,b,a,b")
|
||||
(unspec:V2HI [(match_operand:V2HI 1 "register_operand" "a,b,?b,?a")
|
||||
(match_operand:V2HI 2 "register_operand" "a,b,a,b")] UNSPEC_AVG))]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tavg2\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "units" "m")
|
||||
(set_attr "type" "mpy2")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "uavgv4qi3"
|
||||
[(set (match_operand:V4QI 0 "register_operand" "=a,b,a,b")
|
||||
(unspec:V4QI [(match_operand:V4QI 1 "register_operand" "a,b,?b,?a")
|
||||
(match_operand:V4QI 2 "register_operand" "a,b,a,b")] UNSPEC_AVG))]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tavgu4\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "units" "m")
|
||||
(set_attr "type" "mpy2")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; Multiplication
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
(define_insn "mulhi3"
|
||||
[(set (match_operand:HI 0 "register_operand" "=a,b,a,b")
|
||||
(mult:HI (match_operand:HI 1 "register_operand" "a,b,?b,?a")
|
||||
(match_operand:HI 2 "reg_or_scst5_operand" "aIs5,bIs5,aIs5,bIs5")))]
|
||||
""
|
||||
"%|%.\\tmpy\\t%$\\t%2, %1, %0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhisi3_const"
|
||||
[(set (match_operand:SI 0 "register_operand" "=a,b,ab")
|
||||
(mult:SI (sign_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "a,b,?ab"))
|
||||
(match_operand:HI 2 "scst5_operand" "Is5,Is5,Is5")))]
|
||||
""
|
||||
"%|%.\\tmpy\\t%$\\t%2, %1, %0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y")])
|
||||
|
||||
(define_insn "*mulhisi3_insn"
|
||||
[(set (match_operand:SI 0 "register_operand" "=a,b,a,b")
|
||||
(mult:SI (sign_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "%a,b,?a,?b"))
|
||||
(sign_extend:SI
|
||||
(match_operand:HI 2 "reg_or_scst5_operand" "a,b,b,a"))))]
|
||||
""
|
||||
"%|%.\\tmpy\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhisi3_lh"
|
||||
[(set (match_operand:SI 0 "register_operand" "=a,b,a,b")
|
||||
(mult:SI (sign_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "a,b,?a,?b"))
|
||||
(ashiftrt:SI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")
|
||||
(const_int 16))))]
|
||||
""
|
||||
"%|%.\\tmpylh\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhisi3_hl"
|
||||
[(set (match_operand:SI 0 "register_operand" "=a,b,a,b")
|
||||
(mult:SI (ashiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "a,b,?a,?b")
|
||||
(const_int 16))
|
||||
(sign_extend:SI
|
||||
(match_operand:HI 2 "register_operand" "a,b,b,a"))))]
|
||||
""
|
||||
"%|%.\\tmpyhl\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhisi3_hh"
|
||||
[(set (match_operand:SI 0 "register_operand" "=a,b,a,b")
|
||||
(mult:SI (ashiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "%a,b,?a,?b")
|
||||
(const_int 16))
|
||||
(ashiftrt:SI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")
|
||||
(const_int 16))))]
|
||||
""
|
||||
"%|%.\\tmpyh\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "umulhisi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=a,b,a,b")
|
||||
(mult:SI (zero_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "%a,b,?a,?b"))
|
||||
(zero_extend:SI
|
||||
(match_operand:HI 2 "register_operand" "a,b,b,a"))))]
|
||||
""
|
||||
"%|%.\\tmpyu\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "umulhisi3_lh"
|
||||
[(set (match_operand:SI 0 "register_operand" "=a,b,a,b")
|
||||
(mult:SI (zero_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "a,b,?a,?b"))
|
||||
(lshiftrt:SI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")
|
||||
(const_int 16))))]
|
||||
""
|
||||
"%|%.\\tmpylhu\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "umulhisi3_hl"
|
||||
[(set (match_operand:SI 0 "register_operand" "=a,b,a,b")
|
||||
(mult:SI (lshiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "a,b,?a,?b")
|
||||
(const_int 16))
|
||||
(zero_extend:SI
|
||||
(match_operand:HI 2 "register_operand" "a,b,b,a"))))]
|
||||
""
|
||||
"%|%.\\tmpyhlu\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "umulhisi3_hh"
|
||||
[(set (match_operand:SI 0 "register_operand" "=a,b,a,b")
|
||||
(mult:SI (lshiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "%a,b,?a,?b")
|
||||
(const_int 16))
|
||||
(lshiftrt:SI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")
|
||||
(const_int 16))))]
|
||||
""
|
||||
"%|%.\\tmpyhu\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "usmulhisi3_const"
|
||||
[(set (match_operand:SI 0 "register_operand" "=a,b,ab")
|
||||
(mult:SI (zero_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "a,b,?ab"))
|
||||
(match_operand:SI 2 "scst5_operand" "Is5,Is5,Is5")))]
|
||||
""
|
||||
"%|%.\\tmpysu\\t%$\\t%2, %1, %0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y")])
|
||||
|
||||
(define_insn "*usmulhisi3_insn"
|
||||
[(set (match_operand:SI 0 "register_operand" "=a,b,a,b")
|
||||
(mult:SI (zero_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "a,b,?a,?b"))
|
||||
(sign_extend:SI
|
||||
(match_operand:HI 2 "reg_or_scst5_operand" "aIs5,bIs5,bIs5,aIs5"))))]
|
||||
""
|
||||
"%|%.\\tmpyus\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "usmulhisi3_lh"
|
||||
[(set (match_operand:SI 0 "register_operand" "=a,b,a,b")
|
||||
(mult:SI (zero_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "a,b,?a,?b"))
|
||||
(ashiftrt:SI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")
|
||||
(const_int 16))))]
|
||||
""
|
||||
"%|%.\\tmpyluhs\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "usmulhisi3_hl"
|
||||
[(set (match_operand:SI 0 "register_operand" "=a,b,a,b")
|
||||
(mult:SI (lshiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "a,b,?a,?b")
|
||||
(const_int 16))
|
||||
(sign_extend:SI
|
||||
(match_operand:HI 2 "register_operand" "a,b,b,a"))))]
|
||||
""
|
||||
"%|%.\\tmpyhuls\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "usmulhisi3_hh"
|
||||
[(set (match_operand:SI 0 "register_operand" "=a,b,a,b")
|
||||
(mult:SI (lshiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "a,b,?a,?b")
|
||||
(const_int 16))
|
||||
(ashiftrt:SI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")
|
||||
(const_int 16))))]
|
||||
""
|
||||
"%|%.\\tmpyhus\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulsi3_insn"
|
||||
[(set (match_operand:SI 0 "register_operand" "=a,b,a,b")
|
||||
(mult:SI (match_operand:SI 1 "register_operand" "%a,b,?a,?b")
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")))]
|
||||
"TARGET_MPY32"
|
||||
"%|%.\\tmpy32\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "<u>mulsidi3"
|
||||
[(set (match_operand:DI 0 "register_operand" "=a,b,a,b")
|
||||
(mult:DI (any_ext:DI
|
||||
(match_operand:SI 1 "register_operand" "%a,b,?a,?b"))
|
||||
(any_ext:DI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a"))))]
|
||||
"TARGET_MPY32"
|
||||
"%|%.\\tmpy32<u>\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "usmulsidi3"
|
||||
[(set (match_operand:DI 0 "register_operand" "=a,b,a,b")
|
||||
(mult:DI (zero_extend:DI
|
||||
(match_operand:SI 1 "register_operand" "a,b,?a,?b"))
|
||||
(sign_extend:DI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a"))))]
|
||||
"TARGET_MPY32"
|
||||
"%|%.\\tmpy32us\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
;; Widening vector multiply and dot product
|
||||
|
||||
(define_insn "mulv2hiv2si3"
|
||||
[(set (match_operand:V2SI 0 "register_operand" "=a,b,a,b")
|
||||
(mult:V2SI
|
||||
(sign_extend:V2SI (match_operand:V2HI 1 "register_operand" "a,b,a,b"))
|
||||
(sign_extend:V2SI (match_operand:V2HI 2 "register_operand" "a,b,?b,?a"))))]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tmpy2\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "umulv4qiv4hi3"
|
||||
[(set (match_operand:V4HI 0 "register_operand" "=a,b,a,b")
|
||||
(mult:V4HI
|
||||
(zero_extend:V4HI (match_operand:V4QI 1 "register_operand" "a,b,a,b"))
|
||||
(zero_extend:V4HI (match_operand:V4QI 2 "register_operand" "a,b,?b,?a"))))]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tmpyu4\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "usmulv4qiv4hi3"
|
||||
[(set (match_operand:V4HI 0 "register_operand" "=a,b,a,b")
|
||||
(mult:V4HI
|
||||
(zero_extend:V4HI (match_operand:V4QI 1 "register_operand" "a,b,?b,?a"))
|
||||
(sign_extend:V4HI (match_operand:V4QI 2 "register_operand" "a,b,a,b"))))]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tmpyus4\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "dotv2hi"
|
||||
[(set (match_operand:SI 0 "register_operand" "=a,b,a,b")
|
||||
(plus:SI
|
||||
(mult:SI
|
||||
(sign_extend:SI
|
||||
(vec_select:HI
|
||||
(match_operand:V2HI 1 "register_operand" "a,b,a,b")
|
||||
(parallel [(const_int 0)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI
|
||||
(match_operand:V2HI 2 "register_operand" "a,b,?b,?a")
|
||||
(parallel [(const_int 0)]))))
|
||||
(mult:SI
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 1)]))))))]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tdotp2\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
;; Fractional multiply
|
||||
|
||||
(define_insn "mulv2hqv2sq3"
|
||||
[(set (match_operand:V2SQ 0 "register_operand" "=a,b,a,b")
|
||||
(ss_mult:V2SQ
|
||||
(fract_convert:V2SQ
|
||||
(match_operand:V2HQ 1 "register_operand" "%a,b,?a,?b"))
|
||||
(fract_convert:V2SQ
|
||||
(match_operand:V2HQ 2 "register_operand" "a,b,b,a"))))]
|
||||
""
|
||||
"%|%.\\tsmpy2\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhqsq3"
|
||||
[(set (match_operand:SQ 0 "register_operand" "=a,b,a,b")
|
||||
(ss_mult:SQ
|
||||
(fract_convert:SQ
|
||||
(match_operand:HQ 1 "register_operand" "%a,b,?a,?b"))
|
||||
(fract_convert:SQ
|
||||
(match_operand:HQ 2 "register_operand" "a,b,b,a"))))]
|
||||
""
|
||||
"%|%.\\tsmpy\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhqsq3_lh"
|
||||
[(set (match_operand:SQ 0 "register_operand" "=a,b,a,b")
|
||||
(ss_mult:SQ
|
||||
(fract_convert:SQ
|
||||
(match_operand:HQ 1 "register_operand" "a,b,?a,?b"))
|
||||
(fract_convert:SQ
|
||||
(truncate:HQ (match_operand:SQ 2 "register_operand" "a,b,b,a")))))]
|
||||
""
|
||||
"%|%.\\tsmpylh\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhqsq3_hl"
|
||||
[(set (match_operand:SQ 0 "register_operand" "=a,b,a,b")
|
||||
(ss_mult:SQ
|
||||
(fract_convert:SQ
|
||||
(truncate:HQ (match_operand:SQ 1 "register_operand" "a,b,b,a")))
|
||||
(fract_convert:SQ
|
||||
(match_operand:HQ 2 "register_operand" "a,b,b,a"))))]
|
||||
""
|
||||
"%|%.\\tsmpyhl\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhqsq3_hh"
|
||||
[(set (match_operand:SQ 0 "register_operand" "=a,b,a,b")
|
||||
(ss_mult:SQ
|
||||
(fract_convert:SQ
|
||||
(truncate:HQ (match_operand:SQ 1 "register_operand" "a,b,b,a")))
|
||||
(fract_convert:SQ
|
||||
(truncate:HQ (match_operand:SQ 2 "register_operand" "a,b,b,a")))))]
|
||||
""
|
||||
"%|%.\\tsmpyh\\t%$\\t%1, %2, %0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
;; Multiplication patterns for TI C6X.
|
||||
;; This file is processed by genmult.sh to produce two variants of each
|
||||
;; pattern, a normal one and a real_mult variant for modulo scheduling.
|
||||
;; Copyright (C) 2010, 2011 Free Software Foundation, Inc.
|
||||
;; Contributed by Bernd Schmidt <bernds@codesourcery.com>
|
||||
;; Contributed by CodeSourcery.
|
||||
;;
|
||||
;; This file is part of GCC.
|
||||
;;
|
||||
;; GCC is free software; you can redistribute it and/or modify
|
||||
;; it under the terms of the GNU General Public License as published by
|
||||
;; the Free Software Foundation; either version 3, or (at your option)
|
||||
;; any later version.
|
||||
;;
|
||||
;; GCC is distributed in the hope that it will be useful,
|
||||
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
;; GNU General Public License for more details.
|
||||
;;
|
||||
;; You should have received a copy of the GNU General Public License
|
||||
;; along with GCC; see the file COPYING3. If not see
|
||||
;; <http://www.gnu.org/licenses/>.
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; Miscellaneous insns that execute on the M units
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
(define_insn "rotlsi3_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(rotate:SI (match_operand:SI 1 "register_operand" "a,b,?b,?a")
|
||||
(match_operand:SI 2 "reg_or_ucst5_operand" "aIu5,bIu5,aIu5,bIu5"))] UNSPEC_REAL_MULT)]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\trotl\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "units" "m")
|
||||
(set_attr "type" "mpy2")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "bitrevsi2_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JA,JB,JB")
|
||||
(unspec:SI [(match_operand:SI 1 "register_operand" "a,?b,b,?a")]
|
||||
UNSPEC_BITREV)] UNSPEC_REAL_MULT)]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tbitr\\t%$\\t%1, %k0"
|
||||
[(set_attr "units" "m")
|
||||
(set_attr "type" "mpy2")
|
||||
(set_attr "cross" "n,y,n,y")])
|
||||
|
||||
;; Vector average.
|
||||
|
||||
(define_insn "avgv2hi3_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(unspec:V2HI [(match_operand:V2HI 1 "register_operand" "a,b,?b,?a")
|
||||
(match_operand:V2HI 2 "register_operand" "a,b,a,b")] UNSPEC_AVG)] UNSPEC_REAL_MULT)]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tavg2\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "units" "m")
|
||||
(set_attr "type" "mpy2")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "uavgv4qi3_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(unspec:V4QI [(match_operand:V4QI 1 "register_operand" "a,b,?b,?a")
|
||||
(match_operand:V4QI 2 "register_operand" "a,b,a,b")] UNSPEC_AVG)] UNSPEC_REAL_MULT)]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tavgu4\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "units" "m")
|
||||
(set_attr "type" "mpy2")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; Multiplication
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
(define_insn "mulhi3_real"
|
||||
[(unspec [(match_operand:HI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(mult:HI (match_operand:HI 1 "register_operand" "a,b,?b,?a")
|
||||
(match_operand:HI 2 "reg_or_scst5_operand" "aIs5,bIs5,aIs5,bIs5"))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tmpy\\t%$\\t%2, %1, %k0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhisi3_const_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JAJB")
|
||||
(mult:SI (sign_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "a,b,?ab"))
|
||||
(match_operand:HI 2 "scst5_operand" "Is5,Is5,Is5"))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tmpy\\t%$\\t%2, %1, %k0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y")])
|
||||
|
||||
(define_insn "*mulhisi3_insn_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(mult:SI (sign_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "%a,b,?a,?b"))
|
||||
(sign_extend:SI
|
||||
(match_operand:HI 2 "reg_or_scst5_operand" "a,b,b,a")))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tmpy\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhisi3_lh_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(mult:SI (sign_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "a,b,?a,?b"))
|
||||
(ashiftrt:SI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")
|
||||
(const_int 16)))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tmpylh\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhisi3_hl_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(mult:SI (ashiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "a,b,?a,?b")
|
||||
(const_int 16))
|
||||
(sign_extend:SI
|
||||
(match_operand:HI 2 "register_operand" "a,b,b,a")))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tmpyhl\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhisi3_hh_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(mult:SI (ashiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "%a,b,?a,?b")
|
||||
(const_int 16))
|
||||
(ashiftrt:SI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")
|
||||
(const_int 16)))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tmpyh\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "umulhisi3_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(mult:SI (zero_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "%a,b,?a,?b"))
|
||||
(zero_extend:SI
|
||||
(match_operand:HI 2 "register_operand" "a,b,b,a")))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tmpyu\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "umulhisi3_lh_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(mult:SI (zero_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "a,b,?a,?b"))
|
||||
(lshiftrt:SI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")
|
||||
(const_int 16)))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tmpylhu\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "umulhisi3_hl_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(mult:SI (lshiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "a,b,?a,?b")
|
||||
(const_int 16))
|
||||
(zero_extend:SI
|
||||
(match_operand:HI 2 "register_operand" "a,b,b,a")))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tmpyhlu\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "umulhisi3_hh_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(mult:SI (lshiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "%a,b,?a,?b")
|
||||
(const_int 16))
|
||||
(lshiftrt:SI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")
|
||||
(const_int 16)))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tmpyhu\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "usmulhisi3_const_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JAJB")
|
||||
(mult:SI (zero_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "a,b,?ab"))
|
||||
(match_operand:SI 2 "scst5_operand" "Is5,Is5,Is5"))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tmpysu\\t%$\\t%2, %1, %k0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y")])
|
||||
|
||||
(define_insn "*usmulhisi3_insn_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(mult:SI (zero_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "a,b,?a,?b"))
|
||||
(sign_extend:SI
|
||||
(match_operand:HI 2 "reg_or_scst5_operand" "aIs5,bIs5,bIs5,aIs5")))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tmpyus\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "usmulhisi3_lh_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(mult:SI (zero_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "a,b,?a,?b"))
|
||||
(ashiftrt:SI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")
|
||||
(const_int 16)))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tmpyluhs\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "usmulhisi3_hl_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(mult:SI (lshiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "a,b,?a,?b")
|
||||
(const_int 16))
|
||||
(sign_extend:SI
|
||||
(match_operand:HI 2 "register_operand" "a,b,b,a")))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tmpyhuls\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "usmulhisi3_hh_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(mult:SI (lshiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "a,b,?a,?b")
|
||||
(const_int 16))
|
||||
(ashiftrt:SI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")
|
||||
(const_int 16)))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tmpyhus\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulsi3_insn_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(mult:SI (match_operand:SI 1 "register_operand" "%a,b,?a,?b")
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a"))] UNSPEC_REAL_MULT)]
|
||||
"TARGET_MPY32"
|
||||
"%|%.\\tmpy32\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "<u>mulsidi3_real"
|
||||
[(unspec [(match_operand:DI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(mult:DI (any_ext:DI
|
||||
(match_operand:SI 1 "register_operand" "%a,b,?a,?b"))
|
||||
(any_ext:DI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")))] UNSPEC_REAL_MULT)]
|
||||
"TARGET_MPY32"
|
||||
"%|%.\\tmpy32<u>\\t%$\\t%1, %2, %K0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "usmulsidi3_real"
|
||||
[(unspec [(match_operand:DI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(mult:DI (zero_extend:DI
|
||||
(match_operand:SI 1 "register_operand" "a,b,?a,?b"))
|
||||
(sign_extend:DI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")))] UNSPEC_REAL_MULT)]
|
||||
"TARGET_MPY32"
|
||||
"%|%.\\tmpy32us\\t%$\\t%1, %2, %K0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
;; Widening vector multiply and dot product
|
||||
|
||||
(define_insn "mulv2hiv2si3_real"
|
||||
[(unspec [(match_operand:V2SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(mult:V2SI
|
||||
(sign_extend:V2SI (match_operand:V2HI 1 "register_operand" "a,b,a,b"))
|
||||
(sign_extend:V2SI (match_operand:V2HI 2 "register_operand" "a,b,?b,?a")))] UNSPEC_REAL_MULT)]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tmpy2\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "umulv4qiv4hi3_real"
|
||||
[(unspec [(match_operand:V4HI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(mult:V4HI
|
||||
(zero_extend:V4HI (match_operand:V4QI 1 "register_operand" "a,b,a,b"))
|
||||
(zero_extend:V4HI (match_operand:V4QI 2 "register_operand" "a,b,?b,?a")))] UNSPEC_REAL_MULT)]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tmpyu4\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "usmulv4qiv4hi3_real"
|
||||
[(unspec [(match_operand:V4HI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(mult:V4HI
|
||||
(zero_extend:V4HI (match_operand:V4QI 1 "register_operand" "a,b,?b,?a"))
|
||||
(sign_extend:V4HI (match_operand:V4QI 2 "register_operand" "a,b,a,b")))] UNSPEC_REAL_MULT)]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tmpyus4\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "dotv2hi_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(plus:SI
|
||||
(mult:SI
|
||||
(sign_extend:SI
|
||||
(vec_select:HI
|
||||
(match_operand:V2HI 1 "register_operand" "a,b,a,b")
|
||||
(parallel [(const_int 0)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI
|
||||
(match_operand:V2HI 2 "register_operand" "a,b,?b,?a")
|
||||
(parallel [(const_int 0)]))))
|
||||
(mult:SI
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))] UNSPEC_REAL_MULT)]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tdotp2\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
;; Fractional multiply
|
||||
|
||||
(define_insn "mulv2hqv2sq3_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(ss_mult:V2SQ
|
||||
(fract_convert:V2SQ
|
||||
(match_operand:V2HQ 1 "register_operand" "%a,b,?a,?b"))
|
||||
(fract_convert:V2SQ
|
||||
(match_operand:V2HQ 2 "register_operand" "a,b,b,a")))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tsmpy2\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhqsq3_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(ss_mult:SQ
|
||||
(fract_convert:SQ
|
||||
(match_operand:HQ 1 "register_operand" "%a,b,?a,?b"))
|
||||
(fract_convert:SQ
|
||||
(match_operand:HQ 2 "register_operand" "a,b,b,a")))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tsmpy\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhqsq3_lh_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(ss_mult:SQ
|
||||
(fract_convert:SQ
|
||||
(match_operand:HQ 1 "register_operand" "a,b,?a,?b"))
|
||||
(fract_convert:SQ
|
||||
(truncate:HQ (match_operand:SQ 2 "register_operand" "a,b,b,a"))))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tsmpylh\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhqsq3_hl_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(ss_mult:SQ
|
||||
(fract_convert:SQ
|
||||
(truncate:HQ (match_operand:SQ 1 "register_operand" "a,b,b,a")))
|
||||
(fract_convert:SQ
|
||||
(match_operand:HQ 2 "register_operand" "a,b,b,a")))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tsmpyhl\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhqsq3_hh_real"
|
||||
[(unspec [(match_operand:SI 0 "const_int_operand" "=JA,JB,JA,JB")
|
||||
(ss_mult:SQ
|
||||
(fract_convert:SQ
|
||||
(truncate:HQ (match_operand:SQ 1 "register_operand" "a,b,b,a")))
|
||||
(fract_convert:SQ
|
||||
(truncate:HQ (match_operand:SQ 2 "register_operand" "a,b,b,a"))))] UNSPEC_REAL_MULT)]
|
||||
""
|
||||
"%|%.\\tsmpyh\\t%$\\t%1, %2, %k0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
419
gcc/config/c6x/c6x-mult.md.in
Normal file
419
gcc/config/c6x/c6x-mult.md.in
Normal file
|
|
@ -0,0 +1,419 @@
|
|||
;; Multiplication patterns for TI C6X.
|
||||
;; This file is processed by genmult.sh to produce two variants of each
|
||||
;; pattern, a normal one and a real_mult variant for modulo scheduling.
|
||||
;; Copyright (C) 2010, 2011 Free Software Foundation, Inc.
|
||||
;; Contributed by Bernd Schmidt <bernds@codesourcery.com>
|
||||
;; Contributed by CodeSourcery.
|
||||
;;
|
||||
;; This file is part of GCC.
|
||||
;;
|
||||
;; GCC is free software; you can redistribute it and/or modify
|
||||
;; it under the terms of the GNU General Public License as published by
|
||||
;; the Free Software Foundation; either version 3, or (at your option)
|
||||
;; any later version.
|
||||
;;
|
||||
;; GCC is distributed in the hope that it will be useful,
|
||||
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
;; GNU General Public License for more details.
|
||||
;;
|
||||
;; You should have received a copy of the GNU General Public License
|
||||
;; along with GCC; see the file COPYING3. If not see
|
||||
;; <http://www.gnu.org/licenses/>.
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; Miscellaneous insns that execute on the M units
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
(define_insn "rotlsi3_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:SI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(rotate:SI (match_operand:SI 1 "register_operand" "a,b,?b,?a")
|
||||
(match_operand:SI 2 "reg_or_ucst5_operand" "aIu5,bIu5,aIu5,bIu5"))_CBRK_)]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\trotl\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "units" "m")
|
||||
(set_attr "type" "mpy2")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "bitrevsi2_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:SI 0 "_DESTOPERAND_" "=_A_,_A_,_B_,_B_")
|
||||
(unspec:SI [(match_operand:SI 1 "register_operand" "a,?b,b,?a")]
|
||||
UNSPEC_BITREV)_CBRK_)]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tbitr\\t%$\\t%1, %_MODk_0"
|
||||
[(set_attr "units" "m")
|
||||
(set_attr "type" "mpy2")
|
||||
(set_attr "cross" "n,y,n,y")])
|
||||
|
||||
;; Vector average.
|
||||
|
||||
(define_insn "avgv2hi3_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:_MV2HI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(unspec:V2HI [(match_operand:V2HI 1 "register_operand" "a,b,?b,?a")
|
||||
(match_operand:V2HI 2 "register_operand" "a,b,a,b")] UNSPEC_AVG)_CBRK_)]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tavg2\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "units" "m")
|
||||
(set_attr "type" "mpy2")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "uavgv4qi3_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:_MV4QI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(unspec:V4QI [(match_operand:V4QI 1 "register_operand" "a,b,?b,?a")
|
||||
(match_operand:V4QI 2 "register_operand" "a,b,a,b")] UNSPEC_AVG)_CBRK_)]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tavgu4\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "units" "m")
|
||||
(set_attr "type" "mpy2")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
;; -------------------------------------------------------------------------
|
||||
;; Multiplication
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
(define_insn "mulhi3_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:HI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(mult:HI (match_operand:HI 1 "register_operand" "a,b,?b,?a")
|
||||
(match_operand:HI 2 "reg_or_scst5_operand" "aIs5,bIs5,aIs5,bIs5"))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tmpy\\t%$\\t%2, %1, %_MODk_0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhisi3_const_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:SI 0 "_DESTOPERAND_" "=_A_,_B_,_A__B_")
|
||||
(mult:SI (sign_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "a,b,?ab"))
|
||||
(match_operand:HI 2 "scst5_operand" "Is5,Is5,Is5"))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tmpy\\t%$\\t%2, %1, %_MODk_0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y")])
|
||||
|
||||
(define_insn "*mulhisi3_insn_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:SI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(mult:SI (sign_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "%a,b,?a,?b"))
|
||||
(sign_extend:SI
|
||||
(match_operand:HI 2 "reg_or_scst5_operand" "a,b,b,a")))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tmpy\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhisi3_lh_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:SI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(mult:SI (sign_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "a,b,?a,?b"))
|
||||
(ashiftrt:SI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")
|
||||
(const_int 16)))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tmpylh\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhisi3_hl_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:SI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(mult:SI (ashiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "a,b,?a,?b")
|
||||
(const_int 16))
|
||||
(sign_extend:SI
|
||||
(match_operand:HI 2 "register_operand" "a,b,b,a")))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tmpyhl\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhisi3_hh_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:SI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(mult:SI (ashiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "%a,b,?a,?b")
|
||||
(const_int 16))
|
||||
(ashiftrt:SI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")
|
||||
(const_int 16)))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tmpyh\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "umulhisi3_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:SI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(mult:SI (zero_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "%a,b,?a,?b"))
|
||||
(zero_extend:SI
|
||||
(match_operand:HI 2 "register_operand" "a,b,b,a")))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tmpyu\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "umulhisi3_lh_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:SI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(mult:SI (zero_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "a,b,?a,?b"))
|
||||
(lshiftrt:SI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")
|
||||
(const_int 16)))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tmpylhu\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "umulhisi3_hl_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:SI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(mult:SI (lshiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "a,b,?a,?b")
|
||||
(const_int 16))
|
||||
(zero_extend:SI
|
||||
(match_operand:HI 2 "register_operand" "a,b,b,a")))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tmpyhlu\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "umulhisi3_hh_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:SI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(mult:SI (lshiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "%a,b,?a,?b")
|
||||
(const_int 16))
|
||||
(lshiftrt:SI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")
|
||||
(const_int 16)))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tmpyhu\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "usmulhisi3_const_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:SI 0 "_DESTOPERAND_" "=_A_,_B_,_A__B_")
|
||||
(mult:SI (zero_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "a,b,?ab"))
|
||||
(match_operand:SI 2 "scst5_operand" "Is5,Is5,Is5"))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tmpysu\\t%$\\t%2, %1, %_MODk_0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y")])
|
||||
|
||||
(define_insn "*usmulhisi3_insn_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:SI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(mult:SI (zero_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "a,b,?a,?b"))
|
||||
(sign_extend:SI
|
||||
(match_operand:HI 2 "reg_or_scst5_operand" "aIs5,bIs5,bIs5,aIs5")))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tmpyus\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "usmulhisi3_lh_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:SI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(mult:SI (zero_extend:SI
|
||||
(match_operand:HI 1 "register_operand" "a,b,?a,?b"))
|
||||
(ashiftrt:SI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")
|
||||
(const_int 16)))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tmpyluhs\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "usmulhisi3_hl_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:SI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(mult:SI (lshiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "a,b,?a,?b")
|
||||
(const_int 16))
|
||||
(sign_extend:SI
|
||||
(match_operand:HI 2 "register_operand" "a,b,b,a")))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tmpyhuls\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "usmulhisi3_hh_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:SI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(mult:SI (lshiftrt:SI
|
||||
(match_operand:SI 1 "register_operand" "a,b,?a,?b")
|
||||
(const_int 16))
|
||||
(ashiftrt:SI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")
|
||||
(const_int 16)))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tmpyhus\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulsi3_insn_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:SI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(mult:SI (match_operand:SI 1 "register_operand" "%a,b,?a,?b")
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a"))_CBRK_)]
|
||||
"TARGET_MPY32"
|
||||
"%|%.\\tmpy32\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "<u>mulsidi3_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:DI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(mult:DI (any_ext:DI
|
||||
(match_operand:SI 1 "register_operand" "%a,b,?a,?b"))
|
||||
(any_ext:DI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")))_CBRK_)]
|
||||
"TARGET_MPY32"
|
||||
"%|%.\\tmpy32<u>\\t%$\\t%1, %2, %_MODK_0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "usmulsidi3_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:DI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(mult:DI (zero_extend:DI
|
||||
(match_operand:SI 1 "register_operand" "a,b,?a,?b"))
|
||||
(sign_extend:DI
|
||||
(match_operand:SI 2 "register_operand" "a,b,b,a")))_CBRK_)]
|
||||
"TARGET_MPY32"
|
||||
"%|%.\\tmpy32us\\t%$\\t%1, %2, %_MODK_0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
;; Widening vector multiply and dot product
|
||||
|
||||
(define_insn "mulv2hiv2si3_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:V2SI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(mult:V2SI
|
||||
(sign_extend:V2SI (match_operand:V2HI 1 "register_operand" "a,b,a,b"))
|
||||
(sign_extend:V2SI (match_operand:V2HI 2 "register_operand" "a,b,?b,?a")))_CBRK_)]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tmpy2\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "umulv4qiv4hi3_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:V4HI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(mult:V4HI
|
||||
(zero_extend:V4HI (match_operand:V4QI 1 "register_operand" "a,b,a,b"))
|
||||
(zero_extend:V4HI (match_operand:V4QI 2 "register_operand" "a,b,?b,?a")))_CBRK_)]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tmpyu4\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "usmulv4qiv4hi3_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:V4HI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(mult:V4HI
|
||||
(zero_extend:V4HI (match_operand:V4QI 1 "register_operand" "a,b,?b,?a"))
|
||||
(sign_extend:V4HI (match_operand:V4QI 2 "register_operand" "a,b,a,b")))_CBRK_)]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tmpyus4\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "dotv2hi_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:SI 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(plus:SI
|
||||
(mult:SI
|
||||
(sign_extend:SI
|
||||
(vec_select:HI
|
||||
(match_operand:V2HI 1 "register_operand" "a,b,a,b")
|
||||
(parallel [(const_int 0)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI
|
||||
(match_operand:V2HI 2 "register_operand" "a,b,?b,?a")
|
||||
(parallel [(const_int 0)]))))
|
||||
(mult:SI
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
|
||||
(sign_extend:SI
|
||||
(vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))_CBRK_)]
|
||||
"TARGET_INSNS_64"
|
||||
"%|%.\\tdotp2\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
;; Fractional multiply
|
||||
|
||||
(define_insn "mulv2hqv2sq3_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:_MV2SQ 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(ss_mult:V2SQ
|
||||
(fract_convert:V2SQ
|
||||
(match_operand:V2HQ 1 "register_operand" "%a,b,?a,?b"))
|
||||
(fract_convert:V2SQ
|
||||
(match_operand:V2HQ 2 "register_operand" "a,b,b,a")))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tsmpy2\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy4")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhqsq3_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:_MSQ 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(ss_mult:SQ
|
||||
(fract_convert:SQ
|
||||
(match_operand:HQ 1 "register_operand" "%a,b,?a,?b"))
|
||||
(fract_convert:SQ
|
||||
(match_operand:HQ 2 "register_operand" "a,b,b,a")))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tsmpy\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhqsq3_lh_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:_MSQ 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(ss_mult:SQ
|
||||
(fract_convert:SQ
|
||||
(match_operand:HQ 1 "register_operand" "a,b,?a,?b"))
|
||||
(fract_convert:SQ
|
||||
(truncate:HQ (match_operand:SQ 2 "register_operand" "a,b,b,a"))))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tsmpylh\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhqsq3_hl_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:_MSQ 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(ss_mult:SQ
|
||||
(fract_convert:SQ
|
||||
(truncate:HQ (match_operand:SQ 1 "register_operand" "a,b,b,a")))
|
||||
(fract_convert:SQ
|
||||
(match_operand:HQ 2 "register_operand" "a,b,b,a")))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tsmpyhl\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
|
||||
(define_insn "mulhqsq3_hh_VARIANT_"
|
||||
[(_SET_ _OBRK_(match_operand:_MSQ 0 "_DESTOPERAND_" "=_A_,_B_,_A_,_B_")
|
||||
(ss_mult:SQ
|
||||
(fract_convert:SQ
|
||||
(truncate:HQ (match_operand:SQ 1 "register_operand" "a,b,b,a")))
|
||||
(fract_convert:SQ
|
||||
(truncate:HQ (match_operand:SQ 2 "register_operand" "a,b,b,a"))))_CBRK_)]
|
||||
""
|
||||
"%|%.\\tsmpyh\\t%$\\t%1, %2, %_MODk_0"
|
||||
[(set_attr "type" "mpy2")
|
||||
(set_attr "units" "m")
|
||||
(set_attr "cross" "n,n,y,y")])
|
||||
36
gcc/config/c6x/c6x-opts.h
Normal file
36
gcc/config/c6x/c6x-opts.h
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
/* Definitions for option handling for TI C6X.
|
||||
Copyright (C) 2011
|
||||
Free Software Foundation, Inc.
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 3, or (at your option)
|
||||
any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#ifndef C6X_OPTS_H
|
||||
#define C6X_OPTS_H
|
||||
|
||||
/* An enumeration of all supported target devices. */
|
||||
typedef enum c6x_cpu_type
|
||||
{
|
||||
#define C6X_ISA(NAME,ENUM_VALUE,FLAGS) \
|
||||
ENUM_VALUE,
|
||||
#include "c6x-isas.def"
|
||||
#undef C6X_ISA
|
||||
unk_isa
|
||||
} c6x_cpu_t;
|
||||
|
||||
enum c6x_sdata { C6X_SDATA_NONE, C6X_SDATA_DEFAULT, C6X_SDATA_ALL };
|
||||
|
||||
#endif
|
||||
66
gcc/config/c6x/c6x-protos.h
Normal file
66
gcc/config/c6x/c6x-protos.h
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
/* Prototypes for exported functions defined in c6x.c.
|
||||
Copyright (C) 2010, 2011
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by CodeSourcery.
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
|
||||
option) any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#ifndef GCC_C6X_PROTOS_H
|
||||
#define GCC_C6X_PROTOS_H
|
||||
|
||||
/* Functions defined in c6x.c. */
|
||||
|
||||
#ifdef RTX_CODE
|
||||
extern void c6x_init_cumulative_args (CUMULATIVE_ARGS *, const_tree, rtx, int);
|
||||
extern bool c6x_block_reg_pad_upward (enum machine_mode, const_tree, bool);
|
||||
|
||||
extern bool c6x_legitimate_address_p_1 (enum machine_mode, rtx, bool, bool);
|
||||
extern bool c6x_mem_operand (rtx, enum reg_class, bool);
|
||||
extern bool expand_move (rtx *, enum machine_mode);
|
||||
|
||||
extern bool c6x_long_call_p (rtx);
|
||||
extern void c6x_expand_call (rtx, rtx, bool);
|
||||
extern rtx c6x_expand_compare (rtx, enum machine_mode);
|
||||
extern bool c6x_force_op_for_comparison_p (enum rtx_code, rtx);
|
||||
extern bool c6x_expand_movmem (rtx, rtx, rtx, rtx, rtx, rtx);
|
||||
|
||||
extern rtx c6x_subword (rtx, bool);
|
||||
extern void split_di (rtx *, int, rtx *, rtx *);
|
||||
extern bool c6x_valid_mask_p (HOST_WIDE_INT);
|
||||
|
||||
extern char c6x_get_unit_specifier (rtx);
|
||||
|
||||
extern void c6x_final_prescan_insn(rtx insn, rtx *opvec, int noperands);
|
||||
|
||||
extern int c6x_nsaved_regs (void);
|
||||
extern HOST_WIDE_INT c6x_initial_elimination_offset (int, int);
|
||||
extern void c6x_expand_prologue (void);
|
||||
extern void c6x_expand_epilogue (bool);
|
||||
|
||||
extern rtx c6x_return_addr_rtx (int);
|
||||
|
||||
extern void c6x_set_return_address (rtx, rtx);
|
||||
#endif
|
||||
|
||||
extern void c6x_override_options (void);
|
||||
extern void c6x_optimization_options (int, int);
|
||||
|
||||
extern void c6x_output_file_unwind (FILE *);
|
||||
|
||||
extern void c6x_function_end (FILE *, const char *);
|
||||
|
||||
#endif /* GCC_C6X_PROTOS_H */
|
||||
934
gcc/config/c6x/c6x-sched.md
Normal file
934
gcc/config/c6x/c6x-sched.md
Normal file
|
|
@ -0,0 +1,934 @@
|
|||
;; -*- buffer-read-only: t -*-
|
||||
;; Generated automatically from c6x-sched.md.in by gensched.sh
|
||||
|
||||
;; Definitions for side 1, cross n
|
||||
|
||||
;; Scheduling description for TI C6X.
|
||||
;; Copyright (C) 2010, 2011 Free Software Foundation, Inc.
|
||||
;; Contributed by Bernd Schmidt <bernds@codesourcery.com>
|
||||
;; Contributed by CodeSourcery.
|
||||
;;
|
||||
;; This file is part of GCC.
|
||||
;;
|
||||
;; GCC is free software; you can redistribute it and/or modify
|
||||
;; it under the terms of the GNU General Public License as published by
|
||||
;; the Free Software Foundation; either version 3, or (at your option)
|
||||
;; any later version.
|
||||
;;
|
||||
;; GCC is distributed in the hope that it will be useful,
|
||||
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
;; GNU General Public License for more details.
|
||||
;;
|
||||
;; You should have received a copy of the GNU General Public License
|
||||
;; along with GCC; see the file COPYING3. If not see
|
||||
;; <http://www.gnu.org/licenses/>.
|
||||
|
||||
;; Input file for gensched.sh We process this file multiple times,
|
||||
;; replacing 1 with either 1 or 2 for each of the sides of the
|
||||
;; machine, and a correspondingly with "a" or "b". n and
|
||||
;; are replaced with yes/no and the appropriate reservation.
|
||||
|
||||
(define_insn_reservation "load_d1n" 5
|
||||
(and (eq_attr "type" "load")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "a"))))
|
||||
"d1+t1")
|
||||
|
||||
(define_insn_reservation "store_d1n" 1
|
||||
(and (eq_attr "type" "store")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "a"))))
|
||||
"d1+t1")
|
||||
|
||||
(define_insn_reservation "loadn_d1n" 5
|
||||
(and (eq_attr "type" "loadn")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "a"))))
|
||||
"d1+t1+t2")
|
||||
|
||||
(define_insn_reservation "storen_d1n" 1
|
||||
(and (eq_attr "type" "storen")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "a"))))
|
||||
"d1+t1+t2")
|
||||
|
||||
(define_insn_reservation "single_d1n" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "d")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"d1")
|
||||
|
||||
(define_insn_reservation "single_l1n" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"l1+l1w")
|
||||
|
||||
(define_insn_reservation "fp4_l1n" 4
|
||||
(and (eq_attr "type" "fp4")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"l1,nothing*2,l1w")
|
||||
|
||||
(define_insn_reservation "intdp_l1n" 5
|
||||
(and (eq_attr "type" "intdp")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"l1,nothing*2,l1w*2")
|
||||
|
||||
(define_insn_reservation "adddp_l1n" 7
|
||||
(and (eq_attr "type" "adddp")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(l1)*2,nothing*3,l1w*2")
|
||||
|
||||
(define_insn_reservation "branch_s1n" 6
|
||||
(and (eq_attr "type" "branch")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(s1+s1w)+br1")
|
||||
|
||||
(define_insn_reservation "call_addkpc_s1n" 6
|
||||
(and (eq_attr "type" "call")
|
||||
(and (ne (symbol_ref "TARGET_INSNS_64") (const_int 0))
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "a")))))
|
||||
"(s1+s1w)+br1,s2+br0+br1")
|
||||
|
||||
(define_insn_reservation "call_mvk_s1n" 6
|
||||
(and (eq_attr "type" "call")
|
||||
(and (eq (symbol_ref "TARGET_INSNS_64") (const_int 0))
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "a")))))
|
||||
"(s1+s1w)+br1,s2,s2")
|
||||
|
||||
(define_insn_reservation "single_s1n" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(s1+s1w)")
|
||||
|
||||
(define_insn_reservation "cmpdp_s1n" 2
|
||||
(and (eq_attr "type" "cmpdp")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"s1,(s1)+s1w")
|
||||
|
||||
(define_insn_reservation "dp2_s1n" 2
|
||||
(and (eq_attr "type" "dp2")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"s1+s1w,s1w")
|
||||
|
||||
(define_insn_reservation "fp4_s1n" 4
|
||||
(and (eq_attr "type" "fp4")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"s1,nothing*2,s1w")
|
||||
|
||||
(define_insn_reservation "mvilc4_s1n" 4
|
||||
(and (eq_attr "type" "mvilc")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(s1+s1w)")
|
||||
|
||||
(define_insn_reservation "single_dl1n" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "dl")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(d1|(l1+l1w))")
|
||||
|
||||
(define_insn_reservation "single_ds1n" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "ds")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(d1|(s1+s1w))")
|
||||
|
||||
(define_insn_reservation "single_ls1n" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "ls")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"((l1+l1w)|(s1+s1w))")
|
||||
|
||||
(define_insn_reservation "dp2_l1n" 2
|
||||
(and (eq_attr "type" "dp2")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"l1+l1w,l1w")
|
||||
|
||||
(define_insn_reservation "fp4_ls1n" 4
|
||||
(and (eq_attr "type" "fp4")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "ls")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(s1,nothing*2,s1w)|(l1,nothing*2,l1w)")
|
||||
|
||||
(define_insn_reservation "adddp_ls1n" 7
|
||||
(and (eq_attr "type" "adddp")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "ls")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"((s1)*2,nothing*3,s1w*2)|((l1)*2,nothing*3,l1w*2)")
|
||||
|
||||
(define_insn_reservation "single_dls1n" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "dls")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(d1|(l1+l1w)|(s1+s1w))")
|
||||
|
||||
(define_insn_reservation "mpy2_m1n" 2
|
||||
(and (eq_attr "type" "mpy2")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"m1,m1w")
|
||||
|
||||
(define_insn_reservation "mpy4_m1n" 4
|
||||
(and (eq_attr "type" "mpy4")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"m1,nothing,nothing,m1w")
|
||||
|
||||
(define_insn_reservation "mpydp_m1n" 10
|
||||
(and (eq_attr "type" "mpydp")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(m1)*4,nothing*4,m1w*2")
|
||||
|
||||
(define_insn_reservation "mpyspdp_m1n" 7
|
||||
(and (eq_attr "type" "mpyspdp")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(m1)*2,nothing*3,m1w*2")
|
||||
|
||||
(define_insn_reservation "mpysp2dp_m1n" 5
|
||||
(and (eq_attr "type" "mpysp2dp")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"m1,nothing*2,m1w*2")
|
||||
|
||||
;; Definitions for side 2, cross n
|
||||
|
||||
;; Scheduling description for TI C6X.
|
||||
;; Copyright (C) 2010, 2011 Free Software Foundation, Inc.
|
||||
;; Contributed by Bernd Schmidt <bernds@codesourcery.com>
|
||||
;; Contributed by CodeSourcery.
|
||||
;;
|
||||
;; This file is part of GCC.
|
||||
;;
|
||||
;; GCC is free software; you can redistribute it and/or modify
|
||||
;; it under the terms of the GNU General Public License as published by
|
||||
;; the Free Software Foundation; either version 3, or (at your option)
|
||||
;; any later version.
|
||||
;;
|
||||
;; GCC is distributed in the hope that it will be useful,
|
||||
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
;; GNU General Public License for more details.
|
||||
;;
|
||||
;; You should have received a copy of the GNU General Public License
|
||||
;; along with GCC; see the file COPYING3. If not see
|
||||
;; <http://www.gnu.org/licenses/>.
|
||||
|
||||
;; Input file for gensched.sh We process this file multiple times,
|
||||
;; replacing 2 with either 1 or 2 for each of the sides of the
|
||||
;; machine, and b correspondingly with "a" or "b". n and
|
||||
;; are replaced with yes/no and the appropriate reservation.
|
||||
|
||||
(define_insn_reservation "load_d2n" 5
|
||||
(and (eq_attr "type" "load")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "b"))))
|
||||
"d2+t2")
|
||||
|
||||
(define_insn_reservation "store_d2n" 1
|
||||
(and (eq_attr "type" "store")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "b"))))
|
||||
"d2+t2")
|
||||
|
||||
(define_insn_reservation "loadn_d2n" 5
|
||||
(and (eq_attr "type" "loadn")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "b"))))
|
||||
"d2+t1+t2")
|
||||
|
||||
(define_insn_reservation "storen_d2n" 1
|
||||
(and (eq_attr "type" "storen")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "b"))))
|
||||
"d2+t1+t2")
|
||||
|
||||
(define_insn_reservation "single_d2n" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "d")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"d2")
|
||||
|
||||
(define_insn_reservation "single_l2n" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"l2+l2w")
|
||||
|
||||
(define_insn_reservation "fp4_l2n" 4
|
||||
(and (eq_attr "type" "fp4")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"l2,nothing*2,l2w")
|
||||
|
||||
(define_insn_reservation "intdp_l2n" 5
|
||||
(and (eq_attr "type" "intdp")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"l2,nothing*2,l2w*2")
|
||||
|
||||
(define_insn_reservation "adddp_l2n" 7
|
||||
(and (eq_attr "type" "adddp")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(l2)*2,nothing*3,l2w*2")
|
||||
|
||||
(define_insn_reservation "branch_s2n" 6
|
||||
(and (eq_attr "type" "branch")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(s2+s2w)+br1")
|
||||
|
||||
(define_insn_reservation "call_addkpc_s2n" 6
|
||||
(and (eq_attr "type" "call")
|
||||
(and (ne (symbol_ref "TARGET_INSNS_64") (const_int 0))
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "b")))))
|
||||
"(s2+s2w)+br1,s2+br0+br1")
|
||||
|
||||
(define_insn_reservation "call_mvk_s2n" 6
|
||||
(and (eq_attr "type" "call")
|
||||
(and (eq (symbol_ref "TARGET_INSNS_64") (const_int 0))
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "b")))))
|
||||
"(s2+s2w)+br1,s2,s2")
|
||||
|
||||
(define_insn_reservation "single_s2n" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(s2+s2w)")
|
||||
|
||||
(define_insn_reservation "cmpdp_s2n" 2
|
||||
(and (eq_attr "type" "cmpdp")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"s2,(s2)+s2w")
|
||||
|
||||
(define_insn_reservation "dp2_s2n" 2
|
||||
(and (eq_attr "type" "dp2")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"s2+s2w,s2w")
|
||||
|
||||
(define_insn_reservation "fp4_s2n" 4
|
||||
(and (eq_attr "type" "fp4")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"s2,nothing*2,s2w")
|
||||
|
||||
(define_insn_reservation "mvilc4_s2n" 4
|
||||
(and (eq_attr "type" "mvilc")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(s2+s2w)")
|
||||
|
||||
(define_insn_reservation "single_dl2n" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "dl")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(d2|(l2+l2w))")
|
||||
|
||||
(define_insn_reservation "single_ds2n" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "ds")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(d2|(s2+s2w))")
|
||||
|
||||
(define_insn_reservation "single_ls2n" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "ls")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"((l2+l2w)|(s2+s2w))")
|
||||
|
||||
(define_insn_reservation "dp2_l2n" 2
|
||||
(and (eq_attr "type" "dp2")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"l2+l2w,l2w")
|
||||
|
||||
(define_insn_reservation "fp4_ls2n" 4
|
||||
(and (eq_attr "type" "fp4")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "ls")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(s2,nothing*2,s2w)|(l2,nothing*2,l2w)")
|
||||
|
||||
(define_insn_reservation "adddp_ls2n" 7
|
||||
(and (eq_attr "type" "adddp")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "ls")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"((s2)*2,nothing*3,s2w*2)|((l2)*2,nothing*3,l2w*2)")
|
||||
|
||||
(define_insn_reservation "single_dls2n" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "dls")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(d2|(l2+l2w)|(s2+s2w))")
|
||||
|
||||
(define_insn_reservation "mpy2_m2n" 2
|
||||
(and (eq_attr "type" "mpy2")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"m2,m2w")
|
||||
|
||||
(define_insn_reservation "mpy4_m2n" 4
|
||||
(and (eq_attr "type" "mpy4")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"m2,nothing,nothing,m2w")
|
||||
|
||||
(define_insn_reservation "mpydp_m2n" 10
|
||||
(and (eq_attr "type" "mpydp")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(m2)*4,nothing*4,m2w*2")
|
||||
|
||||
(define_insn_reservation "mpyspdp_m2n" 7
|
||||
(and (eq_attr "type" "mpyspdp")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(m2)*2,nothing*3,m2w*2")
|
||||
|
||||
(define_insn_reservation "mpysp2dp_m2n" 5
|
||||
(and (eq_attr "type" "mpysp2dp")
|
||||
(and (eq_attr "cross" "n")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"m2,nothing*2,m2w*2")
|
||||
|
||||
;; Definitions for side 1, cross y
|
||||
|
||||
;; Scheduling description for TI C6X.
|
||||
;; Copyright (C) 2010, 2011 Free Software Foundation, Inc.
|
||||
;; Contributed by Bernd Schmidt <bernds@codesourcery.com>
|
||||
;; Contributed by CodeSourcery.
|
||||
;;
|
||||
;; This file is part of GCC.
|
||||
;;
|
||||
;; GCC is free software; you can redistribute it and/or modify
|
||||
;; it under the terms of the GNU General Public License as published by
|
||||
;; the Free Software Foundation; either version 3, or (at your option)
|
||||
;; any later version.
|
||||
;;
|
||||
;; GCC is distributed in the hope that it will be useful,
|
||||
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
;; GNU General Public License for more details.
|
||||
;;
|
||||
;; You should have received a copy of the GNU General Public License
|
||||
;; along with GCC; see the file COPYING3. If not see
|
||||
;; <http://www.gnu.org/licenses/>.
|
||||
|
||||
;; Input file for gensched.sh We process this file multiple times,
|
||||
;; replacing 1 with either 1 or 2 for each of the sides of the
|
||||
;; machine, and a correspondingly with "a" or "b". y and
|
||||
;; +x1 are replaced with yes/no and the appropriate reservation.
|
||||
|
||||
(define_insn_reservation "load_d1y" 5
|
||||
(and (eq_attr "type" "load")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "a"))))
|
||||
"d1+t2")
|
||||
|
||||
(define_insn_reservation "store_d1y" 1
|
||||
(and (eq_attr "type" "store")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "a"))))
|
||||
"d1+t2")
|
||||
|
||||
(define_insn_reservation "loadn_d1y" 5
|
||||
(and (eq_attr "type" "loadn")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "a"))))
|
||||
"d1+t1+t2")
|
||||
|
||||
(define_insn_reservation "storen_d1y" 1
|
||||
(and (eq_attr "type" "storen")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "a"))))
|
||||
"d1+t1+t2")
|
||||
|
||||
(define_insn_reservation "single_d1y" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "d")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"d1+x1")
|
||||
|
||||
(define_insn_reservation "single_l1y" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"l1+l1w+x1")
|
||||
|
||||
(define_insn_reservation "fp4_l1y" 4
|
||||
(and (eq_attr "type" "fp4")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"l1+x1,nothing*2,l1w")
|
||||
|
||||
(define_insn_reservation "intdp_l1y" 5
|
||||
(and (eq_attr "type" "intdp")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"l1+x1,nothing*2,l1w*2")
|
||||
|
||||
(define_insn_reservation "adddp_l1y" 7
|
||||
(and (eq_attr "type" "adddp")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(l1+x1)*2,nothing*3,l1w*2")
|
||||
|
||||
(define_insn_reservation "branch_s1y" 6
|
||||
(and (eq_attr "type" "branch")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(s1+s1w)+x1+br1")
|
||||
|
||||
(define_insn_reservation "call_addkpc_s1y" 6
|
||||
(and (eq_attr "type" "call")
|
||||
(and (ne (symbol_ref "TARGET_INSNS_64") (const_int 0))
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "a")))))
|
||||
"(s1+s1w)+x1+br1,s2+br0+br1")
|
||||
|
||||
(define_insn_reservation "call_mvk_s1y" 6
|
||||
(and (eq_attr "type" "call")
|
||||
(and (eq (symbol_ref "TARGET_INSNS_64") (const_int 0))
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "a")))))
|
||||
"(s1+s1w)+x1+br1,s2,s2")
|
||||
|
||||
(define_insn_reservation "single_s1y" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(s1+s1w)+x1")
|
||||
|
||||
(define_insn_reservation "cmpdp_s1y" 2
|
||||
(and (eq_attr "type" "cmpdp")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"s1+x1,(s1+x1)+s1w")
|
||||
|
||||
(define_insn_reservation "dp2_s1y" 2
|
||||
(and (eq_attr "type" "dp2")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"s1+s1w+x1,s1w")
|
||||
|
||||
(define_insn_reservation "fp4_s1y" 4
|
||||
(and (eq_attr "type" "fp4")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"s1+x1,nothing*2,s1w")
|
||||
|
||||
(define_insn_reservation "mvilc4_s1y" 4
|
||||
(and (eq_attr "type" "mvilc")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(s1+s1w)+x1")
|
||||
|
||||
(define_insn_reservation "single_dl1y" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "dl")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(d1|(l1+l1w))+x1")
|
||||
|
||||
(define_insn_reservation "single_ds1y" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "ds")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(d1|(s1+s1w))+x1")
|
||||
|
||||
(define_insn_reservation "single_ls1y" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "ls")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"((l1+l1w)|(s1+s1w))+x1")
|
||||
|
||||
(define_insn_reservation "dp2_l1y" 2
|
||||
(and (eq_attr "type" "dp2")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"l1+l1w+x1,l1w")
|
||||
|
||||
(define_insn_reservation "fp4_ls1y" 4
|
||||
(and (eq_attr "type" "fp4")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "ls")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(s1+x1,nothing*2,s1w)|(l1+x1,nothing*2,l1w)")
|
||||
|
||||
(define_insn_reservation "adddp_ls1y" 7
|
||||
(and (eq_attr "type" "adddp")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "ls")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"((s1+x1)*2,nothing*3,s1w*2)|((l1+x1)*2,nothing*3,l1w*2)")
|
||||
|
||||
(define_insn_reservation "single_dls1y" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "dls")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(d1|(l1+l1w)|(s1+s1w))+x1")
|
||||
|
||||
(define_insn_reservation "mpy2_m1y" 2
|
||||
(and (eq_attr "type" "mpy2")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"m1+x1,m1w")
|
||||
|
||||
(define_insn_reservation "mpy4_m1y" 4
|
||||
(and (eq_attr "type" "mpy4")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"m1+x1,nothing,nothing,m1w")
|
||||
|
||||
(define_insn_reservation "mpydp_m1y" 10
|
||||
(and (eq_attr "type" "mpydp")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(m1+x1)*4,nothing*4,m1w*2")
|
||||
|
||||
(define_insn_reservation "mpyspdp_m1y" 7
|
||||
(and (eq_attr "type" "mpyspdp")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"(m1+x1)*2,nothing*3,m1w*2")
|
||||
|
||||
(define_insn_reservation "mpysp2dp_m1y" 5
|
||||
(and (eq_attr "type" "mpysp2dp")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "a"))))
|
||||
"m1+x1,nothing*2,m1w*2")
|
||||
|
||||
;; Definitions for side 2, cross y
|
||||
|
||||
;; Scheduling description for TI C6X.
|
||||
;; Copyright (C) 2010, 2011 Free Software Foundation, Inc.
|
||||
;; Contributed by Bernd Schmidt <bernds@codesourcery.com>
|
||||
;; Contributed by CodeSourcery.
|
||||
;;
|
||||
;; This file is part of GCC.
|
||||
;;
|
||||
;; GCC is free software; you can redistribute it and/or modify
|
||||
;; it under the terms of the GNU General Public License as published by
|
||||
;; the Free Software Foundation; either version 3, or (at your option)
|
||||
;; any later version.
|
||||
;;
|
||||
;; GCC is distributed in the hope that it will be useful,
|
||||
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
;; GNU General Public License for more details.
|
||||
;;
|
||||
;; You should have received a copy of the GNU General Public License
|
||||
;; along with GCC; see the file COPYING3. If not see
|
||||
;; <http://www.gnu.org/licenses/>.
|
||||
|
||||
;; Input file for gensched.sh We process this file multiple times,
|
||||
;; replacing 2 with either 1 or 2 for each of the sides of the
|
||||
;; machine, and b correspondingly with "a" or "b". y and
|
||||
;; +x2 are replaced with yes/no and the appropriate reservation.
|
||||
|
||||
(define_insn_reservation "load_d2y" 5
|
||||
(and (eq_attr "type" "load")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "b"))))
|
||||
"d2+t1")
|
||||
|
||||
(define_insn_reservation "store_d2y" 1
|
||||
(and (eq_attr "type" "store")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "b"))))
|
||||
"d2+t1")
|
||||
|
||||
(define_insn_reservation "loadn_d2y" 5
|
||||
(and (eq_attr "type" "loadn")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "b"))))
|
||||
"d2+t1+t2")
|
||||
|
||||
(define_insn_reservation "storen_d2y" 1
|
||||
(and (eq_attr "type" "storen")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "b"))))
|
||||
"d2+t1+t2")
|
||||
|
||||
(define_insn_reservation "single_d2y" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "d")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"d2+x2")
|
||||
|
||||
(define_insn_reservation "single_l2y" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"l2+l2w+x2")
|
||||
|
||||
(define_insn_reservation "fp4_l2y" 4
|
||||
(and (eq_attr "type" "fp4")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"l2+x2,nothing*2,l2w")
|
||||
|
||||
(define_insn_reservation "intdp_l2y" 5
|
||||
(and (eq_attr "type" "intdp")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"l2+x2,nothing*2,l2w*2")
|
||||
|
||||
(define_insn_reservation "adddp_l2y" 7
|
||||
(and (eq_attr "type" "adddp")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(l2+x2)*2,nothing*3,l2w*2")
|
||||
|
||||
(define_insn_reservation "branch_s2y" 6
|
||||
(and (eq_attr "type" "branch")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(s2+s2w)+x2+br1")
|
||||
|
||||
(define_insn_reservation "call_addkpc_s2y" 6
|
||||
(and (eq_attr "type" "call")
|
||||
(and (ne (symbol_ref "TARGET_INSNS_64") (const_int 0))
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "b")))))
|
||||
"(s2+s2w)+x2+br1,s2+br0+br1")
|
||||
|
||||
(define_insn_reservation "call_mvk_s2y" 6
|
||||
(and (eq_attr "type" "call")
|
||||
(and (eq (symbol_ref "TARGET_INSNS_64") (const_int 0))
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "b")))))
|
||||
"(s2+s2w)+x2+br1,s2,s2")
|
||||
|
||||
(define_insn_reservation "single_s2y" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(s2+s2w)+x2")
|
||||
|
||||
(define_insn_reservation "cmpdp_s2y" 2
|
||||
(and (eq_attr "type" "cmpdp")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"s2+x2,(s2+x2)+s2w")
|
||||
|
||||
(define_insn_reservation "dp2_s2y" 2
|
||||
(and (eq_attr "type" "dp2")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"s2+s2w+x2,s2w")
|
||||
|
||||
(define_insn_reservation "fp4_s2y" 4
|
||||
(and (eq_attr "type" "fp4")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"s2+x2,nothing*2,s2w")
|
||||
|
||||
(define_insn_reservation "mvilc4_s2y" 4
|
||||
(and (eq_attr "type" "mvilc")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(s2+s2w)+x2")
|
||||
|
||||
(define_insn_reservation "single_dl2y" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "dl")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(d2|(l2+l2w))+x2")
|
||||
|
||||
(define_insn_reservation "single_ds2y" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "ds")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(d2|(s2+s2w))+x2")
|
||||
|
||||
(define_insn_reservation "single_ls2y" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "ls")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"((l2+l2w)|(s2+s2w))+x2")
|
||||
|
||||
(define_insn_reservation "dp2_l2y" 2
|
||||
(and (eq_attr "type" "dp2")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"l2+l2w+x2,l2w")
|
||||
|
||||
(define_insn_reservation "fp4_ls2y" 4
|
||||
(and (eq_attr "type" "fp4")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "ls")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(s2+x2,nothing*2,s2w)|(l2+x2,nothing*2,l2w)")
|
||||
|
||||
(define_insn_reservation "adddp_ls2y" 7
|
||||
(and (eq_attr "type" "adddp")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "ls")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"((s2+x2)*2,nothing*3,s2w*2)|((l2+x2)*2,nothing*3,l2w*2)")
|
||||
|
||||
(define_insn_reservation "single_dls2y" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "dls")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(d2|(l2+l2w)|(s2+s2w))+x2")
|
||||
|
||||
(define_insn_reservation "mpy2_m2y" 2
|
||||
(and (eq_attr "type" "mpy2")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"m2+x2,m2w")
|
||||
|
||||
(define_insn_reservation "mpy4_m2y" 4
|
||||
(and (eq_attr "type" "mpy4")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"m2+x2,nothing,nothing,m2w")
|
||||
|
||||
(define_insn_reservation "mpydp_m2y" 10
|
||||
(and (eq_attr "type" "mpydp")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(m2+x2)*4,nothing*4,m2w*2")
|
||||
|
||||
(define_insn_reservation "mpyspdp_m2y" 7
|
||||
(and (eq_attr "type" "mpyspdp")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"(m2+x2)*2,nothing*3,m2w*2")
|
||||
|
||||
(define_insn_reservation "mpysp2dp_m2y" 5
|
||||
(and (eq_attr "type" "mpysp2dp")
|
||||
(and (eq_attr "cross" "y")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "b"))))
|
||||
"m2+x2,nothing*2,m2w*2")
|
||||
230
gcc/config/c6x/c6x-sched.md.in
Normal file
230
gcc/config/c6x/c6x-sched.md.in
Normal file
|
|
@ -0,0 +1,230 @@
|
|||
;; Scheduling description for TI C6X.
|
||||
;; Copyright (C) 2010, 2011 Free Software Foundation, Inc.
|
||||
;; Contributed by Bernd Schmidt <bernds@codesourcery.com>
|
||||
;; Contributed by CodeSourcery.
|
||||
;;
|
||||
;; This file is part of GCC.
|
||||
;;
|
||||
;; GCC is free software; you can redistribute it and/or modify
|
||||
;; it under the terms of the GNU General Public License as published by
|
||||
;; the Free Software Foundation; either version 3, or (at your option)
|
||||
;; any later version.
|
||||
;;
|
||||
;; GCC is distributed in the hope that it will be useful,
|
||||
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
;; GNU General Public License for more details.
|
||||
;;
|
||||
;; You should have received a copy of the GNU General Public License
|
||||
;; along with GCC; see the file COPYING3. If not see
|
||||
;; <http://www.gnu.org/licenses/>.
|
||||
|
||||
;; Input file for gensched.sh We process this file multiple times,
|
||||
;; replacing _N_ with either 1 or 2 for each of the sides of the
|
||||
;; machine, and _RF_ correspondingly with "a" or "b". _CROSS_ and
|
||||
;; _CUNIT_ are replaced with yes/no and the appropriate reservation.
|
||||
|
||||
(define_insn_reservation "load_d_N__CROSS_" 5
|
||||
(and (eq_attr "type" "load")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "_RF_"))))
|
||||
"d_N_+t_NX_")
|
||||
|
||||
(define_insn_reservation "store_d_N__CROSS_" 1
|
||||
(and (eq_attr "type" "store")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "_RF_"))))
|
||||
"d_N_+t_NX_")
|
||||
|
||||
(define_insn_reservation "loadn_d_N__CROSS_" 5
|
||||
(and (eq_attr "type" "loadn")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "_RF_"))))
|
||||
"d_N_+t1+t2")
|
||||
|
||||
(define_insn_reservation "storen_d_N__CROSS_" 1
|
||||
(and (eq_attr "type" "storen")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "d_addr")
|
||||
(eq_attr "addr_regfile" "_RF_"))))
|
||||
"d_N_+t1+t2")
|
||||
|
||||
(define_insn_reservation "single_d_N__CROSS_" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "d")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"d_N__CUNIT_")
|
||||
|
||||
(define_insn_reservation "single_l_N__CROSS_" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"l_N_+l_N_w_CUNIT_")
|
||||
|
||||
(define_insn_reservation "fp4_l_N__CROSS_" 4
|
||||
(and (eq_attr "type" "fp4")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"l_N__CUNIT_,nothing*2,l_N_w")
|
||||
|
||||
(define_insn_reservation "intdp_l_N__CROSS_" 5
|
||||
(and (eq_attr "type" "intdp")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"l_N__CUNIT_,nothing*2,l_N_w*2")
|
||||
|
||||
(define_insn_reservation "adddp_l_N__CROSS_" 7
|
||||
(and (eq_attr "type" "adddp")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"(l_N__CUNIT_)*2,nothing*3,l_N_w*2")
|
||||
|
||||
(define_insn_reservation "branch_s_N__CROSS_" 6
|
||||
(and (eq_attr "type" "branch")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"(s_N_+s_N_w)_CUNIT_+br1")
|
||||
|
||||
(define_insn_reservation "call_addkpc_s_N__CROSS_" 6
|
||||
(and (eq_attr "type" "call")
|
||||
(and (ne (symbol_ref "TARGET_INSNS_64") (const_int 0))
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "_RF_")))))
|
||||
"(s_N_+s_N_w)_CUNIT_+br1,s2+br0+br1")
|
||||
|
||||
(define_insn_reservation "call_mvk_s_N__CROSS_" 6
|
||||
(and (eq_attr "type" "call")
|
||||
(and (eq (symbol_ref "TARGET_INSNS_64") (const_int 0))
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "_RF_")))))
|
||||
"(s_N_+s_N_w)_CUNIT_+br1,s2,s2")
|
||||
|
||||
(define_insn_reservation "single_s_N__CROSS_" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"(s_N_+s_N_w)_CUNIT_")
|
||||
|
||||
(define_insn_reservation "cmpdp_s_N__CROSS_" 2
|
||||
(and (eq_attr "type" "cmpdp")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"s_N__CUNIT_,(s_N__CUNIT_)+s_N_w")
|
||||
|
||||
(define_insn_reservation "dp2_s_N__CROSS_" 2
|
||||
(and (eq_attr "type" "dp2")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"s_N_+s_N_w_CUNIT_,s_N_w")
|
||||
|
||||
(define_insn_reservation "fp4_s_N__CROSS_" 4
|
||||
(and (eq_attr "type" "fp4")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"s_N__CUNIT_,nothing*2,s_N_w")
|
||||
|
||||
(define_insn_reservation "mvilc4_s_N__CROSS_" 4
|
||||
(and (eq_attr "type" "mvilc")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "s")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"(s_N_+s_N_w)_CUNIT_")
|
||||
|
||||
(define_insn_reservation "single_dl_N__CROSS_" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "dl")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"(d_N_|(l_N_+l_N_w))_CUNIT_")
|
||||
|
||||
(define_insn_reservation "single_ds_N__CROSS_" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "ds")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"(d_N_|(s_N_+s_N_w))_CUNIT_")
|
||||
|
||||
(define_insn_reservation "single_ls_N__CROSS_" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "ls")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"((l_N_+l_N_w)|(s_N_+s_N_w))_CUNIT_")
|
||||
|
||||
(define_insn_reservation "dp2_l_N__CROSS_" 2
|
||||
(and (eq_attr "type" "dp2")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "l")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"l_N_+l_N_w_CUNIT_,l_N_w")
|
||||
|
||||
(define_insn_reservation "fp4_ls_N__CROSS_" 4
|
||||
(and (eq_attr "type" "fp4")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "ls")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"(s_N__CUNIT_,nothing*2,s_N_w)|(l_N__CUNIT_,nothing*2,l_N_w)")
|
||||
|
||||
(define_insn_reservation "adddp_ls_N__CROSS_" 7
|
||||
(and (eq_attr "type" "adddp")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "ls")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"((s_N__CUNIT_)*2,nothing*3,s_N_w*2)|((l_N__CUNIT_)*2,nothing*3,l_N_w*2)")
|
||||
|
||||
(define_insn_reservation "single_dls_N__CROSS_" 1
|
||||
(and (eq_attr "type" "single")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "dls")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"(d_N_|(l_N_+l_N_w)|(s_N_+s_N_w))_CUNIT_")
|
||||
|
||||
(define_insn_reservation "mpy2_m_N__CROSS_" 2
|
||||
(and (eq_attr "type" "mpy2")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"m_N__CUNIT_,m_N_w")
|
||||
|
||||
(define_insn_reservation "mpy4_m_N__CROSS_" 4
|
||||
(and (eq_attr "type" "mpy4")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"m_N__CUNIT_,nothing,nothing,m_N_w")
|
||||
|
||||
(define_insn_reservation "mpydp_m_N__CROSS_" 10
|
||||
(and (eq_attr "type" "mpydp")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"(m_N__CUNIT_)*4,nothing*4,m_N_w*2")
|
||||
|
||||
(define_insn_reservation "mpyspdp_m_N__CROSS_" 7
|
||||
(and (eq_attr "type" "mpyspdp")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"(m_N__CUNIT_)*2,nothing*3,m_N_w*2")
|
||||
|
||||
(define_insn_reservation "mpysp2dp_m_N__CROSS_" 5
|
||||
(and (eq_attr "type" "mpysp2dp")
|
||||
(and (eq_attr "cross" "_CROSS_")
|
||||
(and (eq_attr "units" "m")
|
||||
(eq_attr "dest_regfile" "_RF_"))))
|
||||
"m_N__CUNIT_,nothing*2,m_N_w*2")
|
||||
43
gcc/config/c6x/c6x-tables.opt
Normal file
43
gcc/config/c6x/c6x-tables.opt
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
; -*- buffer-read-only: t -*-
|
||||
; Generated automatically by genopt.sh from c6x-isas.def.
|
||||
;
|
||||
; Copyright (C) 2011 Free Software Foundation, Inc.
|
||||
;
|
||||
; This file is part of GCC.
|
||||
;
|
||||
; GCC is free software; you can redistribute it and/or modify it under
|
||||
; the terms of the GNU General Public License as published by the Free
|
||||
; Software Foundation; either version 3, or (at your option) any later
|
||||
; version.
|
||||
;
|
||||
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
; for more details.
|
||||
;
|
||||
; You should have received a copy of the GNU General Public License
|
||||
; along with GCC; see the file COPYING3. If not see
|
||||
; <http://www.gnu.org/licenses/>.
|
||||
|
||||
Enum
|
||||
Name(c6x_isa) Type(int)
|
||||
Known C6X ISAs (for use with the -march= option):
|
||||
|
||||
EnumValue
|
||||
Enum(c6x_isa) String(c62x) Value(0)
|
||||
|
||||
EnumValue
|
||||
Enum(c6x_isa) String(c64x) Value(1)
|
||||
|
||||
EnumValue
|
||||
Enum(c6x_isa) String(c64x+) Value(2)
|
||||
|
||||
EnumValue
|
||||
Enum(c6x_isa) String(c67x) Value(3)
|
||||
|
||||
EnumValue
|
||||
Enum(c6x_isa) String(c67x+) Value(4)
|
||||
|
||||
EnumValue
|
||||
Enum(c6x_isa) String(c674x) Value(5)
|
||||
|
||||
5572
gcc/config/c6x/c6x.c
Normal file
5572
gcc/config/c6x/c6x.c
Normal file
File diff suppressed because it is too large
Load diff
617
gcc/config/c6x/c6x.h
Normal file
617
gcc/config/c6x/c6x.h
Normal file
|
|
@ -0,0 +1,617 @@
|
|||
/* Target Definitions for TI C6X.
|
||||
Copyright (C) 2010, 2011 Free Software Foundation, Inc.
|
||||
Contributed by Andrew Jenner <andrew@codesourcery.com>
|
||||
Contributed by Bernd Schmidt <bernds@codesourcery.com>
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
|
||||
option) any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#ifndef GCC_C6X_H
|
||||
#define GCC_C6X_H
|
||||
|
||||
/* Feature bit definitions that enable specific insns. */
|
||||
#define C6X_INSNS_C62X 1
|
||||
#define C6X_INSNS_C64X 2
|
||||
#define C6X_INSNS_C64XP 4
|
||||
#define C6X_INSNS_C67X 8
|
||||
#define C6X_INSNS_C67XP 16
|
||||
#define C6X_INSNS_C674X 32
|
||||
#define C6X_INSNS_ATOMIC 64
|
||||
#define C6X_INSNS_ALL_CPU_BITS 127
|
||||
|
||||
#define C6X_DEFAULT_INSN_MASK \
|
||||
(C6X_INSNS_C62X | C6X_INSNS_C64X | C6X_INSNS_C64XP)
|
||||
|
||||
/* A mask of allowed insn types, as defined above. */
|
||||
extern unsigned long c6x_insn_mask;
|
||||
|
||||
/* Value of -march= */
|
||||
extern c6x_cpu_t c6x_arch;
|
||||
#define C6X_DEFAULT_ARCH C6X_CPU_C64XP
|
||||
|
||||
/* True if the target has C64x instructions. */
|
||||
#define TARGET_INSNS_64 ((c6x_insn_mask & C6X_INSNS_C64X) != 0)
|
||||
/* True if the target has C64x+ instructions. */
|
||||
#define TARGET_INSNS_64PLUS ((c6x_insn_mask & C6X_INSNS_C64XP) != 0)
|
||||
/* True if the target has C67x instructions. */
|
||||
#define TARGET_INSNS_67 ((c6x_insn_mask & C6X_INSNS_C67X) != 0)
|
||||
/* True if the target has C67x+ instructions. */
|
||||
#define TARGET_INSNS_67PLUS ((c6x_insn_mask & C6X_INSNS_C67XP) != 0)
|
||||
|
||||
/* True if the target supports doubleword loads. */
|
||||
#define TARGET_LDDW (TARGET_INSNS_64 || TARGET_INSNS_67)
|
||||
/* True if the target supports doubleword loads. */
|
||||
#define TARGET_STDW TARGET_INSNS_64
|
||||
/* True if the target supports the MPY32 family of instructions. */
|
||||
#define TARGET_MPY32 TARGET_INSNS_64PLUS
|
||||
/* True if the target has floating point hardware. */
|
||||
#define TARGET_FP TARGET_INSNS_67
|
||||
/* True if the target has C67x+ floating point extensions. */
|
||||
#define TARGET_FP_EXT TARGET_INSNS_67PLUS
|
||||
|
||||
#define TARGET_DEFAULT 0
|
||||
|
||||
/* Run-time Target. */
|
||||
|
||||
#define TARGET_CPU_CPP_BUILTINS() \
|
||||
do \
|
||||
{ \
|
||||
builtin_assert ("machine=tic6x"); \
|
||||
builtin_assert ("cpu=tic6x"); \
|
||||
builtin_define ("__TMS320C6X__"); \
|
||||
builtin_define ("_TMS320C6X"); \
|
||||
\
|
||||
if (TARGET_DSBT) \
|
||||
builtin_define ("__DSBT__"); \
|
||||
\
|
||||
if (TARGET_BIG_ENDIAN) \
|
||||
builtin_define ("_BIG_ENDIAN"); \
|
||||
else \
|
||||
builtin_define ("_LITTLE_ENDIAN"); \
|
||||
\
|
||||
switch (c6x_arch) \
|
||||
{ \
|
||||
case C6X_CPU_C62X: \
|
||||
builtin_define ("_TMS320C6200"); \
|
||||
break; \
|
||||
\
|
||||
case C6X_CPU_C64XP: \
|
||||
builtin_define ("_TMS320C6400_PLUS"); \
|
||||
/* ... fall through ... */ \
|
||||
case C6X_CPU_C64X: \
|
||||
builtin_define ("_TMS320C6400"); \
|
||||
break; \
|
||||
\
|
||||
case C6X_CPU_C67XP: \
|
||||
builtin_define ("_TMS320C6700_PLUS"); \
|
||||
/* ... fall through ... */ \
|
||||
case C6X_CPU_C67X: \
|
||||
builtin_define ("_TMS320C6700"); \
|
||||
break; \
|
||||
\
|
||||
case C6X_CPU_C674X: \
|
||||
builtin_define ("_TMS320C6740"); \
|
||||
builtin_define ("_TMS320C6700_PLUS"); \
|
||||
builtin_define ("_TMS320C6700"); \
|
||||
builtin_define ("_TMS320C6400_PLUS"); \
|
||||
builtin_define ("_TMS320C6400"); \
|
||||
break; \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
#define OPTION_DEFAULT_SPECS \
|
||||
{"arch", "%{!march=*:-march=%(VALUE)}" }
|
||||
|
||||
/* Storage Layout. */
|
||||
|
||||
#define BITS_BIG_ENDIAN 0
|
||||
#define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
|
||||
#define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0)
|
||||
|
||||
#define REG_WORDS_BIG_ENDIAN 0
|
||||
|
||||
#define UNITS_PER_WORD 4
|
||||
#define PARM_BOUNDARY 8
|
||||
#define STACK_BOUNDARY 64
|
||||
#define FUNCTION_BOUNDARY 32
|
||||
#define BIGGEST_ALIGNMENT 64
|
||||
#define STRICT_ALIGNMENT 1
|
||||
|
||||
/* The ABI requires static arrays must be at least 8 byte aligned.
|
||||
Really only externally visible arrays must be aligned this way, as
|
||||
only those are directly visible from another compilation unit. But
|
||||
we don't have that information available here. */
|
||||
#define DATA_ALIGNMENT(TYPE, ALIGN) \
|
||||
(((ALIGN) < BITS_PER_UNIT * 8 && TREE_CODE (TYPE) == ARRAY_TYPE) \
|
||||
? BITS_PER_UNIT * 8 : (ALIGN))
|
||||
|
||||
/* Type Layout. */
|
||||
|
||||
#define DEFAULT_SIGNED_CHAR 1
|
||||
|
||||
#undef SIZE_TYPE
|
||||
#define SIZE_TYPE "unsigned int"
|
||||
#undef PTRDIFF_TYPE
|
||||
#define PTRDIFF_TYPE "int"
|
||||
|
||||
/* Registers. */
|
||||
|
||||
#define FIRST_PSEUDO_REGISTER 67
|
||||
#define FIXED_REGISTERS \
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, \
|
||||
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 1}
|
||||
#define CALL_USED_REGISTERS \
|
||||
{ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, \
|
||||
1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
|
||||
1, 1, 1}
|
||||
|
||||
/* This lists call-used non-predicate registers first, followed by call-used
|
||||
registers, followed by predicate registers. We want to avoid allocating
|
||||
the predicate registers for other uses as much as possible. */
|
||||
#define REG_ALLOC_ORDER \
|
||||
{ \
|
||||
REG_A0, REG_A3, REG_A4, REG_A5, REG_A6, REG_A7, REG_A8, REG_A9, \
|
||||
REG_A16, REG_A17, REG_A18, REG_A19, REG_A20, REG_A21, REG_A22, REG_A23, \
|
||||
REG_A24, REG_A25, REG_A26, REG_A27, REG_A28, REG_A29, REG_A30, REG_A31, \
|
||||
REG_B4, REG_B5, REG_B6, REG_B7, REG_B8, REG_B9, REG_B16, \
|
||||
REG_B17, REG_B18, REG_B19, REG_B20, REG_B21, REG_B22, REG_B23, REG_B24, \
|
||||
REG_B25, REG_B26, REG_B27, REG_B28, REG_B29, REG_B30, REG_B31, \
|
||||
REG_A10, REG_A11, REG_A12, REG_A13, REG_A14, REG_A15, \
|
||||
REG_B3, REG_B10, REG_B11, REG_B12, REG_B13, REG_B14, REG_B15, \
|
||||
REG_A1, REG_A2, REG_B0, REG_B1, REG_B2, REG_ILC \
|
||||
}
|
||||
|
||||
#define HARD_REGNO_NREGS(regno, mode) \
|
||||
((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) \
|
||||
/ UNITS_PER_WORD)
|
||||
|
||||
#define HARD_REGNO_MODE_OK(reg, mode) (GET_MODE_SIZE (mode) <= UNITS_PER_WORD \
|
||||
? 1 : ((reg) & 1) == 0)
|
||||
|
||||
#define MODES_TIEABLE_P(mode1, mode2) \
|
||||
((mode1) == (mode2) || \
|
||||
(GET_MODE_SIZE (mode1) <= UNITS_PER_WORD && \
|
||||
GET_MODE_SIZE (mode2) <= UNITS_PER_WORD))
|
||||
|
||||
|
||||
/* Register Classes. */
|
||||
|
||||
enum reg_class
|
||||
{
|
||||
NO_REGS,
|
||||
PREDICATE_A_REGS,
|
||||
PREDICATE_B_REGS,
|
||||
PREDICATE_REGS,
|
||||
PICREG,
|
||||
SPREG,
|
||||
CALL_USED_B_REGS,
|
||||
NONPREDICATE_A_REGS,
|
||||
NONPREDICATE_B_REGS,
|
||||
NONPREDICATE_REGS,
|
||||
A_REGS,
|
||||
B_REGS,
|
||||
GENERAL_REGS,
|
||||
ALL_REGS,
|
||||
LIM_REG_CLASSES
|
||||
};
|
||||
|
||||
#define N_REG_CLASSES (int) LIM_REG_CLASSES
|
||||
|
||||
#define REG_CLASS_NAMES { \
|
||||
"NO_REGS", \
|
||||
"PREDICATE_A_REGS", \
|
||||
"PREDICATE_B_REGS", \
|
||||
"PREDICATE_REGS", \
|
||||
"PICREG", \
|
||||
"SPREG", \
|
||||
"CALL_USED_B_REGS", \
|
||||
"NONPREDICATE_A_REGS", \
|
||||
"NONPREDICATE_B_REGS", \
|
||||
"NONPREDICATE_REGS", \
|
||||
"A_REGS", \
|
||||
"B_REGS", \
|
||||
"GENERAL_REGS", \
|
||||
"ALL_REGS" }
|
||||
|
||||
#define REG_CLASS_CONTENTS \
|
||||
{ \
|
||||
/* NO_REGS. */ \
|
||||
{ 0x00000000, 0x00000000, 0 }, \
|
||||
/* PREDICATE_A_REGS. */ \
|
||||
{ 0x00000006, 0x00000000, 0 }, \
|
||||
/* PREDICATE_B_REGS. */ \
|
||||
{ 0x00000000, 0x00000007, 0 }, \
|
||||
/* PREDICATE_REGS. */ \
|
||||
{ 0x00000006, 0x00000007, 0 }, \
|
||||
/* PICREG. */ \
|
||||
{ 0x00000000, 0x00004000, 0 }, \
|
||||
/* SPREG. */ \
|
||||
{ 0x00000000, 0x00008000, 0 }, \
|
||||
/* CALL_USED_B_REGS. */ \
|
||||
{ 0x00000000, 0xFFFF03FF, 0 }, \
|
||||
/* NONPREDICATE_A_REGS. */ \
|
||||
{ 0xFFFFFFF9, 0x00000000, 0 }, \
|
||||
/* NONPREDICATE_B_REGS. */ \
|
||||
{ 0x00000000, 0xFFFFFFF8, 0 }, \
|
||||
/* NONPREDICATE_REGS. */ \
|
||||
{ 0xFFFFFFF9, 0xFFFFFFF8, 0 }, \
|
||||
/* A_REGS. */ \
|
||||
{ 0xFFFFFFFF, 0x00000000, 3 }, \
|
||||
/* B_REGS. */ \
|
||||
{ 0x00000000, 0xFFFFFFFF, 3 }, \
|
||||
/* GENERAL_REGS. */ \
|
||||
{ 0xFFFFFFFF, 0xFFFFFFFF, 3 }, \
|
||||
/* ALL_REGS. */ \
|
||||
{ 0xFFFFFFFF, 0xFFFFFFFF, 7 }, \
|
||||
}
|
||||
|
||||
#define A_REGNO_P(N) ((N) <= REG_A31)
|
||||
#define B_REGNO_P(N) ((N) >= REG_B0 && (N) <= REG_B31)
|
||||
|
||||
#define A_REG_P(X) (REG_P (X) && A_REGNO_P (REGNO (X)))
|
||||
#define CROSS_OPERANDS(X0,X1) \
|
||||
(A_REG_P (X0) == A_REG_P (X1) ? CROSS_N : CROSS_Y)
|
||||
|
||||
#define REGNO_REG_CLASS(reg) \
|
||||
((reg) >= REG_A1 && (reg) <= REG_A2 ? PREDICATE_A_REGS \
|
||||
: (reg) == REG_A0 && TARGET_INSNS_64 ? PREDICATE_A_REGS \
|
||||
: (reg) >= REG_B0 && (reg) <= REG_B2 ? PREDICATE_B_REGS \
|
||||
: A_REGNO_P (reg) ? NONPREDICATE_A_REGS \
|
||||
: call_used_regs[reg] ? CALL_USED_B_REGS : B_REGS)
|
||||
|
||||
#define BASE_REG_CLASS ALL_REGS
|
||||
#define INDEX_REG_CLASS ALL_REGS
|
||||
|
||||
#define REGNO_OK_FOR_BASE_STRICT_P(X) \
|
||||
((X) < FIRST_PSEUDO_REGISTER \
|
||||
|| (reg_renumber[X] >= 0 && reg_renumber[X] < FIRST_PSEUDO_REGISTER))
|
||||
#define REGNO_OK_FOR_BASE_NONSTRICT_P(X) 1
|
||||
|
||||
#define REGNO_OK_FOR_INDEX_STRICT_P(X) \
|
||||
((X) < FIRST_PSEUDO_REGISTER \
|
||||
|| (reg_renumber[X] >= 0 && reg_renumber[X] < FIRST_PSEUDO_REGISTER))
|
||||
#define REGNO_OK_FOR_INDEX_NONSTRICT_P(X) 1
|
||||
|
||||
#ifdef REG_OK_STRICT
|
||||
#define REGNO_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_STRICT_P (X)
|
||||
#define REGNO_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_STRICT_P (X)
|
||||
#else
|
||||
#define REGNO_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_NONSTRICT_P (X)
|
||||
#define REGNO_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_NONSTRICT_P (X)
|
||||
#endif
|
||||
|
||||
#define CLASS_MAX_NREGS(class, mode) \
|
||||
((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
|
||||
|
||||
#define REGNO_OK_FOR_INDIRECT_JUMP_P(REGNO, MODE) B_REGNO_P (REGNO)
|
||||
|
||||
/* Stack and Calling. */
|
||||
|
||||
/* SP points to 4 bytes below the first word of the frame. */
|
||||
#define STACK_POINTER_OFFSET 4
|
||||
/* Likewise for AP (which is the incoming stack pointer). */
|
||||
#define FIRST_PARM_OFFSET(fundecl) 4
|
||||
#define STARTING_FRAME_OFFSET 0
|
||||
#define FRAME_GROWS_DOWNWARD 1
|
||||
#define STACK_GROWS_DOWNWARD
|
||||
|
||||
#define STACK_POINTER_REGNUM REG_B15
|
||||
#define HARD_FRAME_POINTER_REGNUM REG_A15
|
||||
/* These two always get eliminated in favour of the stack pointer
|
||||
or the hard frame pointer. */
|
||||
#define FRAME_POINTER_REGNUM REG_FRAME
|
||||
#define ARG_POINTER_REGNUM REG_ARGP
|
||||
|
||||
#define PIC_OFFSET_TABLE_REGNUM REG_B14
|
||||
|
||||
/* We keep the stack pointer constant rather than using push/pop
|
||||
instructions. */
|
||||
#define ACCUMULATE_OUTGOING_ARGS 1
|
||||
|
||||
/* Before the prologue, the return address is in the B3 register. */
|
||||
#define RETURN_ADDR_REGNO REG_B3
|
||||
#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNO)
|
||||
|
||||
#define RETURN_ADDR_RTX(COUNT, FRAME) c6x_return_addr_rtx (COUNT)
|
||||
|
||||
#define INCOMING_FRAME_SP_OFFSET 0
|
||||
#define ARG_POINTER_CFA_OFFSET(fundecl) 0
|
||||
|
||||
#define STATIC_CHAIN_REGNUM REG_A2
|
||||
|
||||
struct c6x_args {
|
||||
/* Number of arguments to pass in registers. */
|
||||
int nregs;
|
||||
/* Number of arguments passed in registers so far. */
|
||||
int count;
|
||||
};
|
||||
|
||||
#define CUMULATIVE_ARGS struct c6x_args
|
||||
|
||||
#define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \
|
||||
c6x_init_cumulative_args (&cum, fntype, libname, n_named_args)
|
||||
|
||||
#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
|
||||
(c6x_block_reg_pad_upward (MODE, TYPE, FIRST) ? upward : downward)
|
||||
|
||||
#define FUNCTION_ARG_REGNO_P(r) \
|
||||
(((r) >= REG_A4 && (r) <= REG_A13) || ((r) >= REG_B4 && (r) <= REG_B13))
|
||||
|
||||
#define DEFAULT_PCC_STRUCT_RETURN 0
|
||||
|
||||
#define FUNCTION_PROFILER(file, labelno) \
|
||||
fatal_error ("profiling is not yet implemented for this architecture")
|
||||
|
||||
|
||||
/* Trampolines. */
|
||||
#define TRAMPOLINE_SIZE 32
|
||||
#define TRAMPOLINE_ALIGNMENT 256
|
||||
|
||||
#define ELIMINABLE_REGS \
|
||||
{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
||||
{ ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \
|
||||
{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
|
||||
{ FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \
|
||||
|
||||
/* Define the offset between two registers, one to be eliminated, and the other
|
||||
its replacement, at the start of a routine. */
|
||||
|
||||
#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
|
||||
((OFFSET) = c6x_initial_elimination_offset ((FROM), (TO)))
|
||||
|
||||
/* Addressing Modes. */
|
||||
|
||||
#define CONSTANT_ADDRESS_P(x) (CONSTANT_P(x) && GET_CODE(x) != CONST_DOUBLE)
|
||||
#define MAX_REGS_PER_ADDRESS 2
|
||||
|
||||
#define HAVE_PRE_DECREMENT 1
|
||||
#define HAVE_POST_DECREMENT 1
|
||||
#define HAVE_PRE_INCREMENT 1
|
||||
#define HAVE_POST_INCREMENT 1
|
||||
|
||||
/* Register forms are available, but due to scaling we currently don't
|
||||
support them. */
|
||||
#define HAVE_PRE_MODIFY_DISP 1
|
||||
#define HAVE_POST_MODIFY_DISP 1
|
||||
|
||||
#define LEGITIMATE_PIC_OPERAND_P(X) \
|
||||
(!symbolic_operand (X, SImode))
|
||||
|
||||
struct GTY(()) machine_function
|
||||
{
|
||||
/* True if we expanded a sibling call. */
|
||||
int contains_sibcall;
|
||||
};
|
||||
|
||||
/* Costs. */
|
||||
#define NO_FUNCTION_CSE 1
|
||||
|
||||
#define SLOW_BYTE_ACCESS 0
|
||||
|
||||
#define BRANCH_COST(speed_p, predictable_p) 6
|
||||
|
||||
|
||||
/* Model costs for the vectorizer. */
|
||||
|
||||
/* Cost of conditional branch. */
|
||||
#ifndef TARG_COND_BRANCH_COST
|
||||
#define TARG_COND_BRANCH_COST 6
|
||||
#endif
|
||||
|
||||
/* Cost of any scalar operation, excluding load and store. */
|
||||
#ifndef TARG_SCALAR_STMT_COST
|
||||
#define TARG_SCALAR_STMT_COST 1
|
||||
#endif
|
||||
|
||||
/* Cost of scalar load. */
|
||||
#undef TARG_SCALAR_LOAD_COST
|
||||
#define TARG_SCALAR_LOAD_COST 2 /* load + rotate */
|
||||
|
||||
/* Cost of scalar store. */
|
||||
#undef TARG_SCALAR_STORE_COST
|
||||
#define TARG_SCALAR_STORE_COST 10
|
||||
|
||||
/* Cost of any vector operation, excluding load, store,
|
||||
or vector to scalar operation. */
|
||||
#undef TARG_VEC_STMT_COST
|
||||
#define TARG_VEC_STMT_COST 1
|
||||
|
||||
/* Cost of vector to scalar operation. */
|
||||
#undef TARG_VEC_TO_SCALAR_COST
|
||||
#define TARG_VEC_TO_SCALAR_COST 1
|
||||
|
||||
/* Cost of scalar to vector operation. */
|
||||
#undef TARG_SCALAR_TO_VEC_COST
|
||||
#define TARG_SCALAR_TO_VEC_COST 1
|
||||
|
||||
/* Cost of aligned vector load. */
|
||||
#undef TARG_VEC_LOAD_COST
|
||||
#define TARG_VEC_LOAD_COST 1
|
||||
|
||||
/* Cost of misaligned vector load. */
|
||||
#undef TARG_VEC_UNALIGNED_LOAD_COST
|
||||
#define TARG_VEC_UNALIGNED_LOAD_COST 2
|
||||
|
||||
/* Cost of vector store. */
|
||||
#undef TARG_VEC_STORE_COST
|
||||
#define TARG_VEC_STORE_COST 1
|
||||
|
||||
/* Cost of vector permutation. */
|
||||
#ifndef TARG_VEC_PERMUTE_COST
|
||||
#define TARG_VEC_PERMUTE_COST 1
|
||||
#endif
|
||||
|
||||
/* Exception handling. */
|
||||
#define TARGET_EXTRA_CFI_SECTION(unwind) ((unwind) ? ".c6xabi.exidx" : NULL)
|
||||
/* ttype entries (the only interesting data references used) are
|
||||
sb-relative got-indirect (aka .ehtype). */
|
||||
#define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \
|
||||
(((code) == 0 && (data) == 1) ? (DW_EH_PE_datarel | DW_EH_PE_indirect) \
|
||||
: DW_EH_PE_absptr)
|
||||
|
||||
/* This should be the same as the definition in elfos.h, plus the call
|
||||
to output special unwinding directives. */
|
||||
#undef ASM_DECLARE_FUNCTION_NAME
|
||||
#define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
|
||||
do \
|
||||
{ \
|
||||
c6x_output_file_unwind (FILE); \
|
||||
ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "function"); \
|
||||
ASM_DECLARE_RESULT (FILE, DECL_RESULT (DECL)); \
|
||||
ASM_OUTPUT_LABEL (FILE, NAME); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
/* This should be the same as the definition in elfos.h, plus the call
|
||||
to output special unwinding directives. */
|
||||
#undef ASM_DECLARE_FUNCTION_SIZE
|
||||
#define ASM_DECLARE_FUNCTION_SIZE(STREAM, NAME, DECL) \
|
||||
c6x_function_end (STREAM, NAME)
|
||||
|
||||
/* Arbitrarily choose A4/A5. */
|
||||
#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N) + 4 : INVALID_REGNUM)
|
||||
|
||||
/* The register that holds the return address in exception handlers. */
|
||||
#define C6X_EH_STACKADJ_REGNUM 3
|
||||
#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, C6X_EH_STACKADJ_REGNUM)
|
||||
|
||||
|
||||
/* Assembler Format. */
|
||||
|
||||
#define DWARF2_ASM_LINE_DEBUG_INFO 1
|
||||
|
||||
#undef ASM_APP_ON
|
||||
#define ASM_APP_ON "\t; #APP \n"
|
||||
#undef ASM_APP_OFF
|
||||
#define ASM_APP_OFF "\t; #NO_APP \n"
|
||||
|
||||
#define ASM_OUTPUT_COMMON(stream, name, size, rounded)
|
||||
#define ASM_OUTPUT_LOCAL(stream, name, size, rounded)
|
||||
|
||||
#define GLOBAL_ASM_OP "\t.global\t"
|
||||
|
||||
#define REGISTER_NAMES \
|
||||
{ \
|
||||
"A0", "A1", "A2", "A3", "A4", "A5", "A6", "A7", \
|
||||
"A8", "A9", "A10", "A11", "A12", "A13", "A14", "A15", \
|
||||
"A16", "A17", "A18", "A19", "A20", "A21", "A22", "A23", \
|
||||
"A24", "A25", "A26", "A27", "A28", "A29", "A30", "A31", \
|
||||
"B0", "B1", "B2", "B3", "B4", "B5", "B6", "B7", \
|
||||
"B8", "B9", "B10", "B11", "B12", "B13", "B14", "B15", \
|
||||
"B16", "B17", "B18", "B19", "B20", "B21", "B22", "B23", \
|
||||
"B24", "B25", "B26", "B27", "B28", "B29", "B30", "B31", \
|
||||
"FP", "ARGP", "ILC" }
|
||||
|
||||
#define DBX_REGISTER_NUMBER(N) (dbx_register_map[(N)])
|
||||
|
||||
extern int const dbx_register_map[FIRST_PSEUDO_REGISTER];
|
||||
|
||||
#define FINAL_PRESCAN_INSN c6x_final_prescan_insn
|
||||
|
||||
#define TEXT_SECTION_ASM_OP ".text;"
|
||||
#define DATA_SECTION_ASM_OP ".data;"
|
||||
|
||||
#define ASM_OUTPUT_ALIGN(stream, power) \
|
||||
do \
|
||||
{ \
|
||||
if (power) \
|
||||
fprintf ((stream), "\t.align\t%d\n", power); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
#define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
|
||||
do { char __buf[256]; \
|
||||
fprintf (FILE, "\t.long\t"); \
|
||||
ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \
|
||||
assemble_name (FILE, __buf); \
|
||||
fputc ('\n', FILE); \
|
||||
} while (0)
|
||||
|
||||
/* Determine whether to place EXP (an expression or a decl) should be
|
||||
placed into one of the small data sections. */
|
||||
#define PLACE_IN_SDATA_P(EXP) \
|
||||
(c6x_sdata_mode == C6X_SDATA_NONE ? false \
|
||||
: c6x_sdata_mode == C6X_SDATA_ALL ? true \
|
||||
: !AGGREGATE_TYPE_P (TREE_TYPE (EXP)))
|
||||
|
||||
#define SCOMMON_ASM_OP "\t.scomm\t"
|
||||
|
||||
#undef ASM_OUTPUT_ALIGNED_DECL_COMMON
|
||||
#define ASM_OUTPUT_ALIGNED_DECL_COMMON(FILE, DECL, NAME, SIZE, ALIGN) \
|
||||
do \
|
||||
{ \
|
||||
if (DECL != NULL && PLACE_IN_SDATA_P (DECL)) \
|
||||
fprintf ((FILE), "%s", SCOMMON_ASM_OP); \
|
||||
else \
|
||||
fprintf ((FILE), "%s", COMMON_ASM_OP); \
|
||||
assemble_name ((FILE), (NAME)); \
|
||||
fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\
|
||||
} \
|
||||
while (0)
|
||||
|
||||
/* This says how to output assembler code to declare an
|
||||
uninitialized internal linkage data object. */
|
||||
|
||||
#undef ASM_OUTPUT_ALIGNED_DECL_LOCAL
|
||||
#define ASM_OUTPUT_ALIGNED_DECL_LOCAL(FILE, DECL, NAME, SIZE, ALIGN) \
|
||||
do { \
|
||||
if (PLACE_IN_SDATA_P (DECL)) \
|
||||
switch_to_section (sbss_section); \
|
||||
else \
|
||||
switch_to_section (bss_section); \
|
||||
ASM_OUTPUT_TYPE_DIRECTIVE (FILE, NAME, "object"); \
|
||||
if (!flag_inhibit_size_directive) \
|
||||
ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \
|
||||
ASM_OUTPUT_ALIGN ((FILE), exact_log2((ALIGN) / BITS_PER_UNIT)); \
|
||||
ASM_OUTPUT_LABEL(FILE, NAME); \
|
||||
ASM_OUTPUT_SKIP((FILE), (SIZE) ? (SIZE) : 1); \
|
||||
} while (0)
|
||||
|
||||
#define CASE_VECTOR_PC_RELATIVE flag_pic
|
||||
#define JUMP_TABLES_IN_TEXT_SECTION flag_pic
|
||||
|
||||
#define ADDR_VEC_ALIGN(VEC) (JUMP_TABLES_IN_TEXT_SECTION ? 5 : 2)
|
||||
|
||||
/* This is how to output an element of a case-vector that is relative. */
|
||||
#define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
|
||||
do { char buf[100]; \
|
||||
fputs ("\t.long ", FILE); \
|
||||
ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \
|
||||
assemble_name (FILE, buf); \
|
||||
putc ('-', FILE); \
|
||||
ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \
|
||||
assemble_name (FILE, buf); \
|
||||
putc ('\n', FILE); \
|
||||
} while (0)
|
||||
|
||||
/* Misc. */
|
||||
|
||||
#define CASE_VECTOR_MODE SImode
|
||||
#define MOVE_MAX 4
|
||||
#define MOVE_RATIO(SPEED) 4
|
||||
#define TRULY_NOOP_TRUNCATION(outprec, inprec) 1
|
||||
#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1)
|
||||
#define Pmode SImode
|
||||
#define FUNCTION_MODE QImode
|
||||
|
||||
extern int c6x_initial_flag_pic;
|
||||
|
||||
#endif /* GCC_C6X_H */
|
||||
3004
gcc/config/c6x/c6x.md
Normal file
3004
gcc/config/c6x/c6x.md
Normal file
File diff suppressed because it is too large
Load diff
67
gcc/config/c6x/c6x.opt
Normal file
67
gcc/config/c6x/c6x.opt
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
; Option definitions for TI C6X.
|
||||
; Copyright (C) 2010, 2011 Free Software Foundation, Inc.
|
||||
; Contributed by Bernd Schmidt <bernds@codesourcery.com>
|
||||
; Contributed by CodeSourcery.
|
||||
;
|
||||
; This file is part of GCC.
|
||||
;
|
||||
; GCC is free software; you can redistribute it and/or modify
|
||||
; it under the terms of the GNU General Public License as published by
|
||||
; the Free Software Foundation; either version 3, or (at your option)
|
||||
; any later version.
|
||||
;
|
||||
; GCC is distributed in the hope that it will be useful,
|
||||
; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
; GNU General Public License for more details.
|
||||
;
|
||||
; You should have received a copy of the GNU General Public License
|
||||
; along with GCC; see the file COPYING3. If not see
|
||||
; <http://www.gnu.org/licenses/>.
|
||||
|
||||
HeaderInclude
|
||||
config/c6x/c6x-opts.h
|
||||
|
||||
SourceInclude
|
||||
config/c6x/c6x-opts.h
|
||||
|
||||
mbig-endian
|
||||
Target Report RejectNegative Mask(BIG_ENDIAN)
|
||||
Use big-endian byte order
|
||||
|
||||
mlittle-endian
|
||||
Target Report RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN)
|
||||
Use little-endian byte order
|
||||
|
||||
msim
|
||||
Target RejectNegative
|
||||
Use simulator runtime
|
||||
|
||||
msdata=
|
||||
Target RejectNegative Enum(c6x_sdata) Joined Var(c6x_sdata_mode) Init(C6X_SDATA_DEFAULT)
|
||||
Select method for sdata handling
|
||||
|
||||
Enum
|
||||
Name(c6x_sdata) Type(enum c6x_sdata)
|
||||
Valid arguments for the -msdata= option
|
||||
|
||||
EnumValue
|
||||
Enum(c6x_sdata) String(none) Value(C6X_SDATA_NONE)
|
||||
|
||||
EnumValue
|
||||
Enum(c6x_sdata) String(default) Value(C6X_SDATA_DEFAULT)
|
||||
|
||||
EnumValue
|
||||
Enum(c6x_sdata) String(all) Value(C6X_SDATA_ALL)
|
||||
|
||||
mdsbt
|
||||
Target Mask(DSBT)
|
||||
Compile for the DSBT shared library ABI
|
||||
|
||||
mlong-calls
|
||||
Target Report Mask(LONG_CALLS)
|
||||
Avoid generating pc-relative calls; use indirection
|
||||
|
||||
march=
|
||||
Target RejectNegative Joined Enum(c6x_isa) Var(c6x_arch_option)
|
||||
Specify the name of the target architecture
|
||||
194
gcc/config/c6x/c6x_intrinsics.h
Normal file
194
gcc/config/c6x/c6x_intrinsics.h
Normal file
|
|
@ -0,0 +1,194 @@
|
|||
/* Intrinsics for TI C6X.
|
||||
|
||||
Copyright (C) 2011 Free Software Foundation, Inc.
|
||||
Contributed by CodeSourcery.
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
|
||||
option) any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
Under Section 7 of GPL version 3, you are granted additional
|
||||
permissions described in the GCC Runtime Library Exception, version
|
||||
3.1, as published by the Free Software Foundation.
|
||||
|
||||
You should have received a copy of the GNU General Public License and
|
||||
a copy of the GCC Runtime Library Exception along with this program;
|
||||
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#ifndef _GCC_C6X_INTRINSICS_H
|
||||
#define _GCC_C6X_INTRINSICS_H
|
||||
|
||||
#if !defined(__TMS320C6X__)
|
||||
# error "c6x_intrinsics.h is only supported for C6X targets"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* Define vector types. */
|
||||
typedef uint8_t __uv4qi __attribute__((vector_size (4)));
|
||||
typedef int16_t __v2hi __attribute__((vector_size (4)));
|
||||
typedef int32_t __v2si __attribute__((vector_size (8)));
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_abs (int src)
|
||||
{
|
||||
return __builtin_c6x_abs (src);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_abs2 (int src)
|
||||
{
|
||||
return (int)__builtin_c6x_abs2 ((__v2hi)src);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_sadd (int src1, int src2)
|
||||
{
|
||||
return __builtin_c6x_sadd (src1, src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_ssub (int src1, int src2)
|
||||
{
|
||||
return __builtin_c6x_ssub (src1, src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_add2 (int src1, int src2)
|
||||
{
|
||||
return (int)__builtin_c6x_add2 ((__v2hi)src1, (__v2hi)src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_sub2 (int src1, int src2)
|
||||
{
|
||||
return (int)__builtin_c6x_sub2 ((__v2hi)src1, (__v2hi)src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_add4 (int src1, int src2)
|
||||
{
|
||||
return (int)__builtin_c6x_add4 ((__uv4qi)src1, (__uv4qi)src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_sub4 (int src1, int src2)
|
||||
{
|
||||
return (int)__builtin_c6x_sub4 ((__uv4qi)src1, (__uv4qi)src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_sadd2 (int src1, int src2)
|
||||
{
|
||||
return (int)__builtin_c6x_sadd2 ((__v2hi)src1, (__v2hi)src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_ssub2 (int src1, int src2)
|
||||
{
|
||||
return (int)__builtin_c6x_ssub2 ((__v2hi)src1, (__v2hi)src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_saddu4 (int src1, int src2)
|
||||
{
|
||||
return (int)__builtin_c6x_saddu4 ((__uv4qi)src1, (__uv4qi)src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_smpy (int src1, int src2)
|
||||
{
|
||||
return __builtin_c6x_smpy (src1, src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_smpylh (int src1, int src2)
|
||||
{
|
||||
return __builtin_c6x_smpylh (src1, src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_smpyhl (int src1, int src2)
|
||||
{
|
||||
return __builtin_c6x_smpyhl (src1, src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_smpyh (int src1, int src2)
|
||||
{
|
||||
return __builtin_c6x_smpyh (src1, src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline long long __attribute__ ((__always_inline__))
|
||||
_smpy2ll (int src1, int src2)
|
||||
{
|
||||
return (long long)__builtin_c6x_smpy2 ((__v2hi)src1, (__v2hi)src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline long long __attribute__ ((__always_inline__))
|
||||
_mpy2ll (int src1, int src2)
|
||||
{
|
||||
return (long long)__builtin_c6x_mpy2 ((__v2hi)src1, (__v2hi)src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_extr (int src1, int src2)
|
||||
{
|
||||
return __builtin_c6x_extr (src1, src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_extru (int src1, int src2)
|
||||
{
|
||||
return __builtin_c6x_extru (src1, src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_clrr (int src1, int src2)
|
||||
{
|
||||
return __builtin_c6x_clrr (src1, src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_avg2 (int src1, int src2)
|
||||
{
|
||||
return (int)__builtin_c6x_avg2 ((__v2hi)src1, (__v2hi)src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_avgu4 (int src1, int src2)
|
||||
{
|
||||
return (int)__builtin_c6x_avgu4 ((__uv4qi)src1, (__uv4qi)src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_sshl (int src1, int src2)
|
||||
{
|
||||
return __builtin_c6x_sshl (src1, src2);
|
||||
}
|
||||
|
||||
__extension__ static __inline int __attribute__ ((__always_inline__))
|
||||
_subc (int src1, int src2)
|
||||
{
|
||||
return __builtin_c6x_subc (src1, src2);
|
||||
}
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
174
gcc/config/c6x/constraints.md
Normal file
174
gcc/config/c6x/constraints.md
Normal file
|
|
@ -0,0 +1,174 @@
|
|||
;; Constraint definitions for TI C6X.
|
||||
;; Copyright (C) 2010, 2011 Free Software Foundation, Inc.
|
||||
;; Contributed by Andrew Jenner <andrew@codesourcery.com>
|
||||
;; Contributed by Bernd Schmidt <bernds@codesourcery.com>
|
||||
;; Contributed by CodeSourcery.
|
||||
;;
|
||||
;; This file is part of GCC.
|
||||
;;
|
||||
;; GCC is free software; you can redistribute it and/or modify
|
||||
;; it under the terms of the GNU General Public License as published by
|
||||
;; the Free Software Foundation; either version 3, or (at your option)
|
||||
;; any later version.
|
||||
;;
|
||||
;; GCC is distributed in the hope that it will be useful,
|
||||
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
;; GNU General Public License for more details.
|
||||
;;
|
||||
;; You should have received a copy of the GNU General Public License
|
||||
;; along with GCC; see the file COPYING3. If not see
|
||||
;; <http://www.gnu.org/licenses/>.
|
||||
|
||||
(define_register_constraint "a" "A_REGS"
|
||||
"Register file A (A0--A31).")
|
||||
|
||||
(define_register_constraint "b" "B_REGS"
|
||||
"Register file B (B0--B31).")
|
||||
|
||||
(define_register_constraint "A" "PREDICATE_A_REGS"
|
||||
"Predicate registers in register file A (A0--A2 on C64X and higher,
|
||||
A1 and A2 otherwise).")
|
||||
|
||||
(define_register_constraint "B" "PREDICATE_B_REGS"
|
||||
"Predicate registers in register file B (B0--B2).")
|
||||
|
||||
(define_register_constraint "C" "CALL_USED_B_REGS"
|
||||
"A call-used register in register file B (B0--B9, B16--B31).")
|
||||
|
||||
(define_register_constraint "Da" "NONPREDICATE_A_REGS"
|
||||
"Register file A, excluding predicate registers (A3--A31, plus A0 if
|
||||
not C64X or higher).")
|
||||
|
||||
(define_register_constraint "Db" "NONPREDICATE_B_REGS"
|
||||
"Register file B, excluding predicate registers (B3--B31).")
|
||||
|
||||
(define_register_constraint "Z" "PICREG"
|
||||
"Register B14 (aka DP).")
|
||||
|
||||
(define_register_constraint "z" "SPREG"
|
||||
"Register B15 (aka SP).")
|
||||
|
||||
(define_constraint "Iu4"
|
||||
"Integer constant in the range 0 @dots{} 15, aka ucst4."
|
||||
(and (match_code "const_int")
|
||||
(match_test "ival >= 0 && ival <= 15")))
|
||||
|
||||
(define_constraint "Iu5"
|
||||
"Integer constant in the range 0 @dots{} 31, aka ucst5."
|
||||
(and (match_code "const_int")
|
||||
(match_test "ival >= 0 && ival <= 31")))
|
||||
|
||||
(define_constraint "In5"
|
||||
"Integer constant in the range @minus{}31 @dots{} 0, negation of ucst5."
|
||||
(and (match_code "const_int")
|
||||
(match_test "ival >= -31 && ival <= 0")))
|
||||
|
||||
(define_constraint "Is5"
|
||||
"Integer constant in the range @minus{}16 @dots{} 15, aka scst5."
|
||||
(and (match_code "const_int")
|
||||
(match_test "ival >= -16 && ival <= 15")))
|
||||
|
||||
(define_constraint "I5x"
|
||||
"Integer constant that can be the operand of an ADDA or a SUBA insn."
|
||||
(and (match_code "const_int")
|
||||
(match_test "(ival >= -31 && ival <= 31)
|
||||
|| ((ival & 1) == 0 && ival >= -62 && ival <= 62)
|
||||
|| ((ival & 3) == 0 && ival >= -124 && ival <= 124)
|
||||
|| ((TARGET_INSNS_64 || TARGET_INSNS_67)
|
||||
&& (ival & 7) == 0 && ival > 0 && ival <= 248)")))
|
||||
|
||||
(define_constraint "Iux"
|
||||
"Integer constant that can be the operand of a long ADDA or a SUBA insn,
|
||||
i.e. one involving B14 or B15 as source operand."
|
||||
(and (match_code "const_int")
|
||||
(and (match_test "TARGET_INSNS_64PLUS")
|
||||
(match_test "ival >= 0
|
||||
&& (ival < 32768
|
||||
|| ((ival & 1) == 0 && ival < 65536)
|
||||
|| ((ival & 3) == 0 && ival < 131072))"))))
|
||||
|
||||
(define_constraint "IuB"
|
||||
"Integer constant in the range 0 @dots{} 65535, aka ucst16."
|
||||
(and (match_code "const_int")
|
||||
(match_test "ival >= 0 && ival <= 65535")))
|
||||
|
||||
(define_constraint "IsB"
|
||||
"Integer constant in the range @minus{}32768 @dots{} 32767."
|
||||
(and (match_code "const_int")
|
||||
(match_test "ival >= -32768 && ival <= 32767")))
|
||||
|
||||
(define_constraint "IsC"
|
||||
"Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}."
|
||||
(and (match_code "const_int")
|
||||
(match_test "ival >= -0x100000 && ival <= 0xfffff")))
|
||||
|
||||
(define_constraint "JA"
|
||||
"@internal
|
||||
Integer constant in the range 0 @dots{} 31, corresponding to an A register
|
||||
number."
|
||||
(and (match_code "const_int")
|
||||
(match_test "ival >= 0 && ival < 32")))
|
||||
|
||||
(define_constraint "JB"
|
||||
"@internal
|
||||
Integer constant in the range 32 @dots{} 63, corresponding to a B register
|
||||
number."
|
||||
(and (match_code "const_int")
|
||||
(match_test "ival >= 32 && ival < 64")))
|
||||
|
||||
(define_constraint "Jc"
|
||||
"Integer constant that is a valid mask for the clr instruction"
|
||||
(and (match_code "const_int")
|
||||
(match_test "c6x_valid_mask_p (ival)")))
|
||||
|
||||
(define_constraint "Js"
|
||||
"Integer constant that is a valid mask for the set instruction"
|
||||
(and (match_code "const_int")
|
||||
(match_test "c6x_valid_mask_p (~ival)")))
|
||||
|
||||
(define_memory_constraint "Q"
|
||||
"Memory location with A base register."
|
||||
(and (match_code "mem")
|
||||
(match_test "c6x_mem_operand (op, A_REGS, false)")))
|
||||
|
||||
(define_memory_constraint "R"
|
||||
"Memory location with B base register."
|
||||
(and (match_code "mem")
|
||||
(match_test "c6x_mem_operand (op, B_REGS, false)")))
|
||||
|
||||
(define_memory_constraint "T"
|
||||
"@internal
|
||||
Memory location with B base register, but not using a long offset."
|
||||
(and (match_code "mem")
|
||||
(match_test "c6x_mem_operand (op, B_REGS, true)")))
|
||||
|
||||
(define_constraint "S0"
|
||||
"@internal
|
||||
On C64x+ targets, a GP-relative small data reference"
|
||||
(and (match_test "TARGET_INSNS_64PLUS")
|
||||
(match_operand 0 "sdata_symbolic_operand")))
|
||||
|
||||
(define_constraint "S1"
|
||||
"@internal
|
||||
Any kind of @code{SYMBOL_REF}, for use in a call address."
|
||||
(and (match_code "symbol_ref")
|
||||
(match_operand 0 "c6x_call_operand")))
|
||||
|
||||
(define_constraint "S2"
|
||||
"@internal
|
||||
Any SYMBOL_REF or LABEL_REF."
|
||||
(ior (match_code "symbol_ref") (match_code "label_ref")))
|
||||
|
||||
(define_constraint "Si"
|
||||
"@internal
|
||||
Any immediate value, unless it matches the S0 constraint."
|
||||
(and (match_operand 0 "immediate_operand")
|
||||
(match_test "!satisfies_constraint_S0 (op)")))
|
||||
|
||||
(define_memory_constraint "W"
|
||||
"@internal
|
||||
A memory operand with an address that can't be used in an unaligned access."
|
||||
(and (match_code "mem")
|
||||
(match_test "!c6x_legitimate_address_p_1 (GET_MODE (op), XEXP (op, 0),
|
||||
reload_completed, true)")))
|
||||
39
gcc/config/c6x/crti.s
Normal file
39
gcc/config/c6x/crti.s
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
/* Copyright 2010, 2011 Free Software Foundation, Inc.
|
||||
Contributed by Bernd Schmidt <bernds@codesourcery.com>.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 3, or (at your option) any
|
||||
later version.
|
||||
|
||||
This file is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
General Public License for more details.
|
||||
|
||||
Under Section 7 of GPL version 3, you are granted additional
|
||||
permissions described in the GCC Runtime Library Exception, version
|
||||
3.1, as published by the Free Software Foundation.
|
||||
|
||||
You should have received a copy of the GNU General Public License and
|
||||
a copy of the GCC Runtime Library Exception along with this program;
|
||||
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
/*
|
||||
* This file just supplies function prologues for the .init and .fini
|
||||
* sections. It is linked in before crtbegin.o.
|
||||
*/
|
||||
|
||||
.section .init
|
||||
.globl _init
|
||||
.type _init,@function
|
||||
_init:
|
||||
add .l2 -8, B15, B15
|
||||
stw .d2t2 B3,*+B15(4)
|
||||
.section .fini
|
||||
.globl _fini
|
||||
.type _fini,@function
|
||||
_fini:
|
||||
add .l2 -8, B15, B15
|
||||
stw .d2t2 B3,*+B15(4)
|
||||
41
gcc/config/c6x/crtn.s
Normal file
41
gcc/config/c6x/crtn.s
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
/* Copyright 2010, 2011 Free Software Foundation, Inc.
|
||||
Contributed by Bernd Schmidt <bernds@codesourcery.com>.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 3, or (at your option) any
|
||||
later version.
|
||||
|
||||
This file is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
General Public License for more details.
|
||||
|
||||
Under Section 7 of GPL version 3, you are granted additional
|
||||
permissions described in the GCC Runtime Library Exception, version
|
||||
3.1, as published by the Free Software Foundation.
|
||||
|
||||
You should have received a copy of the GNU General Public License and
|
||||
a copy of the GCC Runtime Library Exception along with this program;
|
||||
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
/*
|
||||
* This file supplies function epilogues for the .init and .fini sections.
|
||||
* It is linked in after all other files.
|
||||
*/
|
||||
|
||||
.section .init
|
||||
ldw .d2t2 *+B15(4), B3
|
||||
add .d2 B15, 8, B15
|
||||
nop 3
|
||||
ret .s2 B3
|
||||
nop 5
|
||||
|
||||
.section .fini
|
||||
ldw .d2t2 *+B15(4), B3
|
||||
add .d2 B15, 8, B15
|
||||
nop 3
|
||||
ret .s2 B3
|
||||
nop 5
|
||||
|
||||
37
gcc/config/c6x/elf-common.h
Normal file
37
gcc/config/c6x/elf-common.h
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
/* ELF definitions for TI C6X
|
||||
Copyright (C) 2010 Free Software Foundation, Inc.
|
||||
Contributed by Andrew Jenner <andrew@codesourcery.com>
|
||||
Contributed by Bernd Schmidt <bernds@codesourcery.com>
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
|
||||
option) any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
/* Controlling the Compilation Driver. */
|
||||
#define ENDIAN_LINK_SPEC "%{mbig-endian:-EB} %{mlittle-endian:-EL} "
|
||||
|
||||
#undef ASM_SPEC
|
||||
#define ASM_SPEC "%{march=*:-march=%*} %{mbig-endian:-mbig-endian} \
|
||||
%{mdsbt:-mdsbt %{!fPIC:-mpid=near} %{fPIC:-mpid=far -mpic} %{fpic:-mpic}} \
|
||||
%{!mdsbt:%{fpic:-mpic -mpid=near} %{fPIC:-mpic -mpid=far}}"
|
||||
|
||||
#undef DATA_SECTION_ASM_OP
|
||||
#define DATA_SECTION_ASM_OP "\t.section\t\".fardata\",\"aw\""
|
||||
#undef READONLY_DATA_SECTION_ASM_OP
|
||||
#define READONLY_DATA_SECTION_ASM_OP "\t.section\t\".const\",\"a\",@progbits"
|
||||
#define BSS_SECTION_ASM_OP "\t.section\t\".far\",\"aw\",@nobits"
|
||||
#define SDATA_SECTION_ASM_OP "\t.section\t\".neardata\",\"aw\""
|
||||
#define SBSS_SECTION_ASM_OP "\t.section\t\".bss\",\"aw\",@nobits"
|
||||
#define TARGET_LIBGCC_SDATA_SECTION ".neardata"
|
||||
35
gcc/config/c6x/elf.h
Normal file
35
gcc/config/c6x/elf.h
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
/* ELF definitions for TI C6X
|
||||
Copyright (C) 2010 Free Software Foundation, Inc.
|
||||
Contributed by Andrew Jenner <andrew@codesourcery.com>
|
||||
Contributed by Bernd Schmidt <bernds@codesourcery.com>
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
|
||||
option) any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
/* crt0.o should come from the linker script, but for compatibility,
|
||||
we mention it here for -msim. */
|
||||
#undef STARTFILE_SPEC
|
||||
#define STARTFILE_SPEC "%{msim:crt0%O%s} crti%O%s crtbegin%O%s"
|
||||
|
||||
#undef ENDFILE_SPEC
|
||||
#define ENDFILE_SPEC "crtend%O%s crtn%O%s"
|
||||
|
||||
#undef LIB_SPEC
|
||||
#define LIB_SPEC "%{msim:--start-group -lc -lsim --end-group;" \
|
||||
":-lc}"
|
||||
|
||||
#undef LINK_SPEC
|
||||
#define LINK_SPEC ENDIAN_LINK_SPEC
|
||||
47
gcc/config/c6x/eqd.c
Normal file
47
gcc/config/c6x/eqd.c
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/* Software floating-point emulation.
|
||||
Return 1 iff a == b, 0 otherwise.
|
||||
Copyright (C) 1997,1999,2006,2007,2011 Free Software Foundation, Inc.
|
||||
Contributed by Richard Henderson (rth@cygnus.com) and
|
||||
Jakub Jelinek (jj@ultra.linux.cz).
|
||||
|
||||
This file is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
In addition to the permissions in the GNU Lesser General Public
|
||||
License, the Free Software Foundation gives you unlimited
|
||||
permission to link the compiled version of this file into
|
||||
combinations with other programs, and to distribute those
|
||||
combinations without any restriction coming from the use of this
|
||||
file. (The Lesser General Public License restrictions do apply in
|
||||
other respects; for example, they cover modification of the file,
|
||||
and distribution when not linked into a combine executable.)
|
||||
|
||||
This file is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with GCC; see the file COPYING.LIB. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#include "config/soft-fp/soft-fp.h"
|
||||
#include "config/soft-fp/double.h"
|
||||
|
||||
CMPtype __c6xabi_eqd(DFtype a, DFtype b)
|
||||
{
|
||||
FP_DECL_EX;
|
||||
FP_DECL_D(A); FP_DECL_D(B);
|
||||
CMPtype r;
|
||||
|
||||
FP_UNPACK_RAW_D(A, a);
|
||||
FP_UNPACK_RAW_D(B, b);
|
||||
FP_CMP_EQ_D(r, A, B);
|
||||
if (r && (FP_ISSIGNAN_D(A) || FP_ISSIGNAN_D(B)))
|
||||
FP_SET_EXCEPTION(FP_EX_INVALID);
|
||||
FP_HANDLE_EXCEPTIONS;
|
||||
|
||||
return !r;
|
||||
}
|
||||
47
gcc/config/c6x/eqf.c
Normal file
47
gcc/config/c6x/eqf.c
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/* Software floating-point emulation.
|
||||
Return 1 iff a == b, 0 otherwise.
|
||||
Copyright (C) 1997,1999,2006,2007,2011 Free Software Foundation, Inc.
|
||||
Contributed by Richard Henderson (rth@cygnus.com) and
|
||||
Jakub Jelinek (jj@ultra.linux.cz).
|
||||
|
||||
This file is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
In addition to the permissions in the GNU Lesser General Public
|
||||
License, the Free Software Foundation gives you unlimited
|
||||
permission to link the compiled version of this file into
|
||||
combinations with other programs, and to distribute those
|
||||
combinations without any restriction coming from the use of this
|
||||
file. (The Lesser General Public License restrictions do apply in
|
||||
other respects; for example, they cover modification of the file,
|
||||
and distribution when not linked into a combine executable.)
|
||||
|
||||
This file is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with GCC; see the file COPYING.LIB. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#include "config/soft-fp/soft-fp.h"
|
||||
#include "config/soft-fp/single.h"
|
||||
|
||||
CMPtype __c6xabi_eqf(SFtype a, SFtype b)
|
||||
{
|
||||
FP_DECL_EX;
|
||||
FP_DECL_S(A); FP_DECL_S(B);
|
||||
CMPtype r;
|
||||
|
||||
FP_UNPACK_RAW_S(A, a);
|
||||
FP_UNPACK_RAW_S(B, b);
|
||||
FP_CMP_EQ_S(r, A, B);
|
||||
if (r && (FP_ISSIGNAN_S(A) || FP_ISSIGNAN_S(B)))
|
||||
FP_SET_EXCEPTION(FP_EX_INVALID);
|
||||
FP_HANDLE_EXCEPTIONS;
|
||||
|
||||
return !r;
|
||||
}
|
||||
47
gcc/config/c6x/ged.c
Normal file
47
gcc/config/c6x/ged.c
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/* Software floating-point emulation.
|
||||
Return 1 iff a >= b, 0 otherwise.
|
||||
Copyright (C) 1997,1999,2006,2007,2011 Free Software Foundation, Inc.
|
||||
Contributed by Richard Henderson (rth@cygnus.com) and
|
||||
Jakub Jelinek (jj@ultra.linux.cz).
|
||||
|
||||
This file is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
In addition to the permissions in the GNU Lesser General Public
|
||||
License, the Free Software Foundation gives you unlimited
|
||||
permission to link the compiled version of this file into
|
||||
combinations with other programs, and to distribute those
|
||||
combinations without any restriction coming from the use of this
|
||||
file. (The Lesser General Public License restrictions do apply in
|
||||
other respects; for example, they cover modification of the file,
|
||||
and distribution when not linked into a combine executable.)
|
||||
|
||||
This file is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with GCC; see the file COPYING.LIB. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#include "config/soft-fp/soft-fp.h"
|
||||
#include "config/soft-fp/double.h"
|
||||
|
||||
CMPtype __c6xabi_ged(DFtype a, DFtype b)
|
||||
{
|
||||
FP_DECL_EX;
|
||||
FP_DECL_D(A); FP_DECL_D(B);
|
||||
CMPtype r;
|
||||
|
||||
FP_UNPACK_RAW_D(A, a);
|
||||
FP_UNPACK_RAW_D(B, b);
|
||||
FP_CMP_D(r, A, B, -2);
|
||||
if (r == -2 && (FP_ISSIGNAN_D(A) || FP_ISSIGNAN_D(B)))
|
||||
FP_SET_EXCEPTION(FP_EX_INVALID);
|
||||
FP_HANDLE_EXCEPTIONS;
|
||||
|
||||
return r >= 0;
|
||||
}
|
||||
47
gcc/config/c6x/gef.c
Normal file
47
gcc/config/c6x/gef.c
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/* Software floating-point emulation.
|
||||
Return 1 iff a >= b, 0 otherwise.
|
||||
Copyright (C) 1997,1999,2006,2007 Free Software Foundation, Inc.
|
||||
Contributed by Richard Henderson (rth@cygnus.com) and
|
||||
Jakub Jelinek (jj@ultra.linux.cz).
|
||||
|
||||
This file is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
In addition to the permissions in the GNU Lesser General Public
|
||||
License, the Free Software Foundation gives you unlimited
|
||||
permission to link the compiled version of this file into
|
||||
combinations with other programs, and to distribute those
|
||||
combinations without any restriction coming from the use of this
|
||||
file. (The Lesser General Public License restrictions do apply in
|
||||
other respects; for example, they cover modification of the file,
|
||||
and distribution when not linked into a combine executable.)
|
||||
|
||||
This file is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with GCC; see the file COPYING.LIB. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#include "config/soft-fp/soft-fp.h"
|
||||
#include "config/soft-fp/single.h"
|
||||
|
||||
CMPtype __c6xabi_gef(SFtype a, SFtype b)
|
||||
{
|
||||
FP_DECL_EX;
|
||||
FP_DECL_S(A); FP_DECL_S(B);
|
||||
CMPtype r;
|
||||
|
||||
FP_UNPACK_RAW_S(A, a);
|
||||
FP_UNPACK_RAW_S(B, b);
|
||||
FP_CMP_S(r, A, B, -2);
|
||||
if (r == -2 && (FP_ISSIGNAN_S(A) || FP_ISSIGNAN_S(B)))
|
||||
FP_SET_EXCEPTION(FP_EX_INVALID);
|
||||
FP_HANDLE_EXCEPTIONS;
|
||||
|
||||
return r >= 0;
|
||||
}
|
||||
33
gcc/config/c6x/genmult.sh
Normal file
33
gcc/config/c6x/genmult.sh
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
#! /bin/sh
|
||||
# Generate c6x-mult.md from c6x-mult.md.in
|
||||
# The input file is passed as an argument.
|
||||
|
||||
# Copyright 2011 Free Software Foundation, Inc.
|
||||
|
||||
#This file is part of GCC.
|
||||
|
||||
#GCC is free software; you can redistribute it and/or modify
|
||||
#it under the terms of the GNU General Public License as published by
|
||||
#the Free Software Foundation; either version 3, or (at your option)
|
||||
#any later version.
|
||||
|
||||
#GCC is distributed in the hope that it will be useful,
|
||||
#but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
#MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
#GNU General Public License for more details.
|
||||
|
||||
#You should have received a copy of the GNU General Public License
|
||||
#along with GCC; see the file COPYING3. If not see
|
||||
#<http://www.gnu.org/licenses/>.
|
||||
|
||||
echo ";; -*- buffer-read-only: t -*-"
|
||||
echo ";; Generated automatically from c6x-mult.md.in by genmult.sh"
|
||||
|
||||
sed -e "s,_VARIANT_,,g" -e "s,_SET_,set,g" -e "s,_.BRK_,,g" \
|
||||
-e "s,_A_,a,g" -e "s,_B_,b,g" -e "s,_DESTOPERAND_,register_operand,g" \
|
||||
-e "s,_MOD._,,g" -e "s,:_M,:,g" < $1
|
||||
|
||||
sed -e "s,_VARIANT_,_real,g" -e "s,_SET_,unspec,g" -e "s,_OBRK_,[,g" \
|
||||
-e "s,_CBRK_,] UNSPEC_REAL_MULT,g" -e "s,_A_,JA,g" -e "s,_B_,JB,g" \
|
||||
-e "s,_DESTOPERAND_,const_int_operand,g" -e "s,_MODk_,k,g" \
|
||||
-e "s,_MODK_,K,g" -e 's,:_MV..[IQ],:SI,g' -e "s,:_MSQ,:SI,g" < $1
|
||||
59
gcc/config/c6x/genopt.sh
Normal file
59
gcc/config/c6x/genopt.sh
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
#!/bin/sh
|
||||
# Generate c6x-tables.opt from the lists in *.def.
|
||||
# Copyright (C) 2011 Free Software Foundation, Inc.
|
||||
#
|
||||
# This file is part of GCC.
|
||||
#
|
||||
# GCC is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 3, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# GCC is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with GCC; see the file COPYING3. If not see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
|
||||
cat <<EOF
|
||||
; -*- buffer-read-only: t -*-
|
||||
; Generated automatically by genopt.sh from c6x-isas.def.
|
||||
;
|
||||
; Copyright (C) 2011 Free Software Foundation, Inc.
|
||||
;
|
||||
; This file is part of GCC.
|
||||
;
|
||||
; GCC is free software; you can redistribute it and/or modify it under
|
||||
; the terms of the GNU General Public License as published by the Free
|
||||
; Software Foundation; either version 3, or (at your option) any later
|
||||
; version.
|
||||
;
|
||||
; GCC is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
; WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
; for more details.
|
||||
;
|
||||
; You should have received a copy of the GNU General Public License
|
||||
; along with GCC; see the file COPYING3. If not see
|
||||
; <http://www.gnu.org/licenses/>.
|
||||
|
||||
Enum
|
||||
Name(c6x_isa) Type(int)
|
||||
Known C6X ISAs (for use with the -march= option):
|
||||
|
||||
EOF
|
||||
|
||||
awk -F'[(, ]+' 'BEGIN {
|
||||
value = 0
|
||||
}
|
||||
/^C6X_ISA/ {
|
||||
name = $2
|
||||
gsub("\"", "", name)
|
||||
print "EnumValue"
|
||||
print "Enum(c6x_isa) String(" name ") Value(" value ")"
|
||||
print ""
|
||||
value++
|
||||
}' $1/c6x-isas.def
|
||||
44
gcc/config/c6x/gensched.sh
Normal file
44
gcc/config/c6x/gensched.sh
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
#! /bin/sh
|
||||
# Generate c6x-sched.md from c6x-sched.md.in
|
||||
# The input file is passed as an argument.
|
||||
|
||||
# Copyright 2010, 2011 Free Software Foundation, Inc.
|
||||
|
||||
#This file is part of GCC.
|
||||
|
||||
#GCC is free software; you can redistribute it and/or modify
|
||||
#it under the terms of the GNU General Public License as published by
|
||||
#the Free Software Foundation; either version 3, or (at your option)
|
||||
#any later version.
|
||||
|
||||
#GCC is distributed in the hope that it will be useful,
|
||||
#but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
#MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
#GNU General Public License for more details.
|
||||
|
||||
#You should have received a copy of the GNU General Public License
|
||||
#along with GCC; see the file COPYING3. If not see
|
||||
#<http://www.gnu.org/licenses/>.
|
||||
|
||||
echo ";; -*- buffer-read-only: t -*-"
|
||||
echo ";; Generated automatically from c6x-sched.md.in by gensched.sh"
|
||||
|
||||
for cross in n y; do
|
||||
for side in 1 2; do
|
||||
tside=$side
|
||||
case $side in
|
||||
1) rf="a"; otherside=2 ;;
|
||||
2) rf="b"; otherside=1 ;;
|
||||
esac
|
||||
case $cross in
|
||||
y) cunit="+x$side"; tside=$otherside;;
|
||||
n) cunit="";;
|
||||
esac
|
||||
echo
|
||||
echo ";; Definitions for side $side, cross $cross"
|
||||
echo
|
||||
sed -e "s,_CROSS_,$cross,g" -e "s,_CUNIT_,$cunit,g" \
|
||||
-e "s,_N_,$side,g" -e "s,_RF_,$rf,g" -e "s,_NX_,$tside,g" \
|
||||
< $1
|
||||
done
|
||||
done
|
||||
47
gcc/config/c6x/gtd.c
Normal file
47
gcc/config/c6x/gtd.c
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/* Software floating-point emulation.
|
||||
Return 1 iff a > b, 0 otherwise.
|
||||
Copyright (C) 1997,1999,2006,2007,2011 Free Software Foundation, Inc.
|
||||
Contributed by Richard Henderson (rth@cygnus.com) and
|
||||
Jakub Jelinek (jj@ultra.linux.cz).
|
||||
|
||||
This file is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
In addition to the permissions in the GNU Lesser General Public
|
||||
License, the Free Software Foundation gives you unlimited
|
||||
permission to link the compiled version of this file into
|
||||
combinations with other programs, and to distribute those
|
||||
combinations without any restriction coming from the use of this
|
||||
file. (The Lesser General Public License restrictions do apply in
|
||||
other respects; for example, they cover modification of the file,
|
||||
and distribution when not linked into a combine executable.)
|
||||
|
||||
This file is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with GCC; see the file COPYING.LIB. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#include "config/soft-fp/soft-fp.h"
|
||||
#include "config/soft-fp/double.h"
|
||||
|
||||
CMPtype __c6xabi_gtd(DFtype a, DFtype b)
|
||||
{
|
||||
FP_DECL_EX;
|
||||
FP_DECL_D(A); FP_DECL_D(B);
|
||||
CMPtype r;
|
||||
|
||||
FP_UNPACK_RAW_D(A, a);
|
||||
FP_UNPACK_RAW_D(B, b);
|
||||
FP_CMP_D(r, A, B, -2);
|
||||
if (r == -2 && (FP_ISSIGNAN_D(A) || FP_ISSIGNAN_D(B)))
|
||||
FP_SET_EXCEPTION(FP_EX_INVALID);
|
||||
FP_HANDLE_EXCEPTIONS;
|
||||
|
||||
return r > 0;
|
||||
}
|
||||
47
gcc/config/c6x/gtf.c
Normal file
47
gcc/config/c6x/gtf.c
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/* Software floating-point emulation.
|
||||
Return 1 iff a > b, 0 otherwise.
|
||||
Copyright (C) 1997,1999,2006,2007,2011 Free Software Foundation, Inc.
|
||||
Contributed by Richard Henderson (rth@cygnus.com) and
|
||||
Jakub Jelinek (jj@ultra.linux.cz).
|
||||
|
||||
This file is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
In addition to the permissions in the GNU Lesser General Public
|
||||
License, the Free Software Foundation gives you unlimited
|
||||
permission to link the compiled version of this file into
|
||||
combinations with other programs, and to distribute those
|
||||
combinations without any restriction coming from the use of this
|
||||
file. (The Lesser General Public License restrictions do apply in
|
||||
other respects; for example, they cover modification of the file,
|
||||
and distribution when not linked into a combine executable.)
|
||||
|
||||
This file is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with GCC; see the file COPYING.LIB. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#include "config/soft-fp/soft-fp.h"
|
||||
#include "config/soft-fp/single.h"
|
||||
|
||||
CMPtype __c6xabi_gtf(SFtype a, SFtype b)
|
||||
{
|
||||
FP_DECL_EX;
|
||||
FP_DECL_S(A); FP_DECL_S(B);
|
||||
CMPtype r;
|
||||
|
||||
FP_UNPACK_RAW_S(A, a);
|
||||
FP_UNPACK_RAW_S(B, b);
|
||||
FP_CMP_S(r, A, B, -2);
|
||||
if (r == -2 && (FP_ISSIGNAN_S(A) || FP_ISSIGNAN_S(B)))
|
||||
FP_SET_EXCEPTION(FP_EX_INVALID);
|
||||
FP_HANDLE_EXCEPTIONS;
|
||||
|
||||
return r > 0;
|
||||
}
|
||||
47
gcc/config/c6x/led.c
Normal file
47
gcc/config/c6x/led.c
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/* Software floating-point emulation.
|
||||
Return 1 iff a <= b, 0 otherwise.
|
||||
Copyright (C) 1997,1999,2006,2007,2011 Free Software Foundation, Inc.
|
||||
Contributed by Richard Henderson (rth@cygnus.com) and
|
||||
Jakub Jelinek (jj@ultra.linux.cz).
|
||||
|
||||
This file is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
In addition to the permissions in the GNU Lesser General Public
|
||||
License, the Free Software Foundation gives you unlimited
|
||||
permission to link the compiled version of this file into
|
||||
combinations with other programs, and to distribute those
|
||||
combinations without any restriction coming from the use of this
|
||||
file. (The Lesser General Public License restrictions do apply in
|
||||
other respects; for example, they cover modification of the file,
|
||||
and distribution when not linked into a combine executable.)
|
||||
|
||||
This file is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with GCC; see the file COPYING.LIB. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#include "config/soft-fp/soft-fp.h"
|
||||
#include "config/soft-fp/double.h"
|
||||
|
||||
CMPtype __c6xabi_led(DFtype a, DFtype b)
|
||||
{
|
||||
FP_DECL_EX;
|
||||
FP_DECL_D(A); FP_DECL_D(B);
|
||||
CMPtype r;
|
||||
|
||||
FP_UNPACK_RAW_D(A, a);
|
||||
FP_UNPACK_RAW_D(B, b);
|
||||
FP_CMP_D(r, A, B, 2);
|
||||
if (r == 2 && (FP_ISSIGNAN_D(A) || FP_ISSIGNAN_D(B)))
|
||||
FP_SET_EXCEPTION(FP_EX_INVALID);
|
||||
FP_HANDLE_EXCEPTIONS;
|
||||
|
||||
return r <= 0;
|
||||
}
|
||||
47
gcc/config/c6x/lef.c
Normal file
47
gcc/config/c6x/lef.c
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/* Software floating-point emulation.
|
||||
Return 1 iff a <= b, 0 otherwise.
|
||||
Copyright (C) 1997,1999,2006,2007,2011 Free Software Foundation, Inc.
|
||||
Contributed by Richard Henderson (rth@cygnus.com) and
|
||||
Jakub Jelinek (jj@ultra.linux.cz).
|
||||
|
||||
This file is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
In addition to the permissions in the GNU Lesser General Public
|
||||
License, the Free Software Foundation gives you unlimited
|
||||
permission to link the compiled version of this file into
|
||||
combinations with other programs, and to distribute those
|
||||
combinations without any restriction coming from the use of this
|
||||
file. (The Lesser General Public License restrictions do apply in
|
||||
other respects; for example, they cover modification of the file,
|
||||
and distribution when not linked into a combine executable.)
|
||||
|
||||
This file is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with GCC; see the file COPYING.LIB. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#include "config/soft-fp/soft-fp.h"
|
||||
#include "config/soft-fp/single.h"
|
||||
|
||||
CMPtype __c6xabi_lef(SFtype a, SFtype b)
|
||||
{
|
||||
FP_DECL_EX;
|
||||
FP_DECL_S(A); FP_DECL_S(B);
|
||||
CMPtype r;
|
||||
|
||||
FP_UNPACK_RAW_S(A, a);
|
||||
FP_UNPACK_RAW_S(B, b);
|
||||
FP_CMP_S(r, A, B, 2);
|
||||
if (r == 2 && (FP_ISSIGNAN_S(A) || FP_ISSIGNAN_S(B)))
|
||||
FP_SET_EXCEPTION(FP_EX_INVALID);
|
||||
FP_HANDLE_EXCEPTIONS;
|
||||
|
||||
return r <= 0;
|
||||
}
|
||||
438
gcc/config/c6x/lib1funcs.asm
Normal file
438
gcc/config/c6x/lib1funcs.asm
Normal file
|
|
@ -0,0 +1,438 @@
|
|||
/* Copyright 2010, 2011 Free Software Foundation, Inc.
|
||||
Contributed by Bernd Schmidt <bernds@codesourcery.com>.
|
||||
|
||||
This file is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published by the
|
||||
Free Software Foundation; either version 3, or (at your option) any
|
||||
later version.
|
||||
|
||||
This file is distributed in the hope that it will be useful, but
|
||||
WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
General Public License for more details.
|
||||
|
||||
Under Section 7 of GPL version 3, you are granted additional
|
||||
permissions described in the GCC Runtime Library Exception, version
|
||||
3.1, as published by the Free Software Foundation.
|
||||
|
||||
You should have received a copy of the GNU General Public License and
|
||||
a copy of the GCC Runtime Library Exception along with this program;
|
||||
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
;; ABI considerations for the divide functions
|
||||
;; The following registers are call-used:
|
||||
;; __c6xabi_divi A0,A1,A2,A4,A6,B0,B1,B2,B4,B5
|
||||
;; __c6xabi_divu A0,A1,A2,A4,A6,B0,B1,B2,B4
|
||||
;; __c6xabi_remi A1,A2,A4,A5,A6,B0,B1,B2,B4
|
||||
;; __c6xabi_remu A1,A4,A5,A7,B0,B1,B2,B4
|
||||
;;
|
||||
;; In our implementation, divu and remu are leaf functions,
|
||||
;; while both divi and remi call into divu.
|
||||
;; A0 is not clobbered by any of the functions.
|
||||
;; divu does not clobber B2 either, which is taken advantage of
|
||||
;; in remi.
|
||||
;; divi uses B5 to hold the original return address during
|
||||
;; the call to divu.
|
||||
;; remi uses B2 and A5 to hold the input values during the
|
||||
;; call to divu. It stores B3 in on the stack.
|
||||
|
||||
#ifdef L_divsi3
|
||||
.text
|
||||
.align 2
|
||||
.global __c6xabi_divi
|
||||
.hidden __c6xabi_divi
|
||||
.type __c6xabi_divi, STT_FUNC
|
||||
|
||||
__c6xabi_divi:
|
||||
call .s2 __c6xabi_divu
|
||||
|| mv .d2 B3, B5
|
||||
|| cmpgt .l1 0, A4, A1
|
||||
|| cmpgt .l2 0, B4, B1
|
||||
|
||||
[A1] neg .l1 A4, A4
|
||||
|| [B1] neg .l2 B4, B4
|
||||
|| xor .s1x A1, B1, A1
|
||||
|
||||
#ifdef _TMS320C6400
|
||||
[A1] addkpc .s2 1f, B3, 4
|
||||
#else
|
||||
[A1] mvkl .s2 1f, B3
|
||||
[A1] mvkh .s2 1f, B3
|
||||
nop 2
|
||||
#endif
|
||||
1:
|
||||
neg .l1 A4, A4
|
||||
|| mv .l2 B3,B5
|
||||
|| ret .s2 B5
|
||||
nop 5
|
||||
#endif
|
||||
|
||||
#if defined L_modsi3 || defined L_divmodsi4
|
||||
.align 2
|
||||
#ifdef L_modsi3
|
||||
#define MOD_OUTPUT_REG A4
|
||||
.global __c6xabi_remi
|
||||
.hidden __c6xabi_remi
|
||||
.type __c6xabi_remi, STT_FUNC
|
||||
#else
|
||||
#define MOD_OUTPUT_REG A5
|
||||
.global __c6xabi_divremi
|
||||
.hidden __c6xabi_divremi
|
||||
.type __c6xabi_divremi, STT_FUNC
|
||||
__c6xabi_divremi:
|
||||
#endif
|
||||
|
||||
__c6xabi_remi:
|
||||
stw .d2t2 B3, *B15--[2]
|
||||
|| cmpgt .l1 0, A4, A1
|
||||
|| cmpgt .l2 0, B4, B2
|
||||
|| mv .s1 A4, A5
|
||||
|| call .s2 __c6xabi_divu
|
||||
|
||||
[A1] neg .l1 A4, A4
|
||||
|| [B2] neg .l2 B4, B4
|
||||
|| xor .s2x B2, A1, B0
|
||||
|| mv .d2 B4, B2
|
||||
|
||||
#ifdef _TMS320C6400
|
||||
[B0] addkpc .s2 1f, B3, 1
|
||||
[!B0] addkpc .s2 2f, B3, 1
|
||||
nop 2
|
||||
#else
|
||||
[B0] mvkl .s2 1f,B3
|
||||
[!B0] mvkl .s2 2f,B3
|
||||
|
||||
[B0] mvkh .s2 1f,B3
|
||||
[!B0] mvkh .s2 2f,B3
|
||||
#endif
|
||||
1:
|
||||
neg .l1 A4, A4
|
||||
2:
|
||||
ldw .d2t2 *++B15[2], B3
|
||||
|
||||
#ifdef _TMS320C6400_PLUS
|
||||
mpy32 .m1x A4, B2, A6
|
||||
nop 3
|
||||
ret .s2 B3
|
||||
sub .l1 A5, A6, MOD_OUTPUT_REG
|
||||
nop 4
|
||||
#else
|
||||
mpyu .m1x A4, B2, A1
|
||||
nop 1
|
||||
mpylhu .m1x A4, B2, A6
|
||||
|| mpylhu .m2x B2, A4, B2
|
||||
nop 1
|
||||
add .l1x A6, B2, A6
|
||||
|| ret .s2 B3
|
||||
shl .s1 A6, 16, A6
|
||||
add .d1 A6, A1, A6
|
||||
sub .l1 A5, A6, MOD_OUTPUT_REG
|
||||
nop 2
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#if defined L_udivsi3 || defined L_udivmodsi4
|
||||
.align 2
|
||||
#ifdef L_udivsi3
|
||||
.global __c6xabi_divu
|
||||
.hidden __c6xabi_divu
|
||||
.type __c6xabi_divu, STT_FUNC
|
||||
__c6xabi_divu:
|
||||
#else
|
||||
.global __c6xabi_divremu
|
||||
.hidden __c6xabi_divremu
|
||||
.type __c6xabi_divremu, STT_FUNC
|
||||
__c6xabi_divremu:
|
||||
#endif
|
||||
;; We use a series of up to 31 subc instructions. First, we find
|
||||
;; out how many leading zero bits there are in the divisor. This
|
||||
;; gives us both a shift count for aligning (shifting) the divisor
|
||||
;; to the, and the number of times we have to execute subc.
|
||||
|
||||
;; At the end, we have both the remainder and most of the quotient
|
||||
;; in A4. The top bit of the quotient is computed first and is
|
||||
;; placed in A2.
|
||||
|
||||
;; Return immediately if the dividend is zero. Setting B4 to 1
|
||||
;; is a trick to allow us to leave the following insns in the jump
|
||||
;; delay slot without affecting the result.
|
||||
mv .s2x A4, B1
|
||||
|
||||
#ifndef _TMS320C6400
|
||||
[!b1] mvk .s2 1, B4
|
||||
#endif
|
||||
[b1] lmbd .l2 1, B4, B1
|
||||
||[!b1] b .s2 B3 ; RETURN A
|
||||
#ifdef _TMS320C6400
|
||||
||[!b1] mvk .d2 1, B4
|
||||
#endif
|
||||
#ifdef L_udivmodsi4
|
||||
||[!b1] zero .s1 A5
|
||||
#endif
|
||||
mv .l1x B1, A6
|
||||
|| shl .s2 B4, B1, B4
|
||||
|
||||
;; The loop performs a maximum of 28 steps, so we do the
|
||||
;; first 3 here.
|
||||
cmpltu .l1x A4, B4, A2
|
||||
[!A2] sub .l1x A4, B4, A4
|
||||
|| shru .s2 B4, 1, B4
|
||||
|| xor .s1 1, A2, A2
|
||||
|
||||
shl .s1 A2, 31, A2
|
||||
|| [b1] subc .l1x A4,B4,A4
|
||||
|| [b1] add .s2 -1, B1, B1
|
||||
[b1] subc .l1x A4,B4,A4
|
||||
|| [b1] add .s2 -1, B1, B1
|
||||
|
||||
;; RETURN A may happen here (note: must happen before the next branch)
|
||||
0:
|
||||
cmpgt .l2 B1, 7, B0
|
||||
|| [b1] subc .l1x A4,B4,A4
|
||||
|| [b1] add .s2 -1, B1, B1
|
||||
[b1] subc .l1x A4,B4,A4
|
||||
|| [b1] add .s2 -1, B1, B1
|
||||
|| [b0] b .s1 0b
|
||||
[b1] subc .l1x A4,B4,A4
|
||||
|| [b1] add .s2 -1, B1, B1
|
||||
[b1] subc .l1x A4,B4,A4
|
||||
|| [b1] add .s2 -1, B1, B1
|
||||
[b1] subc .l1x A4,B4,A4
|
||||
|| [b1] add .s2 -1, B1, B1
|
||||
[b1] subc .l1x A4,B4,A4
|
||||
|| [b1] add .s2 -1, B1, B1
|
||||
[b1] subc .l1x A4,B4,A4
|
||||
|| [b1] add .s2 -1, B1, B1
|
||||
;; loop backwards branch happens here
|
||||
|
||||
ret .s2 B3
|
||||
|| mvk .s1 32, A1
|
||||
sub .l1 A1, A6, A6
|
||||
#ifdef L_udivmodsi4
|
||||
|| extu .s1 A4, A6, A5
|
||||
#endif
|
||||
shl .s1 A4, A6, A4
|
||||
shru .s1 A4, 1, A4
|
||||
|| sub .l1 A6, 1, A6
|
||||
or .l1 A2, A4, A4
|
||||
shru .s1 A4, A6, A4
|
||||
nop
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef L_umodsi3
|
||||
.align 2
|
||||
.global __c6xabi_remu
|
||||
.hidden __c6xabi_remu
|
||||
.type __c6xabi_remu, STT_FUNC
|
||||
__c6xabi_remu:
|
||||
;; The ABI seems designed to prevent these functions calling each other,
|
||||
;; so we duplicate most of the divsi3 code here.
|
||||
mv .s2x A4, B1
|
||||
#ifndef _TMS320C6400
|
||||
[!b1] mvk .s2 1, B4
|
||||
#endif
|
||||
lmbd .l2 1, B4, B1
|
||||
||[!b1] b .s2 B3 ; RETURN A
|
||||
#ifdef _TMS320C6400
|
||||
||[!b1] mvk .d2 1, B4
|
||||
#endif
|
||||
|
||||
mv .l1x B1, A7
|
||||
|| shl .s2 B4, B1, B4
|
||||
|
||||
cmpltu .l1x A4, B4, A1
|
||||
[!a1] sub .l1x A4, B4, A4
|
||||
shru .s2 B4, 1, B4
|
||||
|
||||
0:
|
||||
cmpgt .l2 B1, 7, B0
|
||||
|| [b1] subc .l1x A4,B4,A4
|
||||
|| [b1] add .s2 -1, B1, B1
|
||||
;; RETURN A may happen here (note: must happen before the next branch)
|
||||
[b1] subc .l1x A4,B4,A4
|
||||
|| [b1] add .s2 -1, B1, B1
|
||||
|| [b0] b .s1 0b
|
||||
[b1] subc .l1x A4,B4,A4
|
||||
|| [b1] add .s2 -1, B1, B1
|
||||
[b1] subc .l1x A4,B4,A4
|
||||
|| [b1] add .s2 -1, B1, B1
|
||||
[b1] subc .l1x A4,B4,A4
|
||||
|| [b1] add .s2 -1, B1, B1
|
||||
[b1] subc .l1x A4,B4,A4
|
||||
|| [b1] add .s2 -1, B1, B1
|
||||
[b1] subc .l1x A4,B4,A4
|
||||
|| [b1] add .s2 -1, B1, B1
|
||||
;; loop backwards branch happens here
|
||||
|
||||
ret .s2 B3
|
||||
[b1] subc .l1x A4,B4,A4
|
||||
|| [b1] add .s2 -1, B1, B1
|
||||
[b1] subc .l1x A4,B4,A4
|
||||
|
||||
extu .s1 A4, A7, A4
|
||||
nop 2
|
||||
#endif
|
||||
|
||||
#if defined L_strasgi_64plus && defined _TMS320C6400_PLUS
|
||||
|
||||
.align 2
|
||||
.global __c6xabi_strasgi_64plus
|
||||
.hidden __c6xabi_strasgi_64plus
|
||||
.type __c6xabi_strasgi_64plus, STT_FUNC
|
||||
__c6xabi_strasgi_64plus:
|
||||
shru .s2x a6, 2, b31
|
||||
|| mv .s1 a4, a30
|
||||
|| mv .d2 b4, b30
|
||||
|
||||
add .s2 -4, b31, b31
|
||||
|
||||
sploopd 1
|
||||
|| mvc .s2 b31, ilc
|
||||
ldw .d2t2 *b30++, b31
|
||||
nop 4
|
||||
mv .s1x b31,a31
|
||||
spkernel 6, 0
|
||||
|| stw .d1t1 a31, *a30++
|
||||
|
||||
ret .s2 b3
|
||||
nop 5
|
||||
#endif
|
||||
|
||||
#ifdef L_strasgi
|
||||
.global __c6xabi_strasgi
|
||||
.type __c6xabi_strasgi, STT_FUNC
|
||||
__c6xabi_strasgi:
|
||||
;; This is essentially memcpy, with alignment known to be at least
|
||||
;; 4, and the size a multiple of 4 greater than or equal to 28.
|
||||
ldw .d2t1 *B4++, A0
|
||||
|| mvk .s2 16, B1
|
||||
ldw .d2t1 *B4++, A1
|
||||
|| mvk .s2 20, B2
|
||||
|| sub .d1 A6, 24, A6
|
||||
ldw .d2t1 *B4++, A5
|
||||
ldw .d2t1 *B4++, A7
|
||||
|| mv .l2x A6, B7
|
||||
ldw .d2t1 *B4++, A8
|
||||
ldw .d2t1 *B4++, A9
|
||||
|| mv .s2x A0, B5
|
||||
|| cmpltu .l2 B2, B7, B0
|
||||
|
||||
0:
|
||||
stw .d1t2 B5, *A4++
|
||||
||[b0] ldw .d2t1 *B4++, A0
|
||||
|| mv .s2x A1, B5
|
||||
|| mv .l2 B7, B6
|
||||
|
||||
[b0] sub .d2 B6, 24, B7
|
||||
||[b0] b .s2 0b
|
||||
|| cmpltu .l2 B1, B6, B0
|
||||
|
||||
[b0] ldw .d2t1 *B4++, A1
|
||||
|| stw .d1t2 B5, *A4++
|
||||
|| mv .s2x A5, B5
|
||||
|| cmpltu .l2 12, B6, B0
|
||||
|
||||
[b0] ldw .d2t1 *B4++, A5
|
||||
|| stw .d1t2 B5, *A4++
|
||||
|| mv .s2x A7, B5
|
||||
|| cmpltu .l2 8, B6, B0
|
||||
|
||||
[b0] ldw .d2t1 *B4++, A7
|
||||
|| stw .d1t2 B5, *A4++
|
||||
|| mv .s2x A8, B5
|
||||
|| cmpltu .l2 4, B6, B0
|
||||
|
||||
[b0] ldw .d2t1 *B4++, A8
|
||||
|| stw .d1t2 B5, *A4++
|
||||
|| mv .s2x A9, B5
|
||||
|| cmpltu .l2 0, B6, B0
|
||||
|
||||
[b0] ldw .d2t1 *B4++, A9
|
||||
|| stw .d1t2 B5, *A4++
|
||||
|| mv .s2x A0, B5
|
||||
|| cmpltu .l2 B2, B7, B0
|
||||
|
||||
;; loop back branch happens here
|
||||
|
||||
cmpltu .l2 B1, B6, B0
|
||||
|| ret .s2 b3
|
||||
|
||||
[b0] stw .d1t1 A1, *A4++
|
||||
|| cmpltu .l2 12, B6, B0
|
||||
[b0] stw .d1t1 A5, *A4++
|
||||
|| cmpltu .l2 8, B6, B0
|
||||
[b0] stw .d1t1 A7, *A4++
|
||||
|| cmpltu .l2 4, B6, B0
|
||||
[b0] stw .d1t1 A8, *A4++
|
||||
|| cmpltu .l2 0, B6, B0
|
||||
[b0] stw .d1t1 A9, *A4++
|
||||
|
||||
;; return happens here
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef _TMS320C6400_PLUS
|
||||
#ifdef L_push_rts
|
||||
.align 2
|
||||
.global __c6xabi_push_rts
|
||||
.hidden __c6xabi_push_rts
|
||||
.type __c6xabi_push_rts, STT_FUNC
|
||||
__c6xabi_push_rts:
|
||||
stw .d2t2 B14, *B15--[2]
|
||||
stdw .d2t1 A15:A14, *B15--
|
||||
|| b .s2x A3
|
||||
stdw .d2t2 B13:B12, *B15--
|
||||
stdw .d2t1 A13:A12, *B15--
|
||||
stdw .d2t2 B11:B10, *B15--
|
||||
stdw .d2t1 A11:A10, *B15--
|
||||
stdw .d2t2 B3:B2, *B15--
|
||||
#endif
|
||||
|
||||
#ifdef L_pop_rts
|
||||
.align 2
|
||||
.global __c6xabi_pop_rts
|
||||
.hidden __c6xabi_pop_rts
|
||||
.type __c6xabi_pop_rts, STT_FUNC
|
||||
__c6xabi_pop_rts:
|
||||
lddw .d2t2 *++B15, B3:B2
|
||||
lddw .d2t1 *++B15, A11:A10
|
||||
lddw .d2t2 *++B15, B11:B10
|
||||
lddw .d2t1 *++B15, A13:A12
|
||||
lddw .d2t2 *++B15, B13:B12
|
||||
lddw .d2t1 *++B15, A15:A14
|
||||
|| b .s2 B3
|
||||
ldw .d2t2 *++B15[2], B14
|
||||
nop 4
|
||||
#endif
|
||||
|
||||
#ifdef L_call_stub
|
||||
.align 2
|
||||
.global __c6xabi_call_stub
|
||||
.type __c6xabi_call_stub, STT_FUNC
|
||||
__c6xabi_call_stub:
|
||||
stw .d2t1 A2, *B15--[2]
|
||||
stdw .d2t1 A7:A6, *B15--
|
||||
|| call .s2 B31
|
||||
stdw .d2t1 A1:A0, *B15--
|
||||
stdw .d2t2 B7:B6, *B15--
|
||||
stdw .d2t2 B5:B4, *B15--
|
||||
stdw .d2t2 B1:B0, *B15--
|
||||
stdw .d2t2 B3:B2, *B15--
|
||||
|| addkpc .s2 1f, B3, 0
|
||||
1:
|
||||
lddw .d2t2 *++B15, B3:B2
|
||||
lddw .d2t2 *++B15, B1:B0
|
||||
lddw .d2t2 *++B15, B5:B4
|
||||
lddw .d2t2 *++B15, B7:B6
|
||||
lddw .d2t1 *++B15, A1:A0
|
||||
lddw .d2t1 *++B15, A7:A6
|
||||
|| b .s2 B3
|
||||
ldw .d2t1 *++B15[2], A2
|
||||
nop 4
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
103
gcc/config/c6x/libgcc-c6xeabi.ver
Normal file
103
gcc/config/c6x/libgcc-c6xeabi.ver
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
# Copyright (C) 2011 Free Software Foundation, Inc.
|
||||
#
|
||||
# This file is part of GCC.
|
||||
#
|
||||
# GCC is free software; you can redistribute it and/or modify
|
||||
# it under the terms of the GNU General Public License as published by
|
||||
# the Free Software Foundation; either version 3, or (at your option)
|
||||
# any later version.
|
||||
#
|
||||
# GCC is distributed in the hope that it will be useful,
|
||||
# but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
# GNU General Public License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with GCC; see the file COPYING3. If not see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
|
||||
GCC_4.7.0 {
|
||||
__c6xabi_strasgi
|
||||
__c6xabi_call_stub
|
||||
__c6xabi_mpyll
|
||||
__c6xabi_negll
|
||||
__c6xabi_llshru
|
||||
__c6xabi_llshl
|
||||
__c6xabi_llshr
|
||||
__c6xabi_fixfu
|
||||
__c6xabi_fixdu
|
||||
__c6xabi_fixflli
|
||||
__c6xabi_fixdlli
|
||||
__c6xabi_fixfull
|
||||
__c6xabi_fixdull
|
||||
__c6xabi_fltllif
|
||||
__c6xabi_fltllid
|
||||
__c6xabi_fltullf
|
||||
__c6xabi_fltulld
|
||||
__c6xabi_divlli
|
||||
__c6xabi_remlli
|
||||
__c6xabi_divull
|
||||
__c6xabi_remull
|
||||
__c6xabi_divremull
|
||||
__c6xabi_gef
|
||||
__c6xabi_gtf
|
||||
__c6xabi_lef
|
||||
__c6xabi_ltf
|
||||
__c6xabi_eqf
|
||||
__c6xabi_ged
|
||||
__c6xabi_gtd
|
||||
__c6xabi_led
|
||||
__c6xabi_ltd
|
||||
__c6xabi_eqd
|
||||
__c6xabi_addf
|
||||
__c6xabi_divf
|
||||
__c6xabi_neqf
|
||||
__c6xabi_cmpf
|
||||
__c6xabi_mpyf
|
||||
__c6xabi_negf
|
||||
__c6xabi_subf
|
||||
__c6xabi_unordf
|
||||
__c6xabi_fixfi
|
||||
__c6xabi_fltif
|
||||
__c6xabi_fltuf
|
||||
__c6xabi_addd
|
||||
__c6xabi_divd
|
||||
__c6xabi_neqd
|
||||
__c6xabi_cmpd
|
||||
__c6xabi_mpyd
|
||||
__c6xabi_negd
|
||||
__c6xabi_subd
|
||||
__c6xabi_unordd
|
||||
__c6xabi_fixdi
|
||||
__c6xabi_fltid
|
||||
__c6xabi_fltud
|
||||
__c6xabi_cvtfd
|
||||
__c6xabi_cvtdf
|
||||
__c6xabi_mulcf
|
||||
__c6xabi_mulcd
|
||||
__c6xabi_divcf
|
||||
__c6xabi_divcd
|
||||
|
||||
__gnu_ltsf2
|
||||
__gnu_ltdf2
|
||||
__gnu_gesf2
|
||||
__gnu_gedf2
|
||||
__gnu_gtsf2
|
||||
__gnu_gtdf2
|
||||
__gnu_eqsf2
|
||||
__gnu_eqdf2
|
||||
|
||||
# Exception-Handling
|
||||
_Unwind_Complete
|
||||
_Unwind_VRS_Get
|
||||
_Unwind_VRS_Set
|
||||
_Unwind_VRS_Pop
|
||||
__c6xabi_unwind_cpp_pr0
|
||||
__c6xabi_unwind_cpp_pr1
|
||||
__c6xabi_unwind_cpp_pr2
|
||||
__c6xabi_unwind_cpp_pr3
|
||||
__c6xabi_unwind_cpp_pr4
|
||||
# The libstdc++ exception-handling personality routine uses this
|
||||
# GNU-specific entry point.
|
||||
__gnu_unwind_frame
|
||||
}
|
||||
47
gcc/config/c6x/ltd.c
Normal file
47
gcc/config/c6x/ltd.c
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/* Software floating-point emulation.
|
||||
Return 1 iff a < b, 0 otherwise.
|
||||
Copyright (C) 1997,1999,2006,2007,2011 Free Software Foundation, Inc.
|
||||
Contributed by Richard Henderson (rth@cygnus.com) and
|
||||
Jakub Jelinek (jj@ultra.linux.cz).
|
||||
|
||||
This file is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
In addition to the permissions in the GNU Lesser General Public
|
||||
License, the Free Software Foundation gives you unlimited
|
||||
permission to link the compiled version of this file into
|
||||
combinations with other programs, and to distribute those
|
||||
combinations without any restriction coming from the use of this
|
||||
file. (The Lesser General Public License restrictions do apply in
|
||||
other respects; for example, they cover modification of the file,
|
||||
and distribution when not linked into a combine executable.)
|
||||
|
||||
This file is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with GCC; see the file COPYING.LIB. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#include "config/soft-fp/soft-fp.h"
|
||||
#include "config/soft-fp/double.h"
|
||||
|
||||
CMPtype __c6xabi_ltd(DFtype a, DFtype b)
|
||||
{
|
||||
FP_DECL_EX;
|
||||
FP_DECL_D(A); FP_DECL_D(B);
|
||||
CMPtype r;
|
||||
|
||||
FP_UNPACK_RAW_D(A, a);
|
||||
FP_UNPACK_RAW_D(B, b);
|
||||
FP_CMP_D(r, A, B, 2);
|
||||
if (r == 2 && (FP_ISSIGNAN_D(A) || FP_ISSIGNAN_D(B)))
|
||||
FP_SET_EXCEPTION(FP_EX_INVALID);
|
||||
FP_HANDLE_EXCEPTIONS;
|
||||
|
||||
return r < 0;
|
||||
}
|
||||
47
gcc/config/c6x/ltf.c
Normal file
47
gcc/config/c6x/ltf.c
Normal file
|
|
@ -0,0 +1,47 @@
|
|||
/* Software floating-point emulation.
|
||||
Return 1 iff a < b, 0 otherwise.
|
||||
Copyright (C) 1997,1999,2006,2007,2011 Free Software Foundation, Inc.
|
||||
Contributed by Richard Henderson (rth@cygnus.com) and
|
||||
Jakub Jelinek (jj@ultra.linux.cz).
|
||||
|
||||
This file is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
In addition to the permissions in the GNU Lesser General Public
|
||||
License, the Free Software Foundation gives you unlimited
|
||||
permission to link the compiled version of this file into
|
||||
combinations with other programs, and to distribute those
|
||||
combinations without any restriction coming from the use of this
|
||||
file. (The Lesser General Public License restrictions do apply in
|
||||
other respects; for example, they cover modification of the file,
|
||||
and distribution when not linked into a combine executable.)
|
||||
|
||||
This file is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with GCC; see the file COPYING.LIB. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#include "config/soft-fp/soft-fp.h"
|
||||
#include "config/soft-fp/single.h"
|
||||
|
||||
CMPtype __c6xabi_ltf(SFtype a, SFtype b)
|
||||
{
|
||||
FP_DECL_EX;
|
||||
FP_DECL_S(A); FP_DECL_S(B);
|
||||
CMPtype r;
|
||||
|
||||
FP_UNPACK_RAW_S(A, a);
|
||||
FP_UNPACK_RAW_S(B, b);
|
||||
FP_CMP_S(r, A, B, 2);
|
||||
if (r == 2 && (FP_ISSIGNAN_S(A) || FP_ISSIGNAN_S(B)))
|
||||
FP_SET_EXCEPTION(FP_EX_INVALID);
|
||||
FP_HANDLE_EXCEPTIONS;
|
||||
|
||||
return r < 0;
|
||||
}
|
||||
226
gcc/config/c6x/predicates.md
Normal file
226
gcc/config/c6x/predicates.md
Normal file
|
|
@ -0,0 +1,226 @@
|
|||
/* Predicates for TI C6X
|
||||
Copyright (C) 2010, 2011 Free Software Foundation, Inc.
|
||||
Contributed by Andrew Jenner <andrew@codesourcery.com>
|
||||
Contributed by Bernd Schmidt <bernds@codesourcery.com>
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
|
||||
option) any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
(define_predicate "reg_or_const_int_operand"
|
||||
(ior (match_operand 0 "register_operand")
|
||||
(match_operand 0 "const_int_operand")))
|
||||
|
||||
(define_predicate "const_vector_operand"
|
||||
(match_code "const_vector"))
|
||||
|
||||
(define_predicate "scst5_operand"
|
||||
(and (match_operand 0 "const_int_operand")
|
||||
(match_test "satisfies_constraint_Is5 (op)")))
|
||||
|
||||
(define_predicate "reg_or_ucst4_operand"
|
||||
(ior (match_operand 0 "register_operand")
|
||||
(and (match_operand 0 "const_int_operand")
|
||||
(match_test "satisfies_constraint_Iu4 (op)"))))
|
||||
|
||||
(define_predicate "reg_or_scst5_operand"
|
||||
(ior (match_operand 0 "register_operand")
|
||||
(match_operand 0 "scst5_operand")))
|
||||
|
||||
(define_predicate "reg_or_ucst5_operand"
|
||||
(ior (match_operand 0 "register_operand")
|
||||
(and (match_operand 0 "const_int_operand")
|
||||
(match_test "satisfies_constraint_Iu5 (op)"))))
|
||||
|
||||
(define_predicate "addsi_operand"
|
||||
(ior (match_operand 0 "register_operand")
|
||||
(and (match_operand 0 "const_int_operand")
|
||||
(match_test "satisfies_constraint_IsB (op)"))))
|
||||
|
||||
(define_predicate "andsi_operand"
|
||||
(ior (match_operand 0 "reg_or_scst5_operand")
|
||||
(and (match_operand 0 "const_int_operand")
|
||||
(match_test "satisfies_constraint_Jc (op)"))))
|
||||
|
||||
(define_predicate "iorsi_operand"
|
||||
(ior (match_operand 0 "reg_or_scst5_operand")
|
||||
(and (match_operand 0 "const_int_operand")
|
||||
(match_test "satisfies_constraint_Js (op)"))))
|
||||
|
||||
(define_predicate "insv_operand"
|
||||
(and (match_operand 0 "const_int_operand")
|
||||
(match_test "INTVAL (op) == 0 || INTVAL (op) == -1")))
|
||||
|
||||
(define_predicate "c6x_jump_operand"
|
||||
(match_code "label_ref,symbol_ref,reg"))
|
||||
|
||||
(define_predicate "c6x_call_operand"
|
||||
(ior (match_code "symbol_ref,reg")
|
||||
(and (match_code "subreg")
|
||||
(match_test "GET_CODE (XEXP (op, 0)) == REG")))
|
||||
{
|
||||
/* The linker transforms jumps to undefined weak symbols in a way that
|
||||
is incompatible with our code generation. */
|
||||
return (GET_CODE (op) != SYMBOL_REF
|
||||
|| (!SYMBOL_REF_WEAK (op)
|
||||
&& !c6x_long_call_p (op)));
|
||||
})
|
||||
|
||||
;; Returns 1 if OP is a symbolic operand, i.e. a symbol_ref or a label_ref,
|
||||
;; possibly with an offset.
|
||||
(define_predicate "symbolic_operand"
|
||||
(ior (match_code "symbol_ref,label_ref")
|
||||
(and (match_code "const")
|
||||
(match_test "GET_CODE (XEXP (op,0)) == PLUS
|
||||
&& (GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF
|
||||
|| GET_CODE (XEXP (XEXP (op, 0), 0)) == LABEL_REF)
|
||||
&& GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST_INT"))))
|
||||
|
||||
(define_predicate "const_int_or_symbolic_operand"
|
||||
(ior (match_operand 0 "symbolic_operand")
|
||||
(match_operand 0 "const_int_operand")))
|
||||
|
||||
;; Return nonzero iff OP is one of the integer constants 2, 4 or 8.
|
||||
(define_predicate "adda_scale_operand"
|
||||
(and (match_code "const_int")
|
||||
(match_test "INTVAL (op) == 2 || INTVAL (op) == 4
|
||||
|| ((TARGET_INSNS_64 || TARGET_INSNS_67)
|
||||
&& INTVAL (op) == 8)")))
|
||||
|
||||
;; Return nonzero iff OP is one of the integer constants 2 or 4.
|
||||
(define_predicate "suba_scale_operand"
|
||||
(and (match_code "const_int")
|
||||
(match_test "INTVAL (op) == 2 || INTVAL (op) == 4")))
|
||||
|
||||
;; True if this operator is valid for predication.
|
||||
(define_predicate "predicate_operator"
|
||||
(match_code "eq,ne"))
|
||||
|
||||
(define_predicate "c6x_comparison_operator"
|
||||
(match_code "eq,ltu,gtu,lt,gt"))
|
||||
|
||||
(define_predicate "non_c6x_comparison_operator"
|
||||
(match_code "ne,leu,geu,le,ge"))
|
||||
|
||||
;; FP Comparisons handled by c6x_expand_compare.
|
||||
(define_predicate "c6x_fp_comparison_operator"
|
||||
(ior (match_code "eq,lt,gt,le,ge")
|
||||
(and (match_test "TARGET_FP")
|
||||
(match_code "ltgt,uneq,unlt,ungt,unle,unge,ordered,unordered"))))
|
||||
|
||||
(define_predicate "c6x_any_comparison_operand"
|
||||
(match_code "eq,lt,gt,le,ge,ltu,gtu")
|
||||
{
|
||||
rtx op0 = XEXP (op, 0);
|
||||
rtx op1 = XEXP (op, 1);
|
||||
if (ltugtu_operator (op, SImode)
|
||||
&& register_operand (op0, SImode)
|
||||
&& ((TARGET_INSNS_64 && reg_or_ucst5_operand (op1, SImode))
|
||||
|| (!TARGET_INSNS_64 && reg_or_ucst4_operand (op1, SImode))))
|
||||
return true;
|
||||
if (eqltgt_operator (op, SImode)
|
||||
&& register_operand (op0, SImode)
|
||||
&& reg_or_scst5_operand (op1, SImode))
|
||||
return true;
|
||||
if (!TARGET_FP)
|
||||
return false;
|
||||
if (!eqltgt_operator (op, SFmode) && !eqltgt_operator (op, DFmode))
|
||||
return false;
|
||||
if (register_operand (op0, GET_MODE (op))
|
||||
&& register_operand (op1, GET_MODE (op)))
|
||||
return true;
|
||||
return false;
|
||||
})
|
||||
|
||||
(define_predicate "ltugtu_operator"
|
||||
(match_code "ltu,gtu"))
|
||||
|
||||
(define_predicate "eqltgt_operator"
|
||||
(match_code "eq,lt,gt"))
|
||||
|
||||
(define_predicate "eqne_operator"
|
||||
(match_code "eq,ne"))
|
||||
|
||||
(define_predicate "predicate_register"
|
||||
(and (match_code "reg")
|
||||
(ior (match_test "REGNO_REG_CLASS (REGNO (op)) == PREDICATE_A_REGS")
|
||||
(match_test "REGNO_REG_CLASS (REGNO (op)) == PREDICATE_B_REGS"))))
|
||||
|
||||
;; Allow const_ints for things like the real_mult patterns.
|
||||
(define_predicate "a_register"
|
||||
(ior (and (match_code "reg")
|
||||
(match_test "A_REGNO_P (REGNO (op))"))
|
||||
(and (match_code "const_int")
|
||||
(match_test "A_REGNO_P (INTVAL (op))"))))
|
||||
|
||||
(define_predicate "b_register"
|
||||
(ior (and (match_code "reg")
|
||||
(match_test "B_REGNO_P (REGNO (op))"))
|
||||
(and (match_code "const_int")
|
||||
(match_test "B_REGNO_P (INTVAL (op))"))))
|
||||
|
||||
(define_predicate "pic_register_operand"
|
||||
(and (match_code "reg")
|
||||
(match_test "op == pic_offset_table_rtx")))
|
||||
|
||||
;; True if OP refers to a symbol in the sdata section.
|
||||
(define_predicate "sdata_symbolic_operand"
|
||||
(match_code "symbol_ref,const")
|
||||
{
|
||||
HOST_WIDE_INT offset = 0, size = 0;
|
||||
tree t;
|
||||
|
||||
switch (GET_CODE (op))
|
||||
{
|
||||
case CONST:
|
||||
op = XEXP (op, 0);
|
||||
if (GET_CODE (op) != PLUS
|
||||
|| GET_CODE (XEXP (op, 0)) != SYMBOL_REF
|
||||
|| GET_CODE (XEXP (op, 1)) != CONST_INT)
|
||||
return false;
|
||||
offset = INTVAL (XEXP (op, 1));
|
||||
op = XEXP (op, 0);
|
||||
/* FALLTHRU */
|
||||
|
||||
case SYMBOL_REF:
|
||||
/* For shared libraries, only allow symbols we know are local.
|
||||
For executables, the linker knows to create copy relocs if
|
||||
necessary so we can use DP-relative addressing for all small
|
||||
objects. */
|
||||
if ((c6x_initial_flag_pic && !SYMBOL_REF_LOCAL_P (op))
|
||||
|| !SYMBOL_REF_SMALL_P (op))
|
||||
return false;
|
||||
|
||||
/* Note that in addition to DECLs, we can get various forms
|
||||
of constants here. */
|
||||
t = SYMBOL_REF_DECL (op);
|
||||
if (DECL_P (t))
|
||||
t = DECL_SIZE_UNIT (t);
|
||||
else
|
||||
t = TYPE_SIZE_UNIT (TREE_TYPE (t));
|
||||
if (t && host_integerp (t, 0))
|
||||
{
|
||||
size = tree_low_cst (t, 0);
|
||||
if (size < 0)
|
||||
size = 0;
|
||||
}
|
||||
|
||||
/* Don't allow addressing outside the object. */
|
||||
return (offset >= 0 && offset <= size);
|
||||
|
||||
default:
|
||||
gcc_unreachable ();
|
||||
}
|
||||
})
|
||||
120
gcc/config/c6x/sfp-machine.h
Normal file
120
gcc/config/c6x/sfp-machine.h
Normal file
|
|
@ -0,0 +1,120 @@
|
|||
/* Soft-FP definitions for TI C6X.
|
||||
Copyright (C) 2010, 2011 Free Software Foundation, Inc.
|
||||
|
||||
This files is free software; you can redistribute it and/or
|
||||
modify it under the terms of the GNU Lesser General Public
|
||||
License as published by the Free Software Foundation; either
|
||||
version 2.1 of the License, or (at your option) any later version.
|
||||
|
||||
In addition to the permissions in the GNU Lesser General Public
|
||||
License, the Free Software Foundation gives you unlimited
|
||||
permission to link the compiled version of this file into
|
||||
combinations with other programs, and to distribute those
|
||||
combinations without any restriction coming from the use of this
|
||||
file. (The Lesser General Public License restrictions do apply in
|
||||
other respects; for example, they cover modification of the file,
|
||||
and distribution when not linked into a combine executable.)
|
||||
|
||||
This file is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
Lesser General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU Lesser General Public
|
||||
License along with GCC; see the file COPYING.LIB. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#define _FP_W_TYPE_SIZE 32
|
||||
#define _FP_W_TYPE unsigned long
|
||||
#define _FP_WS_TYPE signed long
|
||||
#define _FP_I_TYPE long
|
||||
|
||||
#define _FP_MUL_MEAT_S(R,X,Y) \
|
||||
_FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
|
||||
#define _FP_MUL_MEAT_D(R,X,Y) \
|
||||
_FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
|
||||
#define _FP_MUL_MEAT_Q(R,X,Y) \
|
||||
_FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
|
||||
|
||||
#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_loop(S,R,X,Y)
|
||||
#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
|
||||
#define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
|
||||
|
||||
#define _FP_NANFRAC_H ((_FP_QNANBIT_H << 1) - 1)
|
||||
#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
|
||||
#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1
|
||||
#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
|
||||
#define _FP_NANSIGN_H 0
|
||||
#define _FP_NANSIGN_S 0
|
||||
#define _FP_NANSIGN_D 0
|
||||
#define _FP_NANSIGN_Q 0
|
||||
|
||||
#define _FP_KEEPNANFRACP 1
|
||||
|
||||
/* Someone please check this. */
|
||||
#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
|
||||
do { \
|
||||
if ((_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs) \
|
||||
&& !(_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs)) \
|
||||
{ \
|
||||
R##_s = Y##_s; \
|
||||
_FP_FRAC_COPY_##wc(R,Y); \
|
||||
} \
|
||||
else \
|
||||
{ \
|
||||
R##_s = X##_s; \
|
||||
_FP_FRAC_COPY_##wc(R,X); \
|
||||
} \
|
||||
R##_c = FP_CLS_NAN; \
|
||||
} while (0)
|
||||
|
||||
#define __LITTLE_ENDIAN 1234
|
||||
#define __BIG_ENDIAN 4321
|
||||
|
||||
#if defined _BIG_ENDIAN
|
||||
# define __BYTE_ORDER __BIG_ENDIAN
|
||||
#else
|
||||
# define __BYTE_ORDER __LITTLE_ENDIAN
|
||||
#endif
|
||||
|
||||
|
||||
/* Define ALIASNAME as a strong alias for NAME. */
|
||||
# define strong_alias(name, aliasname) _strong_alias(name, aliasname)
|
||||
# define _strong_alias(name, aliasname) \
|
||||
extern __typeof (name) aliasname __attribute__ ((alias (#name)));
|
||||
|
||||
/* Rename helper functions to the names specified in the C6000 ELF ABI. */
|
||||
#define __fixdfsi __c6xabi_fixdi
|
||||
#define __fixsfsi __c6xabi_fixfi
|
||||
#define __floatsidf __c6xabi_fltid
|
||||
#define __floatunsidf __c6xabi_fltud
|
||||
#define __floatsisf __c6xabi_fltif
|
||||
#define __floatunsisf __c6xabi_fltuf
|
||||
#define __truncdfsf2 __c6xabi_cvtdf
|
||||
#define __extendsfdf2 __c6xabi_cvtfd
|
||||
#define __adddf3 __c6xabi_addd
|
||||
#define __subdf3 __c6xabi_subd
|
||||
#define __muldf3 __c6xabi_mpyd
|
||||
#define __divdf3 __c6xabi_divd
|
||||
#define __negdf2 __c6xabi_negd
|
||||
#define __absdf2 __c6xabi_absd
|
||||
#define __addsf3 __c6xabi_addf
|
||||
#define __subsf3 __c6xabi_subf
|
||||
#define __mulsf3 __c6xabi_mpyf
|
||||
#define __divsf3 __c6xabi_divf
|
||||
#define __negsf2 __c6xabi_negf
|
||||
#define __abssf2 __c6xabi_absf
|
||||
#define __lesf2 __c6xabi_cmpf
|
||||
#define __ledf2 __c6xabi_cmpd
|
||||
#define __ltsf2 __gnu_ltsf2
|
||||
#define __ltdf2 __gnu_ltdf2
|
||||
#define __gesf2 __gnu_gesf2
|
||||
#define __gedf2 __gnu_gedf2
|
||||
#define __gtsf2 __gnu_gtsf2
|
||||
#define __gtdf2 __gnu_gtdf2
|
||||
#define __eqsf2 __gnu_eqsf2
|
||||
#define __eqdf2 __gnu_eqdf2
|
||||
#define __nesf2 __c6xabi_neqf
|
||||
#define __nedf2 __c6xabi_neqd
|
||||
#define __unordsf2 __c6xabi_unordf
|
||||
#define __unorddf2 __c6xabi_unordd
|
||||
270
gcc/config/c6x/sync.md
Normal file
270
gcc/config/c6x/sync.md
Normal file
|
|
@ -0,0 +1,270 @@
|
|||
;; GCC machine description for C6X synchronization instructions.
|
||||
;; Copyright (C) 2011 Free Software Foundation, Inc.
|
||||
;;
|
||||
;; This file is part of GCC.
|
||||
;;
|
||||
;; GCC is free software; you can redistribute it and/or modify
|
||||
;; it under the terms of the GNU General Public License as published by
|
||||
;; the Free Software Foundation; either version 3, or (at your option)
|
||||
;; any later version.
|
||||
;;
|
||||
;; GCC is distributed in the hope that it will be useful,
|
||||
;; but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
;; GNU General Public License for more details.
|
||||
;;
|
||||
;; You should have received a copy of the GNU General Public License
|
||||
;; along with GCC; see the file COPYING3. If not see
|
||||
;; <http://www.gnu.org/licenses/>.
|
||||
|
||||
;; C64X+ has atomic instructions, but they are not atomic on all
|
||||
;; devices and have other problems. We use normal loads and stores,
|
||||
;; and place them in overlapping branch shadows to ensure interrupts
|
||||
;; are disabled during the sequence, which guarantees atomicity on all
|
||||
;; single-core systems.
|
||||
|
||||
(define_code_iterator FETCHOP [plus minus ior xor and])
|
||||
(define_code_attr fetchop_name
|
||||
[(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")])
|
||||
(define_code_attr fetchop_pred
|
||||
[(plus "reg_or_scst5_operand") (minus "register_operand")
|
||||
(ior "reg_or_scst5_operand") (xor "reg_or_scst5_operand")
|
||||
(and "reg_or_scst5_operand")])
|
||||
(define_code_attr fetchop_constr
|
||||
[(plus "bIs5") (minus "b") (ior "bIs5") (xor "bIs5") (and "bIs5")])
|
||||
(define_code_attr fetchop_opcode
|
||||
[(plus "add") (minus "sub") (ior "or") (xor "xor") (and "and")])
|
||||
(define_code_attr fetchop_inops02
|
||||
[(plus "%2, %0") (minus "%0, %2") (ior "%2, %0") (xor "%2, %0")
|
||||
(and "%2, %0")])
|
||||
(define_code_attr fetchop_inops21
|
||||
[(plus "%1, %2") (minus "%2, %1") (ior "%1, %2") (xor "%1, %2")
|
||||
(and "%1, %2")])
|
||||
|
||||
(define_expand "sync_compare_and_swapsi"
|
||||
[(parallel
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(match_operand:SI 1 "memory_operand" ""))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:SI
|
||||
[(match_operand:SI 2 "register_operand" "")
|
||||
(match_operand:SI 3 "register_operand" "")]
|
||||
UNSPECV_CAS))
|
||||
(clobber (match_scratch:SI 4 ""))])]
|
||||
""
|
||||
{
|
||||
})
|
||||
|
||||
(define_expand "sync_<fetchop_name>si"
|
||||
[(parallel
|
||||
[(set (match_operand:SI 0 "memory_operand" "")
|
||||
(unspec:SI
|
||||
[(FETCHOP:SI (match_dup 0)
|
||||
(match_operand:SI 1 "<fetchop_pred>" ""))]
|
||||
UNSPEC_ATOMIC))
|
||||
(clobber (match_scratch:SI 2 ""))])]
|
||||
""
|
||||
{
|
||||
})
|
||||
|
||||
(define_expand "sync_old_<fetchop_name>si"
|
||||
[(parallel
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(match_operand:SI 1 "memory_operand" ""))
|
||||
(set (match_dup 1)
|
||||
(unspec:SI
|
||||
[(FETCHOP:SI (match_dup 1)
|
||||
(match_operand:SI 2 "<fetchop_pred>" ""))]
|
||||
UNSPEC_ATOMIC))
|
||||
(clobber (match_scratch:SI 3 ""))])]
|
||||
""
|
||||
{
|
||||
})
|
||||
|
||||
(define_expand "sync_new_<fetchop_name>si"
|
||||
[(parallel
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(FETCHOP:SI (match_operand:SI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "<fetchop_pred>" "")))
|
||||
(set (match_dup 1)
|
||||
(unspec:SI [(FETCHOP:SI (match_dup 1) (match_dup 2))]
|
||||
UNSPEC_ATOMIC))
|
||||
(clobber (match_scratch:SI 3 ""))])]
|
||||
""
|
||||
{
|
||||
})
|
||||
|
||||
(define_expand "sync_nandsi"
|
||||
[(parallel
|
||||
[(set (match_operand:SI 0 "memory_operand" "")
|
||||
(unspec:SI
|
||||
[(not:SI (and:SI (match_dup 0)
|
||||
(match_operand:SI 1 "reg_or_scst5_operand" "")))]
|
||||
UNSPEC_ATOMIC))
|
||||
(clobber (match_scratch:SI 2 ""))])]
|
||||
""
|
||||
{
|
||||
})
|
||||
|
||||
(define_expand "sync_old_nandsi"
|
||||
[(parallel
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(match_operand:SI 1 "memory_operand" ""))
|
||||
(set (match_dup 1)
|
||||
(unspec:SI
|
||||
[(not:SI (and:SI (match_dup 1)
|
||||
(match_operand:SI 2 "reg_or_scst5_operand" "")))]
|
||||
UNSPEC_ATOMIC))
|
||||
(clobber (match_scratch:SI 3 ""))])]
|
||||
""
|
||||
{
|
||||
})
|
||||
|
||||
(define_expand "sync_new_nandsi"
|
||||
[(parallel
|
||||
[(set (match_operand:SI 0 "register_operand" "")
|
||||
(not:SI (and:SI (match_operand:SI 1 "memory_operand" "")
|
||||
(match_operand:SI 2 "reg_or_scst5_operand" ""))))
|
||||
(set (match_dup 1)
|
||||
(unspec:SI [(not:SI (and:SI (match_dup 1) (match_dup 2)))]
|
||||
UNSPEC_ATOMIC))
|
||||
(clobber (match_scratch:SI 3 ""))])]
|
||||
""
|
||||
{
|
||||
})
|
||||
|
||||
(define_insn "*sync_compare_and_swapsi"
|
||||
[(set (match_operand:SI 0 "register_operand" "=&b")
|
||||
(match_operand:SI 1 "memory_operand" "+m"))
|
||||
(set (match_dup 1)
|
||||
(unspec_volatile:SI
|
||||
[(match_operand:SI 2 "register_operand" "B")
|
||||
(match_operand:SI 3 "register_operand" "b")]
|
||||
UNSPECV_CAS))
|
||||
(clobber (match_scratch:SI 4 "=&B"))]
|
||||
""
|
||||
"0: b .s2 1f ; 0\n\\
|
||||
|| ldw .d%U1t%U0 %1, %0\n\\
|
||||
nop 4\n\\
|
||||
|| b .s2 2f ; 1\n\\
|
||||
cmpeq .l2 %0, %2, %2 ; 5\n\\
|
||||
1: [%2] stw .d%U1t%U3 %3, %1 ; 6\n\\
|
||||
2:"
|
||||
[(set_attr "type" "atomic")])
|
||||
|
||||
(define_insn "sync_<fetchop_name>si_insn"
|
||||
[(set (match_operand:SI 0 "memory_operand" "+m")
|
||||
(unspec:SI
|
||||
[(FETCHOP:SI (match_dup 0)
|
||||
(match_operand:SI 1 "<fetchop_pred>" "<fetchop_constr>"))]
|
||||
UNSPEC_ATOMIC))
|
||||
(clobber (match_scratch:SI 2 "=&B"))]
|
||||
""
|
||||
"0: b .s2 1f ; 0\n\\
|
||||
|| ldw .d%U0t%U2 %0, %2\n\\
|
||||
nop 4\n\\
|
||||
|| b .s2 2f ; 1\n\\
|
||||
<fetchop_opcode> .l2 <fetchop_inops21>, %2 ; 5\n\\
|
||||
1: stw .d%U0t%U2 %2, %0 ; 6\n\\
|
||||
2:"
|
||||
[(set_attr "type" "atomic")])
|
||||
|
||||
(define_insn "sync_old_<fetchop_name>si_insn"
|
||||
[(set (match_operand:SI 0 "register_operand" "=&b")
|
||||
(match_operand:SI 1 "memory_operand" "+m"))
|
||||
(set (match_dup 1)
|
||||
(unspec:SI
|
||||
[(FETCHOP:SI (match_dup 1)
|
||||
(match_operand:SI 2 "<fetchop_pred>" "<fetchop_constr>"))]
|
||||
UNSPEC_ATOMIC))
|
||||
(clobber (match_scratch:SI 3 "=&B"))]
|
||||
""
|
||||
"0: b .s2 1f ; 0\n\\
|
||||
|| ldw .d%U1t%U0 %1, %0\n\\
|
||||
nop 4\n\\
|
||||
|| b .s2 2f ; 1\n\\
|
||||
<fetchop_opcode> .l2 <fetchop_inops02>, %3 ; 5\n\\
|
||||
1: stw .d%U1t%U3 %3, %1 ; 6\n\\
|
||||
2:"
|
||||
[(set_attr "type" "atomic")])
|
||||
|
||||
(define_insn "sync_new_<fetchop_name>si_insn"
|
||||
[(set (match_operand:SI 0 "register_operand" "=&b")
|
||||
(FETCHOP:SI (match_operand:SI 1 "memory_operand" "+m")
|
||||
(match_operand:SI 2 "<fetchop_pred>" "<fetchop_constr>")))
|
||||
(set (match_dup 1)
|
||||
(unspec:SI
|
||||
[(FETCHOP:SI (match_dup 1)
|
||||
(match_dup 2))]
|
||||
UNSPEC_ATOMIC))
|
||||
(clobber (match_scratch:SI 3 "=&B"))]
|
||||
""
|
||||
"0: b .s2 1f ; 0\n\\
|
||||
|| ldw .d%U1t%U0 %1, %0\n\\
|
||||
nop 4\n\\
|
||||
|| b .s2 2f ; 1\n\\
|
||||
<fetchop_opcode> .l2 <fetchop_inops02>, %0 ; 5\n\\
|
||||
1: stw .d%U1t%U0 %0, %1 ; 6\n\\
|
||||
2:"
|
||||
[(set_attr "type" "atomic")])
|
||||
|
||||
(define_insn "sync_nandsi_insn"
|
||||
[(set (match_operand:SI 0 "memory_operand" "+m")
|
||||
(unspec:SI
|
||||
[(not:SI (and:SI (match_dup 0)
|
||||
(match_operand:SI 1 "reg_or_scst5_operand" "bIs5")))]
|
||||
UNSPEC_ATOMIC))
|
||||
(clobber (match_scratch:SI 2 "=&B"))]
|
||||
""
|
||||
"0: b .s2 1f ; 0\n\\
|
||||
|| ldw .d%U0t%U2 %0, %2\n\\
|
||||
nop 1\n\\
|
||||
nop 3\n\\
|
||||
|| b .s2 2f ; 2\n\\
|
||||
and .l2 %1, %2, %2 ; 5\n\\
|
||||
1: not .l2 %2, %2 ; 6\n\\
|
||||
stw .d%U0t%U2 %2, %0 ; 7\n\\
|
||||
2:"
|
||||
[(set_attr "type" "atomic")])
|
||||
|
||||
(define_insn "sync_old_nandsi_insn"
|
||||
[(set (match_operand:SI 0 "register_operand" "=&b")
|
||||
(match_operand:SI 1 "memory_operand" "+m"))
|
||||
(set (match_dup 1)
|
||||
(unspec:SI
|
||||
[(not:SI (and:SI (match_dup 1)
|
||||
(match_operand:SI 2 "reg_or_scst5_operand" "bIs5")))]
|
||||
UNSPEC_ATOMIC))
|
||||
(clobber (match_scratch:SI 3 "=&B"))]
|
||||
""
|
||||
"0: b .s2 1f ; 0\n\\
|
||||
|| ldw .d%U1t%U0 %1, %0\n\\
|
||||
nop 1\n\\
|
||||
nop 3\n\\
|
||||
|| b .s2 2f ; 2\n\\
|
||||
and .l2 %2, %0, %3 ; 5\n\\
|
||||
1: not .l2 %3, %3 ; 6\n\\
|
||||
stw .d%U1t%U3 %3, %1 ; 7\n\\
|
||||
2:"
|
||||
[(set_attr "type" "atomic")])
|
||||
|
||||
(define_insn "sync_new_nandsi_insn"
|
||||
[(set (match_operand:SI 0 "register_operand" "=&b")
|
||||
(not:SI (and:SI (match_operand:SI 1 "memory_operand" "+m")
|
||||
(match_operand:SI 2 "reg_or_scst5_operand" "bIs5"))))
|
||||
(set (match_dup 1)
|
||||
(unspec:SI
|
||||
[(not:SI (and:SI (match_dup 1) (match_dup 2)))]
|
||||
UNSPEC_ATOMIC))
|
||||
(clobber (match_scratch:SI 3 "=&B"))]
|
||||
""
|
||||
"0: b .s2 1f ; 0\n\\
|
||||
|| ldw .d%U1t%U0 %1, %0\n\\
|
||||
nop 1\n\\
|
||||
nop 3\n\\
|
||||
|| b .s2 2f ; 2\n\\
|
||||
and .l2 %2, %0, %0 ; 5\n\\
|
||||
1: not .l2 %0, %0 ; 6\n\\
|
||||
stw .d%U1t%U0 %0, %1 ; 7\n\\
|
||||
2:"
|
||||
[(set_attr "type" "atomic")])
|
||||
43
gcc/config/c6x/t-c6x
Normal file
43
gcc/config/c6x/t-c6x
Normal file
|
|
@ -0,0 +1,43 @@
|
|||
# Target Makefile Fragment for TI C6X.
|
||||
# Copyright (C) 2010, 2011
|
||||
# Free Software Foundation, Inc.
|
||||
# Contributed by CodeSourcery.
|
||||
#
|
||||
# This file is part of GCC.
|
||||
#
|
||||
# GCC is free software; you can redistribute it and/or modify it
|
||||
# under the terms of the GNU General Public License as published
|
||||
# by the Free Software Foundation; either version 3, or (at your
|
||||
# option) any later version.
|
||||
#
|
||||
# GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
# License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with GCC; see the file COPYING3. If not see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
|
||||
MD_INCLUDES= $(srcdir)/config/c6x/constraints.md \
|
||||
$(srcdir)/config/c6x/predicates.md \
|
||||
$(srcdir)/config/c6x/c6x-mult.md \
|
||||
$(srcdir)/config/c6x/c6x-sched.md
|
||||
|
||||
s-config s-conditions s-flags s-codes s-constants s-emit s-recog s-preds \
|
||||
s-opinit s-extract s-peep s-attr s-attrtab s-output: $(MD_INCLUDES)
|
||||
|
||||
$(srcdir)/config/c6x/c6x-sched.md: $(srcdir)/config/c6x/gensched.sh \
|
||||
$(srcdir)/config/c6x/c6x-sched.md.in
|
||||
$(SHELL) $(srcdir)/config/c6x/gensched.sh \
|
||||
$(srcdir)/config/c6x/c6x-sched.md.in > $@
|
||||
|
||||
$(srcdir)/config/c6x/c6x-mult.md: $(srcdir)/config/c6x/genmult.sh \
|
||||
$(srcdir)/config/c6x/c6x-mult.md.in
|
||||
$(SHELL) $(srcdir)/config/c6x/genmult.sh \
|
||||
$(srcdir)/config/c6x/c6x-mult.md.in > $@
|
||||
|
||||
$(srcdir)/config/c6x/c6x-tables.opt: $(srcdir)/config/c6x/genopt.sh \
|
||||
$(srcdir)/config/c6x/c6x-isas.def
|
||||
$(SHELL) $(srcdir)/config/c6x/genopt.sh $(srcdir)/config/c6x > \
|
||||
$(srcdir)/config/c6x/c6x-tables.opt
|
||||
66
gcc/config/c6x/t-c6x-elf
Normal file
66
gcc/config/c6x/t-c6x-elf
Normal file
|
|
@ -0,0 +1,66 @@
|
|||
# Target Makefile Fragment for TI C6X using ELF.
|
||||
# Copyright (C) 2010, 2011 Free Software Foundation, Inc.
|
||||
# Contributed by CodeSourcery.
|
||||
#
|
||||
# This file is part of GCC.
|
||||
#
|
||||
# GCC is free software; you can redistribute it and/or modify it
|
||||
# under the terms of the GNU General Public License as published
|
||||
# by the Free Software Foundation; either version 3, or (at your
|
||||
# option) any later version.
|
||||
#
|
||||
# GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
# or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
# License for more details.
|
||||
#
|
||||
# You should have received a copy of the GNU General Public License
|
||||
# along with GCC; see the file COPYING3. If not see
|
||||
# <http://www.gnu.org/licenses/>.
|
||||
|
||||
LIB1ASMSRC = c6x/lib1funcs.asm
|
||||
LIB1ASMFUNCS = _divsi3 _udivsi3 _umodsi3 _modsi3 _udivmodsi4 _divmodsi4
|
||||
LIB1ASMFUNCS += _strasgi _strasgi_64plus _clzsi2 _clzdi2 _clz
|
||||
LIB1ASMFUNCS += _push_rts _pop_rts _call_stub
|
||||
|
||||
LIB2FUNCS_EXCLUDE = _cmpdi2 _ucmpdi2 _gcc_bcmp _eprintf _clzsi _clzdi
|
||||
|
||||
LIB2FUNCS_EXTRA = $(srcdir)/config/c6x/gef.c \
|
||||
$(srcdir)/config/c6x/gtf.c \
|
||||
$(srcdir)/config/c6x/lef.c \
|
||||
$(srcdir)/config/c6x/ltf.c \
|
||||
$(srcdir)/config/c6x/eqf.c \
|
||||
$(srcdir)/config/c6x/ged.c \
|
||||
$(srcdir)/config/c6x/gtd.c \
|
||||
$(srcdir)/config/c6x/led.c \
|
||||
$(srcdir)/config/c6x/ltd.c \
|
||||
$(srcdir)/config/c6x/eqd.c
|
||||
|
||||
# Use this variant for fully testing all CPU types
|
||||
#MULTILIB_OPTIONS = mbig-endian march=c674x/march=c64x/march=c67x/march=c67x+/march=c62x
|
||||
#MULTILIB_DIRNAMES = be c674x c64x c67x c67x+ c62x
|
||||
|
||||
MULTILIB_OPTIONS = mbig-endian march=c674x
|
||||
MULTILIB_DIRNAMES = be c674x
|
||||
MULTILIB_EXCEPTIONS =
|
||||
MULTILIB_MATCHES =
|
||||
|
||||
# Assemble startup files.
|
||||
$(T)crti.o: $(srcdir)/config/c6x/crti.s $(GCC_PASSES)
|
||||
$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
|
||||
-c -o $(T)crti.o $(CRTSTUFF_T_CFLAGS) -x assembler-with-cpp \
|
||||
$(srcdir)/config/c6x/crti.s
|
||||
|
||||
$(T)crtn.o: $(srcdir)/config/c6x/crtn.s $(GCC_PASSES)
|
||||
$(GCC_FOR_TARGET) $(GCC_CFLAGS) $(MULTILIB_CFLAGS) $(INCLUDES) \
|
||||
-c -o $(T)crtn.o $(CRTSTUFF_T_CFLAGS) -x assembler-with-cpp \
|
||||
$(srcdir)/config/c6x/crtn.s
|
||||
|
||||
EXTRA_MULTILIB_PARTS = crtbegin.o crtend.o crtbeginS.o crtendS.o crti.o crtn.o
|
||||
|
||||
# Avoid failures when the user's GOT becomes too large.
|
||||
CRTSTUFF_T_CFLAGS = -msdata=none
|
||||
CRTSTUFF_T_CFLAGS_S = -msdata=none
|
||||
TARGET_LIBGCC2_CFLAGS = -msdata=none
|
||||
|
||||
SHLIB_MAPFILES += $(srcdir)/config/c6x/libgcc-c6xeabi.ver
|
||||
9
gcc/config/c6x/t-c6x-softfp
Normal file
9
gcc/config/c6x/t-c6x-softfp
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
softfp_float_modes := sf df
|
||||
softfp_int_modes := si di
|
||||
softfp_extensions := sfdf
|
||||
softfp_truncations := dfsf
|
||||
softfp_machine_header := c6x/sfp-machine.h
|
||||
softfp_exclude_libgcc2 := y
|
||||
|
||||
# softfp seems to be missing a whole bunch of prototypes.
|
||||
TARGET_LIBGCC2_CFLAGS += -Wno-missing-prototypes
|
||||
7
gcc/config/c6x/t-c6x-uclinux
Normal file
7
gcc/config/c6x/t-c6x-uclinux
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
MULTILIB_OSDIRNAMES = march.c674x=!c674x
|
||||
MULTILIB_OSDIRNAMES += mbig-endian=!be
|
||||
MULTILIB_OSDIRNAMES += mbig-endian/march.c674x=!be/c674x
|
||||
|
||||
CRTSTUFF_T_CFLAGS = -fPIC -msdata=none
|
||||
CRTSTUFF_T_CFLAGS_S = -fPIC -msdata=none
|
||||
TARGET_LIBGCC2_CFLAGS = -fPIC -msdata=none
|
||||
64
gcc/config/c6x/uclinux-elf.h
Normal file
64
gcc/config/c6x/uclinux-elf.h
Normal file
|
|
@ -0,0 +1,64 @@
|
|||
/* Definitions for TI C6X running ucLinux using ELF
|
||||
Copyright (C) 2010, 2011 Free Software Foundation, Inc.
|
||||
Contributed by Andrew Jenner <andrew@codesourcery.com>
|
||||
Contributed by Bernd Schmidt <bernds@codesourcery.com>
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
|
||||
option) any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
#undef TARGET_OS_CPP_BUILTINS
|
||||
#define TARGET_OS_CPP_BUILTINS() \
|
||||
do \
|
||||
{ \
|
||||
builtin_define ("__uClinux__"); \
|
||||
builtin_define_std ("linux"); \
|
||||
builtin_define_std ("unix"); \
|
||||
builtin_assert ("system=linux"); \
|
||||
builtin_assert ("system=unix"); \
|
||||
builtin_assert ("system=posix"); \
|
||||
} \
|
||||
while (false)
|
||||
|
||||
#undef STARTFILE_SPEC
|
||||
#define STARTFILE_SPEC \
|
||||
"%{!shared:crt1%O%s} crti%O%s %{shared|pie:crtbeginS.o%s;:crtbegin.o%s}"
|
||||
|
||||
#define UCLIBC_DYNAMIC_LINKER "/lib/ld-uClibc.so.0"
|
||||
|
||||
#undef LINK_SPEC
|
||||
#define LINK_SPEC ENDIAN_LINK_SPEC \
|
||||
"%{shared} %{fpie|fPIE:-pie} \
|
||||
%{!shared: %{!static: \
|
||||
%{rdynamic:-export-dynamic} \
|
||||
%{!dynamic-linker:-dynamic-linker " UCLIBC_DYNAMIC_LINKER "}} \
|
||||
%{static}}"
|
||||
|
||||
#undef DRIVER_SELF_SPECS
|
||||
#define DRIVER_SELF_SPECS "%{!mno-dsbt:-mdsbt}"
|
||||
|
||||
/* Clear the instruction cache from `beg' to `end'. This makes an
|
||||
inline system call to SYS_cacheflush. */
|
||||
#undef CLEAR_INSN_CACHE
|
||||
#define CLEAR_INSN_CACHE(BEG, END) \
|
||||
{ \
|
||||
register unsigned long _beg __asm ("A4") = (unsigned long) (BEG); \
|
||||
register unsigned long _end __asm ("B4") = (unsigned long) (END); \
|
||||
register unsigned long _scno __asm ("B0") = 244; \
|
||||
__asm __volatile ("swe ; sys_cache_sync" \
|
||||
: "=a" (_beg) \
|
||||
: "0" (_beg), "b" (_end), "b" (_scno)); \
|
||||
}
|
||||
|
||||
|
|
@ -806,8 +806,8 @@ Tobias Schl@"uter for work on GNU Fortran.
|
|||
|
||||
@item
|
||||
Bernd Schmidt for various code generation improvements and major
|
||||
work in the reload pass as well a serving as release manager for
|
||||
GCC 2.95.3.
|
||||
work in the reload pass, serving as release manager for
|
||||
GCC 2.95.3, and work on the Blackfin and C6X ports.
|
||||
|
||||
@item
|
||||
Peter Schmid for constant testing of libstdc++---especially application
|
||||
|
|
|
|||
|
|
@ -7975,6 +7975,7 @@ instructions, but allow the compiler to schedule those calls.
|
|||
* RX Built-in Functions::
|
||||
* SPARC VIS Built-in Functions::
|
||||
* SPU Built-in Functions::
|
||||
* TI C6X Built-in Functions::
|
||||
@end menu
|
||||
|
||||
@node Alpha Built-in Functions
|
||||
|
|
@ -12793,6 +12794,45 @@ specification is supported. Internally, GCC uses built-in functions to
|
|||
implement the required functionality, but these are not supported and
|
||||
are subject to change without notice.
|
||||
|
||||
@node TI C6X Built-in Functions
|
||||
@subsection TI C6X Built-in Functions
|
||||
|
||||
GCC provides intrinsics to access certain instructions of the TI C6X
|
||||
processors. These intrinsics, listed below, are available after
|
||||
inclusion of the @code{c6x_intrinsics.h} header file. They map directly
|
||||
to C6X instructions.
|
||||
|
||||
@smallexample
|
||||
|
||||
int _sadd (int, int)
|
||||
int _ssub (int, int)
|
||||
int _sadd2 (int, int)
|
||||
int _ssub2 (int, int)
|
||||
long long _mpy2 (int, int)
|
||||
long long _smpy2 (int, int)
|
||||
int _add4 (int, int)
|
||||
int _sub4 (int, int)
|
||||
int _saddu4 (int, int)
|
||||
|
||||
int _smpy (int, int)
|
||||
int _smpyh (int, int)
|
||||
int _smpyhl (int, int)
|
||||
int _smpylh (int, int)
|
||||
|
||||
int _sshl (int, int)
|
||||
int _subc (int, int)
|
||||
|
||||
int _avg2 (int, int)
|
||||
int _avgu4 (int, int)
|
||||
|
||||
int _clrr (int, int)
|
||||
int _extr (int, int)
|
||||
int _extru (int, int)
|
||||
int _abs (int)
|
||||
int _abs2 (int)
|
||||
|
||||
@end smallexample
|
||||
|
||||
@node Target Format Checks
|
||||
@section Format Checks Specific to Particular Target Machines
|
||||
|
||||
|
|
|
|||
|
|
@ -3071,6 +3071,8 @@ information are.
|
|||
@item
|
||||
@uref{#sparcv9-x-solaris2,,sparcv9-*-solaris2*}
|
||||
@item
|
||||
@uref{#c6x-x-x,,c6x-*-*}
|
||||
@item
|
||||
@uref{#x-x-vxworks,,*-*-vxworks*}
|
||||
@item
|
||||
@uref{#x86-64-x-x,,x86_64-*-*, amd64-*-*}
|
||||
|
|
@ -4379,6 +4381,13 @@ and @option{-xildoff} turns off the incremental linker.
|
|||
|
||||
This is a synonym for @samp{sparc64-*-solaris2*}.
|
||||
|
||||
@html
|
||||
<hr />
|
||||
@end html
|
||||
@heading @anchor{c6x-x-x}c6x-*-*
|
||||
|
||||
The C6X family of processors. This port requires binutils-2.22 or newer.
|
||||
|
||||
@html
|
||||
<hr />
|
||||
@end html
|
||||
|
|
|
|||
|
|
@ -496,6 +496,10 @@ Objective-C and Objective-C++ Dialects}.
|
|||
-mfast-fp -minline-plt -mmulticore -mcorea -mcoreb -msdram @gol
|
||||
-micplb}
|
||||
|
||||
@emph{C6X Options}
|
||||
@gccoptlist{-mbig-endian -mlittle-endian -march=@var{cpu} @gol
|
||||
-msim -msdata=@var{sdata-type}}
|
||||
|
||||
@emph{CRIS Options}
|
||||
@gccoptlist{-mcpu=@var{cpu} -march=@var{cpu} -mtune=@var{cpu} @gol
|
||||
-mmax-stack-frame=@var{n} -melinux-stacksize=@var{n} @gol
|
||||
|
|
@ -10091,6 +10095,7 @@ platform.
|
|||
* ARM Options::
|
||||
* AVR Options::
|
||||
* Blackfin Options::
|
||||
* C6X Options::
|
||||
* CRIS Options::
|
||||
* Darwin Options::
|
||||
* DEC Alpha Options::
|
||||
|
|
@ -10755,6 +10760,54 @@ anomaly workarounds. For Linux targets, the default is to assume ICPLBs
|
|||
are enabled; for standalone applications the default is off.
|
||||
@end table
|
||||
|
||||
@node C6X Options
|
||||
@subsection C6X Options
|
||||
@cindex C6X Options
|
||||
|
||||
@table @gcctabopt
|
||||
@item -march=@var{name}
|
||||
@opindex march
|
||||
This specifies the name of the target architecture. GCC uses this
|
||||
name to determine what kind of instructions it can emit when generating
|
||||
assembly code. Permissible names are: @samp{c62x},
|
||||
@samp{c64x}, @samp{c64x+}, @samp{c67x}, @samp{c67x+}, @samp{c674x}.
|
||||
|
||||
@item -mbig-endian
|
||||
@opindex mbig-endian
|
||||
Generate code for a big endian target.
|
||||
|
||||
@item -mlittle-endian
|
||||
@opindex mlittle-endian
|
||||
Generate code for a little endian target. This is the default.
|
||||
|
||||
@item -msim
|
||||
@opindex msim
|
||||
Choose startup files and linker script suitable for the simulator.
|
||||
|
||||
@item -msdata=default
|
||||
@opindex msdata=default
|
||||
Put small global and static data in the @samp{.neardata} section,
|
||||
which is pointed to by register @code{B14}. Put small uninitialized
|
||||
global and static data in the @samp{.bss} section, which is adjacent
|
||||
to the @samp{.neardata} section. Put small read-only data into the
|
||||
@samp{.rodata} section. The corresponding sections used for large
|
||||
pieces of data are @samp{.fardata}, @samp{.far} and @samp{.const}.
|
||||
|
||||
@item -msdata=all
|
||||
@opindex msdata=all
|
||||
Put all data, not just small objets, into the sections reserved for
|
||||
small data, and use addressing relative to the @code{B14} register to
|
||||
access them.
|
||||
|
||||
@item -msdata=none
|
||||
@opindex msdata=none
|
||||
Make no use of the sections reserved for small data, and use absolute
|
||||
addresses to access all data. Put all initialized global and static
|
||||
data in the @samp{.fardata} section, and all uninitialized data in the
|
||||
@samp{.far} section. Put all constant data into the @samp{.const}
|
||||
section.
|
||||
@end table
|
||||
|
||||
@node CRIS Options
|
||||
@subsection CRIS Options
|
||||
@cindex CRIS Options
|
||||
|
|
|
|||
|
|
@ -3304,6 +3304,89 @@ The constant 0.
|
|||
|
||||
@end table
|
||||
|
||||
@item TI C6X family---@file{config/c6x/constraints.md}
|
||||
@table @code
|
||||
@item a
|
||||
Register file A (A0--A31).
|
||||
|
||||
@item b
|
||||
Register file B (B0--B31).
|
||||
|
||||
@item A
|
||||
Predicate registers in register file A (A0--A2 on C64X and
|
||||
higher, A1 and A2 otherwise).
|
||||
|
||||
@item B
|
||||
Predicate registers in register file B (B0--B2).
|
||||
|
||||
@item C
|
||||
A call-used register in register file B (B0--B9, B16--B31).
|
||||
|
||||
@item Da
|
||||
Register file A, excluding predicate registers (A3--A31,
|
||||
plus A0 if not C64X or higher).
|
||||
|
||||
@item Db
|
||||
Register file B, excluding predicate registers (B3--B31).
|
||||
|
||||
@item Iu4
|
||||
Integer constant in the range 0 @dots{} 15.
|
||||
|
||||
@item Iu5
|
||||
Integer constant in the range 0 @dots{} 31.
|
||||
|
||||
@item In5
|
||||
Integer constant in the range @minus{}31 @dots{} 0.
|
||||
|
||||
@item Is5
|
||||
Integer constant in the range @minus{}16 @dots{} 15.
|
||||
|
||||
@item I5x
|
||||
Integer constant that can be the operand of an ADDA or a SUBA insn.
|
||||
|
||||
@item IuB
|
||||
Integer constant in the range 0 @dots{} 65535.
|
||||
|
||||
@item IsB
|
||||
Integer constant in the range @minus{}32768 @dots{} 32767.
|
||||
|
||||
@item IsC
|
||||
Integer constant in the range @math{-2^{20}} @dots{} @math{2^{20} - 1}.
|
||||
|
||||
@item Jc
|
||||
Integer constant that is a valid mask for the clr instruction.
|
||||
|
||||
@item Js
|
||||
Integer constant that is a valid mask for the set instruction.
|
||||
|
||||
@item Q
|
||||
Memory location with A base register.
|
||||
|
||||
@item R
|
||||
Memory location with B base register.
|
||||
|
||||
@ifset INTERNALS
|
||||
@item S0
|
||||
On C64x+ targets, a GP-relative small data reference.
|
||||
|
||||
@item S1
|
||||
Any kind of @code{SYMBOL_REF}, for use in a call address.
|
||||
|
||||
@item Si
|
||||
Any kind of immediate operand, unless it matches the S0 constraint.
|
||||
|
||||
@item T
|
||||
Memory location with B base register, but not using a long offset.
|
||||
|
||||
@item W
|
||||
A memory operand with an address that can't be used in an unaligned access.
|
||||
|
||||
@end ifset
|
||||
@item Z
|
||||
Register B14 (aka DP).
|
||||
|
||||
@end table
|
||||
|
||||
@item Xtensa---@file{config/xtensa/constraints.md}
|
||||
@table @code
|
||||
@item a
|
||||
|
|
|
|||
|
|
@ -1389,6 +1389,36 @@ UDItype __umulsidi3 (USItype, USItype);
|
|||
} while (0)
|
||||
#endif /* __vax__ */
|
||||
|
||||
#ifdef _TMS320C6X
|
||||
#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
|
||||
do \
|
||||
{ \
|
||||
UDItype __ll; \
|
||||
__asm__ ("addu .l1 %1, %2, %0" \
|
||||
: "=a" (__ll) : "a" (al), "a" (bl)); \
|
||||
(sl) = (USItype)__ll; \
|
||||
(sh) = ((USItype)(__ll >> 32)) + (ah) + (bh); \
|
||||
} \
|
||||
while (0)
|
||||
|
||||
#ifdef _TMS320C6400_PLUS
|
||||
#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
|
||||
#define umul_ppmm(w1, w0, u, v) \
|
||||
do { \
|
||||
UDItype __x = (UDItype) (USItype) (u) * (USItype) (v); \
|
||||
(w1) = (USItype) (__x >> 32); \
|
||||
(w0) = (USItype) (__x); \
|
||||
} while (0)
|
||||
#endif /* _TMS320C6400_PLUS */
|
||||
|
||||
#define count_leading_zeros(count, x) ((count) = __builtin_clz (x))
|
||||
#ifdef _TMS320C6400
|
||||
#define count_trailing_zeros(count, x) ((count) = __builtin_ctz (x))
|
||||
#endif
|
||||
#define UMUL_TIME 4
|
||||
#define UDIV_TIME 40
|
||||
#endif /* _TMS320C6X */
|
||||
|
||||
#if defined (__xtensa__) && W_TYPE_SIZE == 32
|
||||
/* This code is not Xtensa-configuration-specific, so rely on the compiler
|
||||
to expand builtin functions depending on what configuration features
|
||||
|
|
|
|||
|
|
@ -1,3 +1,8 @@
|
|||
2011-07-15 Bernd Schmidt <bernds@codesourcery.com>
|
||||
|
||||
* config.host: Handle tic6x-*-*.
|
||||
* config/c6x/c6x-abi.h: New file.
|
||||
|
||||
2011-07-13 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
|
||||
|
||||
* config/i386/crtprec.c: New file.
|
||||
|
|
|
|||
|
|
@ -146,6 +146,9 @@ sh[123456789lbe]*-*-*)
|
|||
v850*-*-*)
|
||||
cpu_type=v850
|
||||
;;
|
||||
tic6x-*-*)
|
||||
cpu_type=c6x
|
||||
;;
|
||||
esac
|
||||
|
||||
# Common parts for widely ported systems.
|
||||
|
|
@ -662,6 +665,9 @@ sparc64-*-netbsd*)
|
|||
;;
|
||||
spu-*-elf*)
|
||||
;;
|
||||
tic6x-*-*)
|
||||
tmake_file="${tmake_file} t-gnu-prefix"
|
||||
;;
|
||||
v850*-*-*)
|
||||
;;
|
||||
vax-*-linux*)
|
||||
|
|
|
|||
109
libgcc/config/c6x/c6x-abi.h
Normal file
109
libgcc/config/c6x/c6x-abi.h
Normal file
|
|
@ -0,0 +1,109 @@
|
|||
/* Header file for C6X ABI versions of libgcc functions.
|
||||
Copyright (C) 2011
|
||||
Free Software Foundation, Inc.
|
||||
Contributed by Bernd Schmidt <bernds@codesourcery.com>
|
||||
|
||||
This file is part of GCC.
|
||||
|
||||
GCC is free software; you can redistribute it and/or modify it
|
||||
under the terms of the GNU General Public License as published
|
||||
by the Free Software Foundation; either version 3, or (at your
|
||||
option) any later version.
|
||||
|
||||
GCC is distributed in the hope that it will be useful, but WITHOUT
|
||||
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
|
||||
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
|
||||
License for more details.
|
||||
|
||||
Under Section 7 of GPL version 3, you are granted additional
|
||||
permissions described in the GCC Runtime Library Exception, version
|
||||
3.1, as published by the Free Software Foundation.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with GCC; see the file COPYING3. If not see
|
||||
<http://www.gnu.org/licenses/>. */
|
||||
|
||||
/* Make __c6xabi_AEABI_NAME an alias for __GCC_NAME. */
|
||||
#define RENAME_LIBRARY(GCC_NAME, AEABI_NAME) \
|
||||
__asm__ (".globl\t__c6xabi_" #AEABI_NAME "\n" \
|
||||
".set\t__c6xabi_" #AEABI_NAME \
|
||||
", __gnu_" #GCC_NAME "\n");
|
||||
|
||||
/* Rename helper functions to the names specified in the C6000 ELF ABI. */
|
||||
#ifdef L_divsi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (divsi3, divi)
|
||||
#endif
|
||||
#ifdef L_divdi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (divdi3, divlli)
|
||||
#endif
|
||||
#ifdef L_udivsi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (udivsi3, divu)
|
||||
#endif
|
||||
#ifdef L_udivdi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (udivdi3, divull)
|
||||
#endif
|
||||
#ifdef L_udivmoddi4
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (udivmoddi4, divremull)
|
||||
#endif
|
||||
#ifdef L_modsi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (modsi3, remi)
|
||||
#endif
|
||||
#ifdef L_moddi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (moddi3, remlli)
|
||||
#endif
|
||||
#ifdef L_umodsi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (umodsi3, remu)
|
||||
#endif
|
||||
#ifdef L_umoddi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (umoddi3, remull)
|
||||
#endif
|
||||
#ifdef L_negdi2
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (negdi2, negll)
|
||||
#endif
|
||||
#ifdef L_muldi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (muldi3, mpyll)
|
||||
#endif
|
||||
#ifdef L_ashrdi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (ashrdi3, llshr)
|
||||
#endif
|
||||
#ifdef L_lshrdi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (lshrdi3, llshru)
|
||||
#endif
|
||||
#ifdef L_ashldi3
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (ashldi3, llshl)
|
||||
#endif
|
||||
|
||||
/* The following are excluded from softfp due to softfp_exclude_libgcc2,
|
||||
so we rename them here rather than in sfp-machine.h. */
|
||||
#ifdef L_fixdfdi
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixdfdi, fixdlli)
|
||||
#endif
|
||||
#ifdef L_fixunsdfsi
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunsdfsi, fixdu)
|
||||
#endif
|
||||
#ifdef L_fixunsdfdi
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunsdfdi, fixdull)
|
||||
#endif
|
||||
#ifdef L_fixsfdi
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixsfdi, fixflli)
|
||||
#endif
|
||||
#ifdef L_fixunssfsi
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunssfsi, fixfu)
|
||||
#endif
|
||||
#ifdef L_fixunssfdi
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (fixunssfdi, fixfull)
|
||||
#endif
|
||||
#ifdef L_floatdidf
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatdidf, fltllid)
|
||||
#endif
|
||||
#ifdef L_floatundidf
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatundidf, fltulld)
|
||||
#endif
|
||||
#ifdef L_floatdisf
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatdisf, fltllif)
|
||||
#endif
|
||||
#ifdef L_floatundisf
|
||||
#define DECLARE_LIBRARY_RENAMES RENAME_LIBRARY (floatundisf, fltullf)
|
||||
#endif
|
||||
|
||||
#define LIBGCC2_GNU_PREFIX
|
||||
Loading…
Add table
Reference in a new issue