rs6000.c (rs6000_expand_vector_set): Add support for using xxinsertw and vinsert{b,h} on ISA 3.0.
[gcc]
2016-11-14 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.c (rs6000_expand_vector_set): Add support
for using xxinsertw and vinsert{b,h} on ISA 3.0.
* config/rs6000/vsx.md (vsx_extract_<mode>): Update comment.
(vsx_set_<mode>_p9): New insn to generate xxinsertw and
vinsert{b,h} on ISA 3.0.
[gcc/testsuite]
2016-11-14 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vec-set-int.c: New test.
* gcc.target/powerpc/vec-set-short.c: Likesie.
* gcc.target/powerpc/vec-set-char.c: Likewise.
From-SVN: r242397
This commit is contained in:
Michael Meissner
Michael Meissner
parent
3eb89071d6
commit
bcb9a772e9
7 changed files with 190 additions and 9 deletions
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@ -1,3 +1,12 @@
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2016-11-14 Michael Meissner <meissner@linux.vnet.ibm.com>
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* config/rs6000/rs6000.c (rs6000_expand_vector_set): Add support
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for using xxinsertw and vinsert{b,h} on ISA 3.0.
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* config/rs6000/vsx.md (vsx_extract_<mode>): Update comment.
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(vsx_set_<mode>_p9): New insn to generate xxinsertw and
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vinsert{b,h} on ISA 3.0.
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2016-11-14 Thomas Preud'homme <thomas.preudhomme@arm.com>
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* tree-ssa-math-opts.c (find_bswap_or_nop): Zero out bytes in cmpxchg
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@ -18,7 +27,7 @@
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2016-11-14 Prasad Ghangal <prasad.ghangal@gmail.com>
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Richard Biener <rguenther@suse.de>
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* doc/invoke.texi (fgimple): Document.
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* dumpfile.h (TDF_GIMPLE): Add.
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* dumpfile.c (dump_options): Add gimple.
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@ -7095,12 +7095,33 @@ rs6000_expand_vector_set (rtx target, rtx val, int elt)
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int width = GET_MODE_SIZE (inner_mode);
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int i;
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if (VECTOR_MEM_VSX_P (mode) && (mode == V2DFmode || mode == V2DImode))
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if (VECTOR_MEM_VSX_P (mode))
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{
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rtx (*set_func) (rtx, rtx, rtx, rtx)
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= ((mode == V2DFmode) ? gen_vsx_set_v2df : gen_vsx_set_v2di);
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emit_insn (set_func (target, target, val, GEN_INT (elt)));
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return;
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rtx insn = NULL_RTX;
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rtx elt_rtx = GEN_INT (elt);
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if (mode == V2DFmode)
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insn = gen_vsx_set_v2df (target, target, val, elt_rtx);
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else if (mode == V2DImode)
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insn = gen_vsx_set_v2di (target, target, val, elt_rtx);
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else if (TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
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&& TARGET_UPPER_REGS_DI && TARGET_POWERPC64)
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{
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if (mode == V4SImode)
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insn = gen_vsx_set_v4si_p9 (target, target, val, elt_rtx);
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else if (mode == V8HImode)
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insn = gen_vsx_set_v8hi_p9 (target, target, val, elt_rtx);
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else if (mode == V16QImode)
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insn = gen_vsx_set_v16qi_p9 (target, target, val, elt_rtx);
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}
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if (insn)
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{
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emit_insn (insn);
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return;
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}
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}
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/* Simplify setting single element vectors like V1TImode. */
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@ -2514,9 +2514,9 @@
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FAIL;
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})
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;; Extraction of a single element in a small integer vector. None of the small
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;; types are currently allowed in a vector register, so we extract to a DImode
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;; and either do a direct move or store.
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;; Extraction of a single element in a small integer vector. Until ISA 3.0,
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;; none of the small types were allowed in a vector register, so we had to
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;; extract to a DImode and either do a direct move or store.
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(define_expand "vsx_extract_<mode>"
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[(parallel [(set (match_operand:<VS_scalar> 0 "gpc_reg_operand")
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(vec_select:<VS_scalar>
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@ -2839,6 +2839,31 @@
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DONE;
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})
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;; V4SI/V8HI/V16QI set operation on ISA 3.0
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(define_insn "vsx_set_<mode>_p9"
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[(set (match_operand:VSX_EXTRACT_I 0 "gpc_reg_operand" "=<VSX_EX>")
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(unspec:VSX_EXTRACT_I
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[(match_operand:VSX_EXTRACT_I 1 "gpc_reg_operand" "0")
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(match_operand:<VS_scalar> 2 "gpc_reg_operand" "<VSX_EX>")
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(match_operand:QI 3 "<VSX_EXTRACT_PREDICATE>" "n")]
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UNSPEC_VSX_SET))]
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"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_P9_VECTOR && TARGET_VSX_SMALL_INTEGER
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&& TARGET_UPPER_REGS_DI && TARGET_POWERPC64"
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{
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int ele = INTVAL (operands[3]);
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int nunits = GET_MODE_NUNITS (<MODE>mode);
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if (!VECTOR_ELT_ORDER_BIG)
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ele = nunits - 1 - ele;
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operands[3] = GEN_INT (nunits * ele);
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if (<MODE>mode == V4SImode)
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return "xxinsertw %x0,%x2,%3";
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else
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return "vinsert<wd> %0,%2,%3";
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}
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[(set_attr "type" "vecperm")])
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;; Expanders for builtins
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(define_expand "vsx_mergel_<mode>"
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[(use (match_operand:VSX_D 0 "vsx_register_operand" ""))
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@ -1,3 +1,9 @@
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2016-11-14 Michael Meissner <meissner@linux.vnet.ibm.com>
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* gcc.target/powerpc/vec-set-int.c: New test.
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* gcc.target/powerpc/vec-set-short.c: Likesie.
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* gcc.target/powerpc/vec-set-char.c: Likewise.
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2016-11-14 Jakub Jelinek <jakub@redhat.com>
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* g++.dg/cpp1z/feat-cxx1z.C: Test __cpp_structured_bindings macro.
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40
gcc/testsuite/gcc.target/powerpc/vec-set-char.c
Normal file
40
gcc/testsuite/gcc.target/powerpc/vec-set-char.c
Normal file
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@ -0,0 +1,40 @@
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#include <altivec.h>
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/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
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/* { dg-require-effective-target powerpc_p9vector_ok } */
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/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di -mvsx-small-integer" } */
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vector char
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insert_0_0 (vector char v)
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{
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return vec_insert (0, v, 0);
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}
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vector char
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insert_m1_1 (vector char v)
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{
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return vec_insert (-1, v, 1);
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}
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vector char
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insert_5_2 (vector char v)
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{
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return vec_insert (5, v, 2);
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}
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vector char
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insert_mem_15 (vector char v, char *p)
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{
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return vec_insert (*p, v, 15);
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}
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/* { dg-final { scan-assembler "vinsertb" } } */
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/* { dg-final { scan-assembler "xxspltib" } } */
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/* { dg-final { scan-assembler "vspltisb" } } */
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/* { dg-final { scan-assembler-not "mtvsrd" } } */
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/* { dg-final { scan-assembler-not "mtvsrdd" } } */
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/* { dg-final { scan-assembler-not "mtvsrwa" } } */
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/* { dg-final { scan-assembler-not "mtvsrwz" } } */
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/* { dg-final { scan-assembler-not "mfvsrd" } } */
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/* { dg-final { scan-assembler-not "mfvsrwz" } } */
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40
gcc/testsuite/gcc.target/powerpc/vec-set-int.c
Normal file
40
gcc/testsuite/gcc.target/powerpc/vec-set-int.c
Normal file
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@ -0,0 +1,40 @@
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#include <altivec.h>
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/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
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/* { dg-require-effective-target powerpc_p9vector_ok } */
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/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di -mvsx-small-integer" } */
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vector int
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insert_0_0 (vector int v)
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{
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return vec_insert (0, v, 0);
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}
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vector int
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insert_m1_1 (vector int v)
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{
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return vec_insert (-1, v, 1);
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}
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vector int
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insert_5_2 (vector int v)
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{
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return vec_insert (5, v, 2);
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}
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vector int
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insert_mem_3 (vector int v, int *p)
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{
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return vec_insert (*p, v, 3);
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}
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/* { dg-final { scan-assembler "xxinsertw" } } */
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/* { dg-final { scan-assembler "xxspltib" } } */
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/* { dg-final { scan-assembler "vspltisw" } } */
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/* { dg-final { scan-assembler-not "mtvsrd" } } */
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/* { dg-final { scan-assembler-not "mtvsrdd" } } */
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/* { dg-final { scan-assembler-not "mtvsrwa" } } */
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/* { dg-final { scan-assembler-not "mtvsrwz" } } */
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/* { dg-final { scan-assembler-not "mfvsrd" } } */
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/* { dg-final { scan-assembler-not "mfvsrwz" } } */
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40
gcc/testsuite/gcc.target/powerpc/vec-set-short.c
Normal file
40
gcc/testsuite/gcc.target/powerpc/vec-set-short.c
Normal file
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@ -0,0 +1,40 @@
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#include <altivec.h>
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/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
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/* { dg-require-effective-target powerpc_p9vector_ok } */
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/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di -mvsx-small-integer" } */
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vector short
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insert_0_0 (vector short v)
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{
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return vec_insert (0, v, 0);
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}
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vector short
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insert_m1_1 (vector short v)
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{
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return vec_insert (-1, v, 1);
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}
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vector short
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insert_5_2 (vector short v)
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{
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return vec_insert (5, v, 2);
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}
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vector short
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insert_mem_7 (vector short v, short *p)
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{
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return vec_insert (*p, v, 7);
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}
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/* { dg-final { scan-assembler "vinserth" } } */
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/* { dg-final { scan-assembler "xxspltib" } } */
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/* { dg-final { scan-assembler "vspltish" } } */
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/* { dg-final { scan-assembler-not "mtvsrd" } } */
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/* { dg-final { scan-assembler-not "mtvsrdd" } } */
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/* { dg-final { scan-assembler-not "mtvsrwa" } } */
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/* { dg-final { scan-assembler-not "mtvsrwz" } } */
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/* { dg-final { scan-assembler-not "mfvsrd" } } */
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/* { dg-final { scan-assembler-not "mfvsrwz" } } */
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