mips.c (mips_prepare_builtin_arg): Replace icode and opno arguments with an expand_operand.
gcc/ * config/mips/mips.c (mips_prepare_builtin_arg): Replace icode and opno arguments with an expand_operand. Use create_input_operand. (mips_prepare_builtin_target): Delete. (mips_expand_builtin_insn, mips_expand_builtin_compare_1): New functions. (mips_expand_builtin_direct): Use create_output_operand and mips_expand_builtin_insn. Update call to mips_prepare_builtin_arg. (mips_expand_builtin_movtf): Likewise. Use mips_expand_fp_comparison. (mips_expand_builtin_compare): Use mips_expand_fp_comparison. From-SVN: r171571
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
5092eb960c
commit
b99ce2a8b9
2 changed files with 75 additions and 103 deletions
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@ -1,3 +1,15 @@
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2011-03-27 Richard Sandiford <rdsandiford@googlemail.com>
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* config/mips/mips.c (mips_prepare_builtin_arg): Replace icode and
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opno arguments with an expand_operand. Use create_input_operand.
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(mips_prepare_builtin_target): Delete.
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(mips_expand_builtin_insn, mips_expand_builtin_compare_1): New
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functions.
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(mips_expand_builtin_direct): Use create_output_operand and
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mips_expand_builtin_insn. Update call to mips_prepare_builtin_arg.
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(mips_expand_builtin_movtf): Likewise. Use mips_expand_fp_comparison.
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(mips_expand_builtin_compare): Use mips_expand_fp_comparison.
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2011-03-27 Ira Rosen <ira.rosen@linaro.org>
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* config/arm/arm.c (arm_autovectorize_vector_sizes): New
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@ -13184,56 +13184,64 @@ mips_builtin_decl (unsigned int code, bool initialize_p ATTRIBUTE_UNUSED)
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return mips_builtin_decls[code];
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}
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/* Take argument ARGNO from EXP's argument list and convert it into a
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form suitable for input operand OPNO of instruction ICODE. Return the
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value. */
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/* Take argument ARGNO from EXP's argument list and convert it into
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an expand operand. Store the operand in *OP. */
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static rtx
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mips_prepare_builtin_arg (enum insn_code icode,
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unsigned int opno, tree exp, unsigned int argno)
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static void
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mips_prepare_builtin_arg (struct expand_operand *op, tree exp,
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unsigned int argno)
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{
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tree arg;
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rtx value;
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enum machine_mode mode;
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arg = CALL_EXPR_ARG (exp, argno);
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value = expand_normal (arg);
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mode = insn_data[icode].operand[opno].mode;
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if (!insn_data[icode].operand[opno].predicate (value, mode))
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{
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/* We need to get the mode from ARG for two reasons:
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- to cope with address operands, where MODE is the mode of the
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memory, rather than of VALUE itself.
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- to cope with special predicates like pmode_register_operand,
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where MODE is VOIDmode. */
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value = copy_to_mode_reg (TYPE_MODE (TREE_TYPE (arg)), value);
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/* Check the predicate again. */
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if (!insn_data[icode].operand[opno].predicate (value, mode))
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{
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error ("invalid argument to built-in function");
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return const0_rtx;
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}
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}
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return value;
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create_input_operand (op, value, TYPE_MODE (TREE_TYPE (arg)));
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}
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/* Return an rtx suitable for output operand OP of instruction ICODE.
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If TARGET is non-null, try to use it where possible. */
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/* Expand instruction ICODE as part of a built-in function sequence.
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Use the first NOPS elements of OPS as the instruction's operands.
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HAS_TARGET_P is true if operand 0 is a target; it is false if the
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instruction has no target.
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Return the target rtx if HAS_TARGET_P, otherwise return const0_rtx. */
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static rtx
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mips_prepare_builtin_target (enum insn_code icode, unsigned int op, rtx target)
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mips_expand_builtin_insn (enum insn_code icode, unsigned int nops,
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struct expand_operand *ops, bool has_target_p)
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{
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enum machine_mode mode;
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if (!maybe_expand_insn (icode, nops, ops))
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{
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error ("invalid argument to built-in function");
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return has_target_p ? gen_reg_rtx (ops[0].mode) : const0_rtx;
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}
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return has_target_p ? ops[0].value : const0_rtx;
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}
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mode = insn_data[icode].operand[op].mode;
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if (target == 0 || !insn_data[icode].operand[op].predicate (target, mode))
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target = gen_reg_rtx (mode);
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/* Expand a floating-point comparison for built-in function call EXP.
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The first NARGS arguments are the values to be compared. ICODE is
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the .md pattern that does the comparison and COND is the condition
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that is being tested. Return an rtx for the result. */
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return target;
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static rtx
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mips_expand_builtin_compare_1 (enum insn_code icode,
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enum mips_fp_condition cond,
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tree exp, int nargs)
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{
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struct expand_operand ops[MAX_RECOG_OPERANDS];
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int opno, argno;
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/* The instruction should have a target operand, an operand for each
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argument, and an operand for COND. */
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gcc_assert (nargs + 2 == insn_data[(int) icode].n_operands);
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opno = 0;
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create_output_operand (&ops[opno++], NULL_RTX,
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insn_data[(int) icode].operand[0].mode);
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for (argno = 0; argno < nargs; argno++)
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mips_prepare_builtin_arg (&ops[opno++], exp, argno);
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create_integer_operand (&ops[opno++], (int) cond);
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return mips_expand_builtin_insn (icode, opno, ops, true);
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}
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/* Expand a MIPS_BUILTIN_DIRECT or MIPS_BUILTIN_DIRECT_NO_TARGET function;
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@ -13245,44 +13253,23 @@ static rtx
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mips_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
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bool has_target_p)
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{
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rtx ops[MAX_RECOG_OPERANDS];
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struct expand_operand ops[MAX_RECOG_OPERANDS];
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int opno, argno;
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/* Map any target to operand 0. */
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opno = 0;
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if (has_target_p)
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{
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target = mips_prepare_builtin_target (icode, opno, target);
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ops[opno] = target;
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opno++;
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}
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create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
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/* Map the arguments to the other operands. The n_operands value
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for an expander includes match_dups and match_scratches as well as
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match_operands, so n_operands is only an upper bound on the number
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of arguments to the expander function. */
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gcc_assert (opno + call_expr_nargs (exp) <= insn_data[icode].n_operands);
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for (argno = 0; argno < call_expr_nargs (exp); argno++, opno++)
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ops[opno] = mips_prepare_builtin_arg (icode, opno, exp, argno);
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for (argno = 0; argno < call_expr_nargs (exp); argno++)
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mips_prepare_builtin_arg (&ops[opno++], exp, argno);
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switch (opno)
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{
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case 2:
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emit_insn (GEN_FCN (icode) (ops[0], ops[1]));
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break;
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case 3:
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emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2]));
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break;
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case 4:
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emit_insn (GEN_FCN (icode) (ops[0], ops[1], ops[2], ops[3]));
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break;
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default:
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gcc_unreachable ();
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}
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return target;
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return mips_expand_builtin_insn (icode, opno, ops, has_target_p);
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}
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/* Expand a __builtin_mips_movt_*_ps or __builtin_mips_movf_*_ps
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@ -13296,27 +13283,24 @@ mips_expand_builtin_movtf (enum mips_builtin_type type,
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enum insn_code icode, enum mips_fp_condition cond,
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rtx target, tree exp)
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{
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rtx cmp_result, op0, op1;
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struct expand_operand ops[4];
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rtx cmp_result;
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cmp_result = mips_prepare_builtin_target (icode, 0, 0);
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op0 = mips_prepare_builtin_arg (icode, 1, exp, 0);
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op1 = mips_prepare_builtin_arg (icode, 2, exp, 1);
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emit_insn (GEN_FCN (icode) (cmp_result, op0, op1, GEN_INT (cond)));
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icode = CODE_FOR_mips_cond_move_tf_ps;
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target = mips_prepare_builtin_target (icode, 0, target);
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cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp, 2);
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create_output_operand (&ops[0], target, TYPE_MODE (TREE_TYPE (exp)));
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if (type == MIPS_BUILTIN_MOVT)
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{
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op1 = mips_prepare_builtin_arg (icode, 2, exp, 2);
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op0 = mips_prepare_builtin_arg (icode, 1, exp, 3);
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mips_prepare_builtin_arg (&ops[2], exp, 2);
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mips_prepare_builtin_arg (&ops[1], exp, 3);
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}
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else
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{
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op0 = mips_prepare_builtin_arg (icode, 1, exp, 2);
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op1 = mips_prepare_builtin_arg (icode, 2, exp, 3);
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mips_prepare_builtin_arg (&ops[1], exp, 2);
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mips_prepare_builtin_arg (&ops[2], exp, 3);
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}
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emit_insn (gen_mips_cond_move_tf_ps (target, op0, op1, cmp_result));
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return target;
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create_fixed_operand (&ops[3], cmp_result);
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return mips_expand_builtin_insn (CODE_FOR_mips_cond_move_tf_ps,
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4, ops, true);
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}
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/* Move VALUE_IF_TRUE into TARGET if CONDITION is true; move VALUE_IF_FALSE
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@ -13357,36 +13341,12 @@ mips_expand_builtin_compare (enum mips_builtin_type builtin_type,
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enum insn_code icode, enum mips_fp_condition cond,
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rtx target, tree exp)
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{
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rtx offset, condition, cmp_result, args[MAX_RECOG_OPERANDS];
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int argno;
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rtx offset, condition, cmp_result;
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if (target == 0 || GET_MODE (target) != SImode)
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target = gen_reg_rtx (SImode);
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/* The instruction should have a target operand, an operand for each
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argument, and an operand for COND. */
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gcc_assert (call_expr_nargs (exp) + 2 == insn_data[icode].n_operands);
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/* Prepare the operands to the comparison. */
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cmp_result = mips_prepare_builtin_target (icode, 0, 0);
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for (argno = 0; argno < call_expr_nargs (exp); argno++)
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args[argno] = mips_prepare_builtin_arg (icode, argno + 1, exp, argno);
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switch (insn_data[icode].n_operands)
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{
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case 4:
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emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
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GEN_INT (cond)));
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break;
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case 6:
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emit_insn (GEN_FCN (icode) (cmp_result, args[0], args[1],
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args[2], args[3], GEN_INT (cond)));
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break;
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default:
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gcc_unreachable ();
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}
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cmp_result = mips_expand_builtin_compare_1 (icode, cond, exp,
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call_expr_nargs (exp));
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/* If the comparison sets more than one register, we define the result
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to be 0 if all registers are false and -1 if all registers are true.
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