i386: Unify {general,timode}_scalar_chain::convert_op [PR111822]
Recent PR111822 fix implemented REG_EH_REGION note copying to a STV converted preload instruction in general_scalar_chain::convert_op. However, the same issue remains in timode_scalar_chain::convert_op. Instead of copying the newly introduced code to timode_scalar_chain::convert_op, the patch unifies both functions to a common function. PR target/111822 gcc/ChangeLog: * config/i386/i386-features.cc (smode_convert_cst): New function to handle SImode, DImode and TImode immediates, generalized from timode_convert_cst. (timode_convert_cst): Remove. (scalar_chain::convert_op): Unify from general_scalar_chain::convert_op and timode_scalar_chain::convert_op. (general_scalar_chain::convert_op): Remove. (timode_scalar_chain::convert_op): Remove. (timode_scalar_chain::convert_insn): Update the call to renamed timode_convert_cst. * config/i386/i386-features.h (class scalar_chain): Redeclare convert_op as protected class member. (class general_calar_chain): Remove convert_op. (class timode_scalar_chain): Ditto. gcc/testsuite/ChangeLog: * g++.target/i386/pr111822.C (dg-do): Compile only for ia32 targets. (dg-options): Add -march=x86-64.
This commit is contained in:
Uros Bizjak
parent
3be2b8f475
commit
b96c543688
3 changed files with 40 additions and 95 deletions
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@ -980,14 +980,35 @@ scalar_chain::convert_reg (rtx_insn *insn, rtx dst, rtx src)
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REGNO (src), REGNO (dst), INSN_UID (insn));
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}
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/* Helper function to convert immediate constant X to vmode. */
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static rtx
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smode_convert_cst (rtx x, enum machine_mode vmode)
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{
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/* Prefer all ones vector in case of -1. */
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if (constm1_operand (x, GET_MODE (x)))
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return CONSTM1_RTX (vmode);
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unsigned n = GET_MODE_NUNITS (vmode);
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rtx *v = XALLOCAVEC (rtx, n);
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v[0] = x;
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for (unsigned i = 1; i < n; ++i)
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v[i] = const0_rtx;
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return gen_rtx_CONST_VECTOR (vmode, gen_rtvec_v (n, v));
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}
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/* Convert operand OP in INSN. We should handle
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memory operands and uninitialized registers.
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All other register uses are converted during
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registers conversion. */
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void
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general_scalar_chain::convert_op (rtx *op, rtx_insn *insn)
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scalar_chain::convert_op (rtx *op, rtx_insn *insn)
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{
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rtx tmp;
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if (GET_MODE (*op) == V1TImode)
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return;
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*op = copy_rtx_if_shared (*op);
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if (GET_CODE (*op) == NOT
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@ -998,20 +1019,21 @@ general_scalar_chain::convert_op (rtx *op, rtx_insn *insn)
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}
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else if (MEM_P (*op))
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{
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rtx_insn* eh_insn, *movabs = NULL;
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rtx tmp = gen_reg_rtx (GET_MODE (*op));
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rtx_insn *movabs = NULL;
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/* Emit MOVABS to load from a 64-bit absolute address to a GPR. */
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if (!memory_operand (*op, GET_MODE (*op)))
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{
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rtx tmp2 = gen_reg_rtx (GET_MODE (*op));
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movabs = emit_insn_before (gen_rtx_SET (tmp2, *op), insn);
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tmp = gen_reg_rtx (GET_MODE (*op));
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movabs = emit_insn_before (gen_rtx_SET (tmp, *op), insn);
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*op = tmp2;
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*op = tmp;
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}
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eh_insn
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= emit_insn_before (gen_rtx_SET (gen_rtx_SUBREG (vmode, tmp, 0),
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tmp = gen_rtx_SUBREG (vmode, gen_reg_rtx (GET_MODE (*op)), 0);
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rtx_insn *eh_insn
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= emit_insn_before (gen_rtx_SET (copy_rtx (tmp),
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gen_gpr_to_xmm_move_src (vmode, *op)),
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insn);
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@ -1028,33 +1050,17 @@ general_scalar_chain::convert_op (rtx *op, rtx_insn *insn)
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}
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}
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*op = gen_rtx_SUBREG (vmode, tmp, 0);
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*op = tmp;
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if (dump_file)
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fprintf (dump_file, " Preloading operand for insn %d into r%d\n",
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INSN_UID (insn), REGNO (tmp));
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}
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else if (REG_P (*op))
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*op = gen_rtx_SUBREG (vmode, *op, 0);
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else if (CONST_SCALAR_INT_P (*op))
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{
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*op = gen_rtx_SUBREG (vmode, *op, 0);
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}
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else if (CONST_INT_P (*op))
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{
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rtx vec_cst;
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rtx tmp = gen_rtx_SUBREG (vmode, gen_reg_rtx (smode), 0);
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/* Prefer all ones vector in case of -1. */
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if (constm1_operand (*op, GET_MODE (*op)))
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vec_cst = CONSTM1_RTX (vmode);
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else
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{
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unsigned n = GET_MODE_NUNITS (vmode);
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rtx *v = XALLOCAVEC (rtx, n);
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v[0] = *op;
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for (unsigned i = 1; i < n; ++i)
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v[i] = const0_rtx;
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vec_cst = gen_rtx_CONST_VECTOR (vmode, gen_rtvec_v (n, v));
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}
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rtx vec_cst = smode_convert_cst (*op, vmode);
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if (!standard_sse_constant_p (vec_cst, vmode))
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{
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@ -1065,6 +1071,8 @@ general_scalar_chain::convert_op (rtx *op, rtx_insn *insn)
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emit_insn_before (seq, insn);
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}
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tmp = gen_rtx_SUBREG (vmode, gen_reg_rtx (smode), 0);
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emit_insn_before (gen_move_insn (copy_rtx (tmp), vec_cst), insn);
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*op = tmp;
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}
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@ -1767,67 +1775,6 @@ timode_scalar_chain::fix_debug_reg_uses (rtx reg)
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}
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}
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/* Helper function to convert immediate constant X to V1TImode. */
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static rtx
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timode_convert_cst (rtx x)
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{
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/* Prefer all ones vector in case of -1. */
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if (constm1_operand (x, TImode))
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return CONSTM1_RTX (V1TImode);
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rtx *v = XALLOCAVEC (rtx, 1);
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v[0] = x;
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return gen_rtx_CONST_VECTOR (V1TImode, gen_rtvec_v (1, v));
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}
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/* Convert operand OP in INSN from TImode to V1TImode. */
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void
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timode_scalar_chain::convert_op (rtx *op, rtx_insn *insn)
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{
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if (GET_MODE (*op) == V1TImode)
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return;
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*op = copy_rtx_if_shared (*op);
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if (REG_P (*op))
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*op = gen_rtx_SUBREG (V1TImode, *op, 0);
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else if (MEM_P (*op))
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{
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rtx tmp = gen_reg_rtx (V1TImode);
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emit_insn_before (gen_rtx_SET (tmp,
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gen_gpr_to_xmm_move_src (V1TImode, *op)),
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insn);
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*op = tmp;
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if (dump_file)
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fprintf (dump_file, " Preloading operand for insn %d into r%d\n",
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INSN_UID (insn), REGNO (tmp));
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}
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else if (CONST_SCALAR_INT_P (*op))
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{
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rtx tmp = gen_reg_rtx (V1TImode);
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rtx vec_cst = timode_convert_cst (*op);
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if (!standard_sse_constant_p (vec_cst, V1TImode))
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{
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start_sequence ();
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vec_cst = validize_mem (force_const_mem (V1TImode, vec_cst));
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rtx_insn *seq = get_insns ();
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end_sequence ();
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emit_insn_before (seq, insn);
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}
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emit_insn_before (gen_move_insn (tmp, vec_cst), insn);
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*op = tmp;
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}
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else
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{
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gcc_assert (SUBREG_P (*op));
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gcc_assert (GET_MODE (*op) == vmode);
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}
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}
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/* Convert INSN from TImode to V1T1mode. */
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void
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@ -1892,7 +1839,7 @@ timode_scalar_chain::convert_insn (rtx_insn *insn)
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}
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else
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{
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src = timode_convert_cst (src);
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src = smode_convert_cst (src, V1TImode);
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src = validize_mem (force_const_mem (V1TImode, src));
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use_move = MEM_P (dst);
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}
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@ -170,13 +170,13 @@ class scalar_chain
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void convert_insn_common (rtx_insn *insn);
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void make_vector_copies (rtx_insn *, rtx);
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void convert_registers ();
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void convert_op (rtx *op, rtx_insn *insn);
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private:
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bool add_insn (bitmap candidates, unsigned insn_uid, bitmap disallowed);
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bool analyze_register_chain (bitmap candidates, df_ref ref,
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bitmap disallowed);
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virtual void convert_insn (rtx_insn *insn) = 0;
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virtual void convert_op (rtx *op, rtx_insn *insn) = 0;
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};
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class general_scalar_chain : public scalar_chain
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@ -188,7 +188,6 @@ class general_scalar_chain : public scalar_chain
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private:
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void convert_insn (rtx_insn *insn) final override;
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void convert_op (rtx *op, rtx_insn *insn) final override;
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int vector_const_cost (rtx exp);
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rtx convert_rotate (enum rtx_code, rtx op0, rtx op1, rtx_insn *insn);
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};
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@ -202,7 +201,6 @@ class timode_scalar_chain : public scalar_chain
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private:
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void fix_debug_reg_uses (rtx reg);
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void convert_insn (rtx_insn *insn) final override;
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void convert_op (rtx *op, rtx_insn *insn) final override;
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};
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} // anon namespace
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@ -1,6 +1,6 @@
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/* PR target/111822 */
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/* { dg-do compile } */
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/* { dg-options "-O2 -flive-range-shrinkage -fno-dce -fnon-call-exceptions" } */
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/* { dg-do compile { target ia32 } } */
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/* { dg-options "-O2 -flive-range-shrinkage -fno-dce -fnon-call-exceptions -march=x86-64" } */
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typedef union {
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int *pNativeClosure;
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