[AArch64] Add branch-cost to cpu tuning information.
* gcc/config/aarch64-protos.h (struct cpu_branch_cost): New.
(tune_params): Add field branch_costs.
(aarch64_branch_cost): Declare.
* gcc/config/aarch64.c (generic_branch_cost): New.
(generic_tunings): Set field cpu_branch_cost to generic_branch_cost.
(cortexa53_tunings): Likewise.
(cortexa57_tunings): Likewise.
(thunderx_tunings): Likewise.
(xgene1_tunings): Likewise.
(aarch64_branch_cost): Define.
* gcc/config/aarch64/aarch64.h (BRANCH_COST): Redefine.
From-SVN: r222805
This commit is contained in:
Matthew Wahab
Matthew Wahab
parent
6987c38487
commit
b9066f5ae8
4 changed files with 54 additions and 1 deletions
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@ -1,3 +1,17 @@
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2015-05-05 Matthew Wahab <matthew.wahab@arm.com>
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* gcc/config/aarch64-protos.h (struct cpu_branch_cost): New.
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(tune_params): Add field branch_costs.
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(aarch64_branch_cost): Declare.
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* gcc/config/aarch64.c (generic_branch_cost): New.
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(generic_tunings): Set field cpu_branch_cost to generic_branch_cost.
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(cortexa53_tunings): Likewise.
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(cortexa57_tunings): Likewise.
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(thunderx_tunings): Likewise.
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(xgene1_tunings): Likewise.
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(aarch64_branch_cost): Define.
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* gcc/config/aarch64/aarch64.h (BRANCH_COST): Redefine.
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2015-05-05 Uros Bizjak <ubizjak@gmail.com>
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* config/i386/i386.c: Use HOST_WIDE_INT_1 instead of (HOST_WIDE_INT) 1
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@ -162,12 +162,20 @@ struct cpu_vector_cost
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const int cond_not_taken_branch_cost; /* Cost of not taken branch. */
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};
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/* Branch costs. */
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struct cpu_branch_cost
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{
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const int predictable; /* Predictable branch or optimizing for size. */
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const int unpredictable; /* Unpredictable branch or optimizing for speed. */
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};
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struct tune_params
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{
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const struct cpu_cost_table *const insn_extra_cost;
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const struct cpu_addrcost_table *const addr_cost;
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const struct cpu_regmove_cost *const regmove_cost;
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const struct cpu_vector_cost *const vec_costs;
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const struct cpu_branch_cost *const branch_costs;
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const int memmov_cost;
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const int issue_rate;
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const unsigned int fuseable_ops;
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@ -184,6 +192,7 @@ struct tune_params
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HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned);
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int aarch64_get_condition_code (rtx);
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bool aarch64_bitmask_imm (HOST_WIDE_INT val, machine_mode);
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int aarch64_branch_cost (bool, bool);
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enum aarch64_symbol_type
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aarch64_classify_symbolic_expression (rtx, enum aarch64_symbol_context);
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bool aarch64_const_vec_all_same_int_p (rtx, HOST_WIDE_INT);
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@ -340,12 +340,20 @@ static const struct cpu_vector_cost xgene1_vector_cost =
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#define AARCH64_FUSE_ADRP_LDR (1 << 3)
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#define AARCH64_FUSE_CMP_BRANCH (1 << 4)
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/* Generic costs for branch instructions. */
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static const struct cpu_branch_cost generic_branch_cost =
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{
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2, /* Predictable. */
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2 /* Unpredictable. */
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};
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static const struct tune_params generic_tunings =
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{
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&cortexa57_extra_costs,
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&generic_addrcost_table,
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&generic_regmove_cost,
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&generic_vector_cost,
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&generic_branch_cost,
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4, /* memmov_cost */
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2, /* issue_rate */
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AARCH64_FUSE_NOTHING, /* fuseable_ops */
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@ -365,6 +373,7 @@ static const struct tune_params cortexa53_tunings =
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&generic_addrcost_table,
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&cortexa53_regmove_cost,
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&generic_vector_cost,
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&generic_branch_cost,
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4, /* memmov_cost */
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2, /* issue_rate */
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(AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
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@ -385,6 +394,7 @@ static const struct tune_params cortexa57_tunings =
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&cortexa57_addrcost_table,
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&cortexa57_regmove_cost,
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&cortexa57_vector_cost,
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&generic_branch_cost,
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4, /* memmov_cost */
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3, /* issue_rate */
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(AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD
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@ -405,6 +415,7 @@ static const struct tune_params thunderx_tunings =
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&generic_addrcost_table,
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&thunderx_regmove_cost,
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&generic_vector_cost,
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&generic_branch_cost,
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6, /* memmov_cost */
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2, /* issue_rate */
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AARCH64_FUSE_CMP_BRANCH, /* fuseable_ops */
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@ -424,6 +435,7 @@ static const struct tune_params xgene1_tunings =
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&xgene1_addrcost_table,
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&xgene1_regmove_cost,
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&xgene1_vector_cost,
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&generic_branch_cost,
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6, /* memmov_cost */
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4, /* issue_rate */
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AARCH64_FUSE_NOTHING, /* fuseable_ops */
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@ -5409,6 +5421,23 @@ aarch64_address_cost (rtx x,
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return cost;
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}
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/* Return the cost of a branch. If SPEED_P is true then the compiler is
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optimizing for speed. If PREDICTABLE_P is true then the branch is predicted
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to be taken. */
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int
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aarch64_branch_cost (bool speed_p, bool predictable_p)
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{
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/* When optimizing for speed, use the cost of unpredictable branches. */
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const struct cpu_branch_cost *branch_costs =
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aarch64_tune_params->branch_costs;
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if (!speed_p || predictable_p)
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return branch_costs->predictable;
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else
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return branch_costs->unpredictable;
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}
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/* Return true if the RTX X in mode MODE is a zero or sign extract
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usable in an ADD or SUB (extended register) instruction. */
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static bool
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@ -827,7 +827,8 @@ do { \
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#define TRAMPOLINE_SECTION text_section
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/* To start with. */
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#define BRANCH_COST(SPEED_P, PREDICTABLE_P) 2
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#define BRANCH_COST(SPEED_P, PREDICTABLE_P) \
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(aarch64_branch_cost (SPEED_P, PREDICTABLE_P))
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/* Assembly output. */
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