recog.c (store_data_bypass_p, [...]): New.
* recog.c (store_data_bypass_p, if_test_bypass_p): New. * recog.h: Declare them. * config/sparc/sparc.c (ultrasparc_store_bypass_p): Remove. * config/sparc/sparc.md: Use store_data_bypass_p instead. * config/sparc/sparc-protos.h: Update. From-SVN: r53132
This commit is contained in:
parent
e1c1132e0b
commit
b37c26149f
6 changed files with 71 additions and 73 deletions
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@ -1,3 +1,12 @@
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2002-05-03 Richard Henderson <rth@redhat.com>
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* recog.c (store_data_bypass_p, if_test_bypass_p): New.
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* recog.h: Declare them.
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* config/sparc/sparc.c (ultrasparc_store_bypass_p): Remove.
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* config/sparc/sparc.md: Use store_data_bypass_p instead.
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* config/sparc/sparc-protos.h: Update.
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2002-05-03 Jason Thorpe <thorpej@wasabisystems.com>
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* config/sparc/netbsd-elf.c (CPP_SUBTARGET_SPEC64): Remove
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@ -120,8 +120,6 @@ extern char *sparc_v8plus_shift PARAMS ((rtx *, rtx, const char *));
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32 bits of REG are 0 before INSN. */
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extern int sparc_check_64 PARAMS ((rtx, rtx));
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extern rtx gen_df_reg PARAMS ((rtx, int));
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/* Used for DFA scheduling when cpu is ultrasparc. */
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extern int ultrasparc_store_bypass_p PARAMS ((rtx, rtx));
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extern int sparc_extra_constraint_check PARAMS ((rtx, int, int));
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#endif /* RTX_CODE */
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@ -7701,75 +7701,6 @@ sparc_cycle_display (clock, last)
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return last;
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}
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/* Make sure that the dependency between OUT_INSN and
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IN_INSN (a store) is on the store data not the address
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operand(s) of the store. */
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int
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ultrasparc_store_bypass_p (out_insn, in_insn)
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rtx out_insn, in_insn;
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{
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rtx out_pat, in_pat;
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unsigned int regno;
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if (recog_memoized (in_insn) < 0)
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return 0;
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if (get_attr_type (in_insn) != TYPE_STORE
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&& get_attr_type (in_insn) != TYPE_FPSTORE)
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abort ();
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out_pat = PATTERN (out_insn);
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in_pat = PATTERN (in_insn);
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if ((GET_CODE (out_pat) != SET
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&& GET_CODE (out_pat) != PARALLEL)
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|| GET_CODE (in_pat) != SET)
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abort ();
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if (GET_CODE (SET_SRC (in_pat)) == REG)
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{
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regno = REGNO (SET_SRC (in_pat));
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}
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else if (GET_CODE (SET_SRC (in_pat)) == SUBREG)
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{
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regno = REGNO (SUBREG_REG (SET_SRC (in_pat)));
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}
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else
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return 0;
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if (GET_CODE (out_pat) == PARALLEL)
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{
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int i;
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for (i = 0; i < XVECLEN (out_pat, 0); i++)
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{
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rtx exp = XVECEXP (out_pat, 0, i);
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if (GET_CODE (exp) != SET)
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return 0;
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if (GET_CODE (SET_DEST (exp)) == REG
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&& regno == REGNO (SET_DEST (exp)))
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return 1;
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if (GET_CODE (SET_DEST (exp)) == SUBREG
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&& regno == REGNO (SUBREG_REG (SET_DEST (exp))))
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return 1;
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}
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}
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else if (GET_CODE (SET_DEST (out_pat)) == REG)
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{
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return regno == REGNO (SET_DEST (out_pat));
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}
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else if (GET_CODE (SET_DEST (out_pat)) == SUBREG)
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{
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return regno == REGNO (SUBREG_REG (SET_DEST (out_pat)));
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}
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return 0;
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}
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static int
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sparc_issue_rate ()
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{
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@ -624,7 +624,7 @@
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;; We need a special guard function because this bypass does
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;; not apply to the address inputs of the store.
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(define_bypass 0 "us1_simple_ieuN,us1_simple_ieu1,us1_simple_ieu0,us1_faddsub_single,us1_faddsub_double,us1_fmov_single,us1_fmov_double,us1_fcmov_single,us1_fcmov_double,us1_fmult_single,us1_fmult_double" "us1_store"
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"ultrasparc_store_bypass_p")
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"store_data_bypass_p")
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;; An integer branch may execute in the same cycle as the compare
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;; creating the condition codes.
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;; We need a special guard function because this bypass does
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;; not apply to the address inputs of the store.
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(define_bypass 0 "us3_integer,us3_faddsub,us3_fmov,us3_fcmov,us3_fmult" "us3_store"
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"ultrasparc_store_bypass_p")
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"store_data_bypass_p")
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;; An integer branch may execute in the same cycle as the compare
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;; creating the condition codes.
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57
gcc/recog.c
57
gcc/recog.c
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@ -3275,3 +3275,60 @@ peephole2_optimize (dump_file)
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#endif
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}
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#endif /* HAVE_peephole2 */
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/* Common predicates for use with define_bypass. */
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/* True if the dependency between OUT_INSN and IN_INSN is on the store
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data not the address operand(s) of the store. Both OUT_INSN and IN_INSN
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must be single_set. */
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int
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store_data_bypass_p (out_insn, in_insn)
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rtx out_insn, in_insn;
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{
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rtx out_set, in_set;
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out_set = single_set (out_insn);
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if (! out_set)
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abort ();
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in_set = single_set (in_insn);
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if (! in_set)
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abort ();
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if (GET_CODE (SET_DEST (in_set)) != MEM)
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return false;
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if (reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_set)))
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return false;
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return true;
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}
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/* True if the dependency between OUT_INSN and IN_INSN is in the
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IF_THEN_ELSE condition, and not the THEN or ELSE branch.
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Both OUT_INSN and IN_INSN must be single_set. */
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int
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if_test_bypass_p (out_insn, in_insn)
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rtx out_insn, in_insn;
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{
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rtx out_set, in_set;
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out_set = single_set (out_insn);
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if (! out_set)
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abort ();
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in_set = single_set (in_insn);
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if (! in_set)
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abort ();
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if (GET_CODE (SET_SRC (in_set)) != IF_THEN_ELSE)
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return false;
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if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1))
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|| reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2)))
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return false;
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return true;
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}
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@ -137,6 +137,9 @@ extern rtx peep2_find_free_register PARAMS ((int, int, const char *,
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extern void peephole2_optimize PARAMS ((FILE *));
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extern rtx peephole2_insns PARAMS ((rtx, rtx, int *));
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extern int store_data_bypass_p PARAMS ((rtx, rtx));
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extern int if_test_bypass_p PARAMS ((rtx, rtx));
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/* Nonzero means volatile operands are recognized. */
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extern int volatile_ok;
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