mips.h (MASK_DEBUG_C, [...]): Delete.
* config/mips/mips.h (MASK_DEBUG_C, TARGET_DEBUG_C_MODE): Delete. (TARGET_SWITCHES): Remove -mdebugc. * config/mips/mips.md (seq, sne, sgt, sge, slt, sle, sgtu, sgeu) (sltu, sleu): Remove TARGET_DEBUG_C_MODE handling. (seq_[sd]i, sne_[sd]i, sge_[sd]i, sle_[sd]i_reg, sgeu_[sd]i) (sle_[sd]i_reg): Delete. From-SVN: r84095
This commit is contained in:
Richard Sandiford
Richard Sandiford
parent
78c2120290
commit
b3583df693
3 changed files with 29 additions and 426 deletions
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@ -1,3 +1,12 @@
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2004-07-04 Richard Sandiford <rsandifo@redhat.com>
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* config/mips/mips.h (MASK_DEBUG_C, TARGET_DEBUG_C_MODE): Delete.
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(TARGET_SWITCHES): Remove -mdebugc.
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* config/mips/mips.md (seq, sne, sgt, sge, slt, sle, sgtu, sgeu)
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(sltu, sleu): Remove TARGET_DEBUG_C_MODE handling.
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(seq_[sd]i, sne_[sd]i, sge_[sd]i, sle_[sd]i_reg, sgeu_[sd]i)
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(sle_[sd]i_reg): Delete.
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2004-07-04 Steven Bosscher <stevenb@suse.de>
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* config/iq2000/iq2000.c (TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE):
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@ -176,7 +176,6 @@ extern const struct mips_cpu_info *mips_tune_info;
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/* Debug switches, not documented */
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#define MASK_DEBUG 0 /* unused */
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#define MASK_DEBUG_C 0 /* don't expand seq, etc. */
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#define MASK_DEBUG_D 0 /* don't do define_split's */
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/* Dummy switches used only in specs */
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@ -197,7 +196,6 @@ extern const struct mips_cpu_info *mips_tune_info;
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/* Debug Modes */
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#define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
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#define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
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#define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
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/* Reg. Naming in .s ($21 vs. $a0) */
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@ -672,8 +670,6 @@ extern const struct mips_cpu_info *mips_tune_info;
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N_("FP exceptions are not enabled") }, \
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{"debug", MASK_DEBUG, \
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NULL}, \
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{"debugc", MASK_DEBUG_C, \
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NULL}, \
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{"debugd", MASK_DEBUG_D, \
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NULL}, \
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{"", (TARGET_DEFAULT \
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@ -6318,20 +6318,8 @@ dsrl\t%3,%3,1\n\
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if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
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FAIL;
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/* Set up operands from compare. */
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operands[1] = branch_cmp[0];
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operands[2] = branch_cmp[1];
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if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
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{
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gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0);
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DONE;
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}
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if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
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operands[2] = force_reg (SImode, operands[2]);
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/* Fall through and generate default code. */
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gen_int_relational (EQ, operands[0], branch_cmp[0], branch_cmp[1], NULL);
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DONE;
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})
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@ -6371,59 +6359,6 @@ dsrl\t%3,%3,1\n\
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[(set_attr "type" "slt")
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(set_attr "mode" "DI")])
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(define_insn "seq_si"
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[(set (match_operand:SI 0 "register_operand" "=d,d")
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(eq:SI (match_operand:SI 1 "register_operand" "%d,d")
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(match_operand:SI 2 "uns_arith_operand" "d,K")))]
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"TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
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"@
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xor\t%0,%1,%2\;sltu\t%0,%0,1
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xori\t%0,%1,%2\;sltu\t%0,%0,1"
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[(set_attr "type" "multi")
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(set_attr "mode" "SI")
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(set_attr "length" "8")])
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(define_split
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[(set (match_operand:SI 0 "register_operand")
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(eq:SI (match_operand:SI 1 "register_operand")
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(match_operand:SI 2 "uns_arith_operand")))]
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"TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
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&& (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
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[(set (match_dup 0)
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(xor:SI (match_dup 1)
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(match_dup 2)))
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(set (match_dup 0)
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(ltu:SI (match_dup 0)
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(const_int 1)))]
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"")
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(define_insn "seq_di"
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[(set (match_operand:DI 0 "register_operand" "=d,d")
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(eq:DI (match_operand:DI 1 "register_operand" "%d,d")
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(match_operand:DI 2 "uns_arith_operand" "d,K")))]
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"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
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"@
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xor\t%0,%1,%2\;sltu\t%0,%0,1
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xori\t%0,%1,%2\;sltu\t%0,%0,1"
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[(set_attr "type" "multi")
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(set_attr "mode" "DI")
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(set_attr "length" "8")])
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(define_split
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[(set (match_operand:DI 0 "register_operand")
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(eq:DI (match_operand:DI 1 "register_operand")
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(match_operand:DI 2 "uns_arith_operand")))]
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"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
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&& !TARGET_MIPS16
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&& (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
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[(set (match_dup 0)
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(xor:DI (match_dup 1)
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(match_dup 2)))
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(set (match_dup 0)
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(ltu:DI (match_dup 0)
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(const_int 1)))]
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"")
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;; On the mips16 the default code is better than using sltu.
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(define_expand "sne"
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@ -6435,20 +6370,8 @@ dsrl\t%3,%3,1\n\
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if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
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FAIL;
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/* Set up operands from compare. */
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operands[1] = branch_cmp[0];
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operands[2] = branch_cmp[1];
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if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
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{
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gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0);
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DONE;
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}
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if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
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operands[2] = force_reg (SImode, operands[2]);
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/* Fall through and generate default code. */
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gen_int_relational (NE, operands[0], branch_cmp[0], branch_cmp[1], NULL);
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DONE;
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})
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(define_insn "sne_si_zero"
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@ -6469,59 +6392,6 @@ dsrl\t%3,%3,1\n\
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[(set_attr "type" "slt")
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(set_attr "mode" "DI")])
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(define_insn "sne_si"
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[(set (match_operand:SI 0 "register_operand" "=d,d")
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(ne:SI (match_operand:SI 1 "register_operand" "%d,d")
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(match_operand:SI 2 "uns_arith_operand" "d,K")))]
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"TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
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"@
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xor\t%0,%1,%2\;sltu\t%0,%.,%0
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xori\t%0,%1,%x2\;sltu\t%0,%.,%0"
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[(set_attr "type" "multi")
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(set_attr "mode" "SI")
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(set_attr "length" "8")])
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(define_split
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[(set (match_operand:SI 0 "register_operand")
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(ne:SI (match_operand:SI 1 "register_operand")
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(match_operand:SI 2 "uns_arith_operand")))]
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"TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
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&& (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
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[(set (match_dup 0)
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(xor:SI (match_dup 1)
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(match_dup 2)))
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(set (match_dup 0)
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(gtu:SI (match_dup 0)
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(const_int 0)))]
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"")
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(define_insn "sne_di"
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[(set (match_operand:DI 0 "register_operand" "=d,d")
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(ne:DI (match_operand:DI 1 "register_operand" "%d,d")
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(match_operand:DI 2 "uns_arith_operand" "d,K")))]
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"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
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"@
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xor\t%0,%1,%2\;sltu\t%0,%.,%0
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xori\t%0,%1,%x2\;sltu\t%0,%.,%0"
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[(set_attr "type" "multi")
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(set_attr "mode" "DI")
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(set_attr "length" "8")])
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(define_split
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[(set (match_operand:DI 0 "register_operand")
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(ne:DI (match_operand:DI 1 "register_operand")
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(match_operand:DI 2 "uns_arith_operand")))]
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"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
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&& !TARGET_MIPS16
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&& (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
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[(set (match_dup 0)
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(xor:DI (match_dup 1)
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(match_dup 2)))
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(set (match_dup 0)
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(gtu:DI (match_dup 0)
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(const_int 0)))]
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"")
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(define_expand "sgt"
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[(set (match_operand:SI 0 "register_operand")
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(gt:SI (match_dup 1)
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@ -6531,20 +6401,8 @@ dsrl\t%3,%3,1\n\
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if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
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FAIL;
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/* Set up operands from compare. */
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operands[1] = branch_cmp[0];
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operands[2] = branch_cmp[1];
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if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
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{
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gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0);
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DONE;
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}
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if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
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operands[2] = force_reg (SImode, operands[2]);
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/* Fall through and generate default code. */
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gen_int_relational (GT, operands[0], branch_cmp[0], branch_cmp[1], NULL);
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DONE;
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})
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(define_insn "sgt_si"
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@ -6592,66 +6450,10 @@ dsrl\t%3,%3,1\n\
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if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
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FAIL;
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/* Set up operands from compare. */
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operands[1] = branch_cmp[0];
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operands[2] = branch_cmp[1];
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if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
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{
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gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0);
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DONE;
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}
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/* Fall through and generate default code. */
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gen_int_relational (GE, operands[0], branch_cmp[0], branch_cmp[1], NULL);
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DONE;
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})
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(define_insn "sge_si"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(ge:SI (match_operand:SI 1 "register_operand" "d")
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(match_operand:SI 2 "arith_operand" "dI")))]
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"TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
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"slt\t%0,%1,%2\;xori\t%0,%0,0x0001"
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[(set_attr "type" "multi")
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(set_attr "mode" "SI")
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(set_attr "length" "8")])
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(define_split
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[(set (match_operand:SI 0 "register_operand")
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(ge:SI (match_operand:SI 1 "register_operand")
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(match_operand:SI 2 "arith_operand")))]
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"TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
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[(set (match_dup 0)
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(lt:SI (match_dup 1)
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(match_dup 2)))
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(set (match_dup 0)
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(xor:SI (match_dup 0)
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(const_int 1)))]
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"")
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(define_insn "sge_di"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(ge:DI (match_operand:DI 1 "register_operand" "d")
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(match_operand:DI 2 "arith_operand" "dI")))]
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"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
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"slt\t%0,%1,%2\;xori\t%0,%0,0x0001"
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[(set_attr "type" "multi")
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(set_attr "mode" "DI")
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(set_attr "length" "8")])
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(define_split
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[(set (match_operand:DI 0 "register_operand")
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(ge:DI (match_operand:DI 1 "register_operand")
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(match_operand:DI 2 "arith_operand")))]
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"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
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&& !TARGET_MIPS16"
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[(set (match_dup 0)
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(lt:DI (match_dup 1)
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(match_dup 2)))
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(set (match_dup 0)
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(xor:DI (match_dup 0)
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(const_int 1)))]
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"")
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(define_expand "slt"
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[(set (match_operand:SI 0 "register_operand")
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(lt:SI (match_dup 1)
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@ -6661,17 +6463,8 @@ dsrl\t%3,%3,1\n\
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if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
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FAIL;
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/* Set up operands from compare. */
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operands[1] = branch_cmp[0];
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operands[2] = branch_cmp[1];
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if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
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{
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gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0);
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DONE;
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}
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/* Fall through and generate default code. */
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gen_int_relational (LT, operands[0], branch_cmp[0], branch_cmp[1], NULL);
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DONE;
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})
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(define_insn "slt_si"
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@ -6729,20 +6522,8 @@ dsrl\t%3,%3,1\n\
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if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
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FAIL;
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/* Set up operands from compare. */
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operands[1] = branch_cmp[0];
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operands[2] = branch_cmp[1];
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if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
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{
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gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0);
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DONE;
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}
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if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
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operands[2] = force_reg (SImode, operands[2]);
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/* Fall through and generate default code. */
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gen_int_relational (LE, operands[0], branch_cmp[0], branch_cmp[1], NULL);
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DONE;
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||||
})
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(define_insn "sle_si_const"
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|
@ -6799,53 +6580,6 @@ dsrl\t%3,%3,1\n\
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(const_int 4)
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(const_int 8)))])
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(define_insn "sle_si_reg"
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[(set (match_operand:SI 0 "register_operand" "=d")
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(le:SI (match_operand:SI 1 "register_operand" "d")
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(match_operand:SI 2 "register_operand" "d")))]
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"TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
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"slt\t%0,%z2,%1\;xori\t%0,%0,0x0001"
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[(set_attr "type" "multi")
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(set_attr "mode" "SI")
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||||
(set_attr "length" "8")])
|
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|
||||
(define_split
|
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[(set (match_operand:SI 0 "register_operand")
|
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(le:SI (match_operand:SI 1 "register_operand")
|
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(match_operand:SI 2 "register_operand")))]
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"TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
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[(set (match_dup 0)
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(lt:SI (match_dup 2)
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(match_dup 1)))
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(set (match_dup 0)
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(xor:SI (match_dup 0)
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(const_int 1)))]
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"")
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(define_insn "sle_di_reg"
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[(set (match_operand:DI 0 "register_operand" "=d")
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(le:DI (match_operand:DI 1 "register_operand" "d")
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(match_operand:DI 2 "register_operand" "d")))]
|
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"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
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"slt\t%0,%z2,%1\;xori\t%0,%0,0x0001"
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[(set_attr "type" "multi")
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(set_attr "mode" "DI")
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(set_attr "length" "8")])
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|
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(define_split
|
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[(set (match_operand:DI 0 "register_operand")
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(le:DI (match_operand:DI 1 "register_operand")
|
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(match_operand:DI 2 "register_operand")))]
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"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
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&& !TARGET_MIPS16"
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[(set (match_dup 0)
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(lt:DI (match_dup 2)
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(match_dup 1)))
|
||||
(set (match_dup 0)
|
||||
(xor:DI (match_dup 0)
|
||||
(const_int 1)))]
|
||||
"")
|
||||
|
||||
(define_expand "sgtu"
|
||||
[(set (match_operand:SI 0 "register_operand")
|
||||
(gtu:SI (match_dup 1)
|
||||
|
|
@ -6855,20 +6589,8 @@ dsrl\t%3,%3,1\n\
|
|||
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
|
||||
FAIL;
|
||||
|
||||
/* Set up operands from compare. */
|
||||
operands[1] = branch_cmp[0];
|
||||
operands[2] = branch_cmp[1];
|
||||
|
||||
if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
|
||||
{
|
||||
gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0);
|
||||
DONE;
|
||||
}
|
||||
|
||||
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
|
||||
operands[2] = force_reg (SImode, operands[2]);
|
||||
|
||||
/* Fall through and generate default code. */
|
||||
gen_int_relational (GTU, operands[0], branch_cmp[0], branch_cmp[1], NULL);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_insn "sgtu_si"
|
||||
|
|
@ -6916,66 +6638,10 @@ dsrl\t%3,%3,1\n\
|
|||
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
|
||||
FAIL;
|
||||
|
||||
/* Set up operands from compare. */
|
||||
operands[1] = branch_cmp[0];
|
||||
operands[2] = branch_cmp[1];
|
||||
|
||||
if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
|
||||
{
|
||||
gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0);
|
||||
DONE;
|
||||
}
|
||||
|
||||
/* Fall through and generate default code. */
|
||||
gen_int_relational (GEU, operands[0], branch_cmp[0], branch_cmp[1], NULL);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_insn "sgeu_si"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(geu:SI (match_operand:SI 1 "register_operand" "d")
|
||||
(match_operand:SI 2 "arith_operand" "dI")))]
|
||||
"TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
|
||||
"sltu\t%0,%1,%2\;xori\t%0,%0,0x0001"
|
||||
[(set_attr "type" "multi")
|
||||
(set_attr "mode" "SI")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:SI 0 "register_operand")
|
||||
(geu:SI (match_operand:SI 1 "register_operand")
|
||||
(match_operand:SI 2 "arith_operand")))]
|
||||
"TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
|
||||
[(set (match_dup 0)
|
||||
(ltu:SI (match_dup 1)
|
||||
(match_dup 2)))
|
||||
(set (match_dup 0)
|
||||
(xor:SI (match_dup 0)
|
||||
(const_int 1)))]
|
||||
"")
|
||||
|
||||
(define_insn "sgeu_di"
|
||||
[(set (match_operand:DI 0 "register_operand" "=d")
|
||||
(geu:DI (match_operand:DI 1 "register_operand" "d")
|
||||
(match_operand:DI 2 "arith_operand" "dI")))]
|
||||
"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
|
||||
"sltu\t%0,%1,%2\;xori\t%0,%0,0x0001"
|
||||
[(set_attr "type" "multi")
|
||||
(set_attr "mode" "DI")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DI 0 "register_operand")
|
||||
(geu:DI (match_operand:DI 1 "register_operand")
|
||||
(match_operand:DI 2 "arith_operand")))]
|
||||
"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
|
||||
&& !TARGET_MIPS16"
|
||||
[(set (match_dup 0)
|
||||
(ltu:DI (match_dup 1)
|
||||
(match_dup 2)))
|
||||
(set (match_dup 0)
|
||||
(xor:DI (match_dup 0)
|
||||
(const_int 1)))]
|
||||
"")
|
||||
|
||||
(define_expand "sltu"
|
||||
[(set (match_operand:SI 0 "register_operand")
|
||||
(ltu:SI (match_dup 1)
|
||||
|
|
@ -6985,17 +6651,8 @@ dsrl\t%3,%3,1\n\
|
|||
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
|
||||
FAIL;
|
||||
|
||||
/* Set up operands from compare. */
|
||||
operands[1] = branch_cmp[0];
|
||||
operands[2] = branch_cmp[1];
|
||||
|
||||
if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
|
||||
{
|
||||
gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0);
|
||||
DONE;
|
||||
}
|
||||
|
||||
/* Fall through and generate default code. */
|
||||
gen_int_relational (LTU, operands[0], branch_cmp[0], branch_cmp[1], NULL);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_insn "sltu_si"
|
||||
|
|
@ -7053,20 +6710,8 @@ dsrl\t%3,%3,1\n\
|
|||
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
|
||||
FAIL;
|
||||
|
||||
/* Set up operands from compare. */
|
||||
operands[1] = branch_cmp[0];
|
||||
operands[2] = branch_cmp[1];
|
||||
|
||||
if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
|
||||
{
|
||||
gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0);
|
||||
DONE;
|
||||
}
|
||||
|
||||
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
|
||||
operands[2] = force_reg (SImode, operands[2]);
|
||||
|
||||
/* Fall through and generate default code. */
|
||||
gen_int_relational (LEU, operands[0], branch_cmp[0], branch_cmp[1], NULL);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_insn "sleu_si_const"
|
||||
|
|
@ -7122,53 +6767,6 @@ dsrl\t%3,%3,1\n\
|
|||
(set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1")
|
||||
(const_int 4)
|
||||
(const_int 8)))])
|
||||
|
||||
(define_insn "sleu_si_reg"
|
||||
[(set (match_operand:SI 0 "register_operand" "=d")
|
||||
(leu:SI (match_operand:SI 1 "register_operand" "d")
|
||||
(match_operand:SI 2 "register_operand" "d")))]
|
||||
"TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
|
||||
"sltu\t%0,%z2,%1\;xori\t%0,%0,0x0001"
|
||||
[(set_attr "type" "multi")
|
||||
(set_attr "mode" "SI")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:SI 0 "register_operand")
|
||||
(leu:SI (match_operand:SI 1 "register_operand")
|
||||
(match_operand:SI 2 "register_operand")))]
|
||||
"TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
|
||||
[(set (match_dup 0)
|
||||
(ltu:SI (match_dup 2)
|
||||
(match_dup 1)))
|
||||
(set (match_dup 0)
|
||||
(xor:SI (match_dup 0)
|
||||
(const_int 1)))]
|
||||
"")
|
||||
|
||||
(define_insn "sleu_di_reg"
|
||||
[(set (match_operand:DI 0 "register_operand" "=d")
|
||||
(leu:DI (match_operand:DI 1 "register_operand" "d")
|
||||
(match_operand:DI 2 "register_operand" "d")))]
|
||||
"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
|
||||
"sltu\t%0,%z2,%1\;xori\t%0,%0,0x0001"
|
||||
[(set_attr "type" "multi")
|
||||
(set_attr "mode" "DI")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand:DI 0 "register_operand")
|
||||
(leu:DI (match_operand:DI 1 "register_operand")
|
||||
(match_operand:DI 2 "register_operand")))]
|
||||
"TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
|
||||
&& !TARGET_MIPS16"
|
||||
[(set (match_dup 0)
|
||||
(ltu:DI (match_dup 2)
|
||||
(match_dup 1)))
|
||||
(set (match_dup 0)
|
||||
(xor:DI (match_dup 0)
|
||||
(const_int 1)))]
|
||||
"")
|
||||
|
||||
;;
|
||||
;; ....................
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue