FreeChainXenon/gcc
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mips.h (ISA_HAS_LL_SC): Exclude TARGET_MIPS5900.

Browse source 
gcc/
2013-06-16  Jürgen Urban  <JuergenUrban@gmx.de>

	* config/mips/mips.h (ISA_HAS_LL_SC): Exclude TARGET_MIPS5900.
	* config/mips/mips.c (mips_start_ll_sc_sync_block): Output
	".set mips3" for 64-bit targets.

From-SVN: r200132
This commit is contained in:
Jürgen Urban 2013-06-16 09:16:23 +00:00 • committed by Richard Sandiford
parent 6f9c34459e
commit b259d352ca
3 changed files with 11 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
gcc/ChangeLog
View file

@ -1,3 +1,9 @@
2013-06-16 Jürgen Urban <JuergenUrban@gmx.de>
* config/mips/mips.h (ISA_HAS_LL_SC): Exclude TARGET_MIPS5900.
* config/mips/mips.c (mips_start_ll_sc_sync_block): Output
".set mips3" for 64-bit targets.
2013-06-15 Dehao Chen <dehao@google.com>
* tree-flow.h (gimple_check_call_matching_types): Add new argument.

5
gcc/config/mips/mips.c
View file

@ -12463,7 +12463,10 @@ mips_start_ll_sc_sync_block (void)
if (!ISA_HAS_LL_SC)
{
output_asm_insn (".set\tpush", 0);
output_asm_insn (".set\tmips2", 0);
if (TARGET_64BIT)
output_asm_insn (".set\tmips3", 0);
else
output_asm_insn (".set\tmips2", 0);
}
}

2
gcc/config/mips/mips.h
View file

@ -1063,7 +1063,7 @@ struct mips_cpu_info {
/* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC
because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC
instructions. */
#define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS16)
#define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16)
#define GENERATE_LL_SC \
(target_flags_explicit & MASK_LLSC \
? TARGET_LLSC && !TARGET_MIPS16 \