[Patch AArch64 3/4] De-const-ify struct tune_params
gcc/ * config/aarch64/aarch64-protos.h (tune_params): Remove const from members. (aarch64_tune_params): Remove const, change to no longer be a pointer. * config/aarch64/aarch64.c (aarch64_tune_params): Remove const, change to no longer be a pointer, initialize to generic_tunings. (aarch64_min_divisions_for_recip_mul): Change dereference of aarch64_tune_params to member access. (aarch64_reassociation_width): Likewise. (aarch64_rtx_mult_cost): Likewise. (aarch64_address_cost): Likewise. (aarch64_branch_cost): Likewise. (aarch64_rtx_costs): Likewise. (aarch64_register_move_cost): Likewise. (aarch64_memory_move_cost): Likewise. (aarch64_sched_issue_rate): Likewise. (aarch64_builtin_vectorization_cost): Likewise. (aarch64_override_options): Take a copy of the selected tuning struct in to aarch64_tune_params, rather than just setting a pointer, change dereferences of aarch64_tune_params to member accesses. (aarch64_override_options_after_change): Change dereferences of aarch64_tune_params to member access. (aarch64_macro_fusion_p): Likewise. (aarch_macro_fusion_pair_p): Likewise. * config/aarch64/cortex-a57-fma-steering.c (gate): Likewise. From-SVN: r225016
This commit is contained in:
James Greenhalgh
James Greenhalgh
parent
dfba575ff3
commit
b175b679a4
4 changed files with 88 additions and 57 deletions
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@ -1,3 +1,32 @@
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2015-06-26 James Greenhalgh <james.greenhalgh@arm.com>
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* config/aarch64/aarch64-protos.h (tune_params): Remove
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const from members.
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(aarch64_tune_params): Remove const, change to no longer be
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a pointer.
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* config/aarch64/aarch64.c (aarch64_tune_params): Remove const,
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change to no longer be a pointer, initialize to generic_tunings.
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(aarch64_min_divisions_for_recip_mul): Change dereference of
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aarch64_tune_params to member access.
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(aarch64_reassociation_width): Likewise.
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(aarch64_rtx_mult_cost): Likewise.
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(aarch64_address_cost): Likewise.
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(aarch64_branch_cost): Likewise.
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(aarch64_rtx_costs): Likewise.
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(aarch64_register_move_cost): Likewise.
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(aarch64_memory_move_cost): Likewise.
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(aarch64_sched_issue_rate): Likewise.
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(aarch64_builtin_vectorization_cost): Likewise.
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(aarch64_override_options): Take a copy of the selected tuning
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struct in to aarch64_tune_params, rather than just setting
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a pointer, change dereferences of aarch64_tune_params to member
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accesses.
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(aarch64_override_options_after_change): Change dereferences of
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aarch64_tune_params to member access.
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(aarch64_macro_fusion_p): Likewise.
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(aarch_macro_fusion_pair_p): Likewise.
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* config/aarch64/cortex-a57-fma-steering.c (gate): Likewise.
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2015-06-26 James Greenhalgh <james.greenhalgh@arm.com>
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* config/aarch64/aarch64.h (AARCH64_FL_USE_FMA_STEERING_PASS): Delete.
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@ -172,23 +172,23 @@ struct cpu_branch_cost
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struct tune_params
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{
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const struct cpu_cost_table *const insn_extra_cost;
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const struct cpu_addrcost_table *const addr_cost;
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const struct cpu_regmove_cost *const regmove_cost;
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const struct cpu_vector_cost *const vec_costs;
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const struct cpu_branch_cost *const branch_costs;
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const int memmov_cost;
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const int issue_rate;
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const unsigned int fusible_ops;
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const int function_align;
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const int jump_align;
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const int loop_align;
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const int int_reassoc_width;
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const int fp_reassoc_width;
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const int vec_reassoc_width;
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const int min_div_recip_mul_sf;
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const int min_div_recip_mul_df;
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const unsigned int extra_tuning_flags;
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const struct cpu_cost_table *insn_extra_cost;
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const struct cpu_addrcost_table *addr_cost;
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const struct cpu_regmove_cost *regmove_cost;
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const struct cpu_vector_cost *vec_costs;
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const struct cpu_branch_cost *branch_costs;
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int memmov_cost;
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int issue_rate;
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unsigned int fusible_ops;
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int function_align;
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int jump_align;
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int loop_align;
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int int_reassoc_width;
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int fp_reassoc_width;
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int vec_reassoc_width;
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int min_div_recip_mul_sf;
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int min_div_recip_mul_df;
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unsigned int extra_tuning_flags;
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};
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#define AARCH64_FUSION_PAIR(x, name, index) \
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@ -229,7 +229,7 @@ enum aarch64_extra_tuning_flags
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};
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#undef AARCH64_EXTRA_TUNING_OPTION
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extern const struct tune_params *aarch64_tune_params;
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extern struct tune_params aarch64_tune_params;
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HOST_WIDE_INT aarch64_initial_elimination_offset (unsigned, unsigned);
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int aarch64_get_condition_code (rtx);
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@ -166,9 +166,6 @@ unsigned aarch64_architecture_version;
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/* The processor for which instructions should be scheduled. */
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enum aarch64_processor aarch64_tune = cortexa53;
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/* The current tuning set. */
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const struct tune_params *aarch64_tune_params;
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/* Mask to specify which instructions we are allowed to generate. */
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unsigned long aarch64_isa_flags = 0;
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@ -495,6 +492,9 @@ static const struct processor *selected_arch;
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static const struct processor *selected_cpu;
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static const struct processor *selected_tune;
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/* The current tuning set. */
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struct tune_params aarch64_tune_params = generic_tunings;
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#define AARCH64_CPU_DEFAULT_FLAGS ((selected_cpu) ? selected_cpu->flags : 0)
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/* An ISA extension in the co-processor and main instruction set space. */
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@ -556,8 +556,8 @@ static unsigned int
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aarch64_min_divisions_for_recip_mul (enum machine_mode mode)
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{
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if (GET_MODE_UNIT_SIZE (mode) == 4)
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return aarch64_tune_params->min_div_recip_mul_sf;
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return aarch64_tune_params->min_div_recip_mul_df;
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return aarch64_tune_params.min_div_recip_mul_sf;
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return aarch64_tune_params.min_div_recip_mul_df;
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}
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static int
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@ -565,11 +565,11 @@ aarch64_reassociation_width (unsigned opc ATTRIBUTE_UNUSED,
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enum machine_mode mode)
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{
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if (VECTOR_MODE_P (mode))
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return aarch64_tune_params->vec_reassoc_width;
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return aarch64_tune_params.vec_reassoc_width;
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if (INTEGRAL_MODE_P (mode))
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return aarch64_tune_params->int_reassoc_width;
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return aarch64_tune_params.int_reassoc_width;
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if (FLOAT_MODE_P (mode))
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return aarch64_tune_params->fp_reassoc_width;
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return aarch64_tune_params.fp_reassoc_width;
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return 1;
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}
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@ -5230,7 +5230,7 @@ aarch64_rtx_mult_cost (rtx x, int code, int outer, bool speed)
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{
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rtx op0, op1;
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const struct cpu_cost_table *extra_cost
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= aarch64_tune_params->insn_extra_cost;
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= aarch64_tune_params.insn_extra_cost;
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int cost = 0;
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bool compound_p = (outer == PLUS || outer == MINUS);
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machine_mode mode = GET_MODE (x);
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@ -5362,7 +5362,7 @@ aarch64_address_cost (rtx x,
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bool speed)
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{
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enum rtx_code c = GET_CODE (x);
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const struct cpu_addrcost_table *addr_cost = aarch64_tune_params->addr_cost;
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const struct cpu_addrcost_table *addr_cost = aarch64_tune_params.addr_cost;
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struct aarch64_address_info info;
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int cost = 0;
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info.shift = 0;
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@ -5459,7 +5459,7 @@ aarch64_branch_cost (bool speed_p, bool predictable_p)
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{
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/* When optimizing for speed, use the cost of unpredictable branches. */
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const struct cpu_branch_cost *branch_costs =
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aarch64_tune_params->branch_costs;
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aarch64_tune_params.branch_costs;
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if (!speed_p || predictable_p)
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return branch_costs->predictable;
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@ -5642,7 +5642,7 @@ aarch64_rtx_costs (rtx x, int code, int outer ATTRIBUTE_UNUSED,
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{
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rtx op0, op1, op2;
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const struct cpu_cost_table *extra_cost
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= aarch64_tune_params->insn_extra_cost;
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= aarch64_tune_params.insn_extra_cost;
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machine_mode mode = GET_MODE (x);
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/* By default, assume that everything has equivalent cost to the
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@ -6802,7 +6802,7 @@ aarch64_register_move_cost (machine_mode mode,
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enum reg_class from = (enum reg_class) from_i;
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enum reg_class to = (enum reg_class) to_i;
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const struct cpu_regmove_cost *regmove_cost
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= aarch64_tune_params->regmove_cost;
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= aarch64_tune_params.regmove_cost;
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/* Caller save and pointer regs are equivalent to GENERAL_REGS. */
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if (to == CALLER_SAVE_REGS || to == POINTER_REGS)
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@ -6857,14 +6857,14 @@ aarch64_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED,
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reg_class_t rclass ATTRIBUTE_UNUSED,
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bool in ATTRIBUTE_UNUSED)
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{
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return aarch64_tune_params->memmov_cost;
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return aarch64_tune_params.memmov_cost;
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}
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/* Return the number of instructions that can be issued per cycle. */
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static int
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aarch64_sched_issue_rate (void)
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{
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return aarch64_tune_params->issue_rate;
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return aarch64_tune_params.issue_rate;
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}
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static int
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@ -6888,44 +6888,44 @@ aarch64_builtin_vectorization_cost (enum vect_cost_for_stmt type_of_cost,
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switch (type_of_cost)
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{
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case scalar_stmt:
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return aarch64_tune_params->vec_costs->scalar_stmt_cost;
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return aarch64_tune_params.vec_costs->scalar_stmt_cost;
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case scalar_load:
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return aarch64_tune_params->vec_costs->scalar_load_cost;
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return aarch64_tune_params.vec_costs->scalar_load_cost;
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case scalar_store:
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return aarch64_tune_params->vec_costs->scalar_store_cost;
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return aarch64_tune_params.vec_costs->scalar_store_cost;
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case vector_stmt:
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return aarch64_tune_params->vec_costs->vec_stmt_cost;
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return aarch64_tune_params.vec_costs->vec_stmt_cost;
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case vector_load:
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return aarch64_tune_params->vec_costs->vec_align_load_cost;
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return aarch64_tune_params.vec_costs->vec_align_load_cost;
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case vector_store:
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return aarch64_tune_params->vec_costs->vec_store_cost;
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return aarch64_tune_params.vec_costs->vec_store_cost;
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case vec_to_scalar:
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return aarch64_tune_params->vec_costs->vec_to_scalar_cost;
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return aarch64_tune_params.vec_costs->vec_to_scalar_cost;
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case scalar_to_vec:
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return aarch64_tune_params->vec_costs->scalar_to_vec_cost;
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return aarch64_tune_params.vec_costs->scalar_to_vec_cost;
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case unaligned_load:
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return aarch64_tune_params->vec_costs->vec_unalign_load_cost;
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return aarch64_tune_params.vec_costs->vec_unalign_load_cost;
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case unaligned_store:
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return aarch64_tune_params->vec_costs->vec_unalign_store_cost;
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return aarch64_tune_params.vec_costs->vec_unalign_store_cost;
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case cond_branch_taken:
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return aarch64_tune_params->vec_costs->cond_taken_branch_cost;
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return aarch64_tune_params.vec_costs->cond_taken_branch_cost;
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case cond_branch_not_taken:
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return aarch64_tune_params->vec_costs->cond_not_taken_branch_cost;
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return aarch64_tune_params.vec_costs->cond_not_taken_branch_cost;
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case vec_perm:
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case vec_promote_demote:
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return aarch64_tune_params->vec_costs->vec_stmt_cost;
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return aarch64_tune_params.vec_costs->vec_stmt_cost;
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case vec_construct:
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elements = TYPE_VECTOR_SUBPARTS (vectype);
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@ -7227,7 +7227,9 @@ aarch64_override_options (void)
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aarch64_tune_flags = selected_tune->flags;
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aarch64_tune = selected_tune->core;
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aarch64_tune_params = selected_tune->tune;
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/* Make a copy of the tuning parameters attached to the core, which
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we may later overwrite. */
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aarch64_tune_params = *(selected_tune->tune);
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aarch64_architecture_version = selected_cpu->architecture_version;
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if (aarch64_fix_a53_err835769 == 2)
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@ -7259,11 +7261,11 @@ aarch64_override_options_after_change (void)
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if (!optimize_size)
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{
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if (align_loops <= 0)
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align_loops = aarch64_tune_params->loop_align;
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align_loops = aarch64_tune_params.loop_align;
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if (align_jumps <= 0)
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align_jumps = aarch64_tune_params->jump_align;
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align_jumps = aarch64_tune_params.jump_align;
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if (align_functions <= 0)
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align_functions = aarch64_tune_params->function_align;
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align_functions = aarch64_tune_params.function_align;
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}
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}
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@ -10958,7 +10960,7 @@ aarch64_gen_ccmp_next (rtx *prep_seq, rtx *gen_seq, rtx prev, int cmp_code,
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static bool
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aarch64_macro_fusion_p (void)
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{
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return aarch64_tune_params->fusible_ops != AARCH64_FUSE_NOTHING;
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return aarch64_tune_params.fusible_ops != AARCH64_FUSE_NOTHING;
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}
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@ -10978,7 +10980,7 @@ aarch_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr)
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return false;
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if (simple_sets_p
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&& (aarch64_tune_params->fusible_ops & AARCH64_FUSE_MOV_MOVK))
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&& (aarch64_tune_params.fusible_ops & AARCH64_FUSE_MOV_MOVK))
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{
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/* We are trying to match:
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prev (mov) == (set (reg r0) (const_int imm16))
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@ -11003,7 +11005,7 @@ aarch_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr)
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}
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if (simple_sets_p
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&& (aarch64_tune_params->fusible_ops & AARCH64_FUSE_ADRP_ADD))
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&& (aarch64_tune_params.fusible_ops & AARCH64_FUSE_ADRP_ADD))
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{
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/* We're trying to match:
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@ -11029,7 +11031,7 @@ aarch_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr)
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}
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if (simple_sets_p
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&& (aarch64_tune_params->fusible_ops & AARCH64_FUSE_MOVK_MOVK))
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&& (aarch64_tune_params.fusible_ops & AARCH64_FUSE_MOVK_MOVK))
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{
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/* We're trying to match:
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@ -11058,7 +11060,7 @@ aarch_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr)
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}
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if (simple_sets_p
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&& (aarch64_tune_params->fusible_ops & AARCH64_FUSE_ADRP_LDR))
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&& (aarch64_tune_params.fusible_ops & AARCH64_FUSE_ADRP_LDR))
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{
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/* We're trying to match:
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prev (adrp) == (set (reg r0)
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@ -11089,7 +11091,7 @@ aarch_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr)
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}
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}
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if ((aarch64_tune_params->fusible_ops & AARCH64_FUSE_CMP_BRANCH)
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if ((aarch64_tune_params.fusible_ops & AARCH64_FUSE_CMP_BRANCH)
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&& any_condjump_p (curr))
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{
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enum attr_type prev_type = get_attr_type (prev);
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@ -1052,7 +1052,7 @@ public:
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/* opt_pass methods: */
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virtual bool gate (function *)
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{
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return (aarch64_tune_params->extra_tuning_flags
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return (aarch64_tune_params.extra_tuning_flags
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& AARCH64_EXTRA_TUNE_RENAME_FMA_REGS)
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&& optimize >= 2;
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}
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