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rs6000: Delete meaningless arguments to define_{expand,split,peephole2}

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This removes the (usually empty) constraint arguments to define_expand,
define_split, and define_peephole2: this argument is meaningless and
just noise.


	* config/rs6000/altivec.md: Delete contraint arguments to
	define_expand, define_split, and define_peephole2, and in
	define_insn_and_split if always unused.
	* config/rs6000/darwin.md: Ditto.
	* config/rs6000/dfp.md: Ditto.
	* config/rs6000/rs6000.md: Ditto.
	* config/rs6000/sync.md: Ditto.
	* config/rs6000/vector.md: Ditto.
	* config/rs6000/vsx.md: Ditto.

From-SVN: r257890
This commit is contained in:
Segher Boessenkool 2018-02-22 02:09:18 +01:00 • committed by Segher Boessenkool
parent 6c33231394
commit ad18eed284
8 changed files with 846 additions and 834 deletions
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12
gcc/ChangeLog
View file

@ -1,3 +1,15 @@
2018-02-21 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/altivec.md: Delete contraint arguments to
define_expand, define_split, and define_peephole2, and in
define_insn_and_split if always unused.
* config/rs6000/darwin.md: Ditto.
* config/rs6000/dfp.md: Ditto.
* config/rs6000/rs6000.md: Ditto.
* config/rs6000/sync.md: Ditto.
* config/rs6000/vector.md: Ditto.
* config/rs6000/vsx.md: Ditto.
2018-02-21 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/altivec.md: Write output control strings as braced

222
gcc/config/rs6000/altivec.md
View file

@ -291,8 +291,8 @@
;; Load up a vector with the most significant bit set by loading up -1 and
;; doing a shift left
(define_split
[(set (match_operand:VM 0 "altivec_register_operand" "")
(match_operand:VM 1 "easy_vector_constant_msb" ""))]
[(set (match_operand:VM 0 "altivec_register_operand")
(match_operand:VM 1 "easy_vector_constant_msb"))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && reload_completed"
[(const_int 0)]
{
@ -318,8 +318,8 @@
})
(define_split
[(set (match_operand:VM 0 "altivec_register_operand" "")
(match_operand:VM 1 "easy_vector_constant_add_self" ""))]
[(set (match_operand:VM 0 "altivec_register_operand")
(match_operand:VM 1 "easy_vector_constant_add_self"))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && reload_completed"
[(set (match_dup 0) (match_dup 3))
(set (match_dup 0) (match_dup 4))]
@ -347,8 +347,8 @@
})
(define_split
[(set (match_operand:VM 0 "altivec_register_operand" "")
(match_operand:VM 1 "easy_vector_constant_vsldoi" ""))]
[(set (match_operand:VM 0 "altivec_register_operand")
(match_operand:VM 1 "easy_vector_constant_vsldoi"))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode) && can_create_pseudo_p ()"
[(set (match_dup 2) (match_dup 3))
(set (match_dup 4) (match_dup 5))
@ -692,9 +692,9 @@
;; We do multiply as a fused multiply-add with an add of a -0.0 vector.
(define_expand "altivec_mulv4sf3"
[(set (match_operand:V4SF 0 "register_operand" "")
(fma:V4SF (match_operand:V4SF 1 "register_operand" "")
(match_operand:V4SF 2 "register_operand" "")
[(set (match_operand:V4SF 0 "register_operand")
(fma:V4SF (match_operand:V4SF 1 "register_operand")
(match_operand:V4SF 2 "register_operand")
(match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
{
@ -728,9 +728,9 @@
[(set_attr "type" "veccomplex")])
(define_expand "mulv4si3"
[(use (match_operand:V4SI 0 "register_operand" ""))
(use (match_operand:V4SI 1 "register_operand" ""))
(use (match_operand:V4SI 2 "register_operand" ""))]
[(use (match_operand:V4SI 0 "register_operand"))
(use (match_operand:V4SI 1 "register_operand"))
(use (match_operand:V4SI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtx zero;
@ -780,9 +780,9 @@
})
(define_expand "mulv8hi3"
[(use (match_operand:V8HI 0 "register_operand" ""))
(use (match_operand:V8HI 1 "register_operand" ""))
(use (match_operand:V8HI 2 "register_operand" ""))]
[(use (match_operand:V8HI 0 "register_operand"))
(use (match_operand:V8HI 1 "register_operand"))
(use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtx zero = gen_reg_rtx (V8HImode);
@ -940,9 +940,9 @@
[(set_attr "type" "veccomplex")])
(define_expand "altivec_vmrghb"
[(use (match_operand:V16QI 0 "register_operand" ""))
(use (match_operand:V16QI 1 "register_operand" ""))
(use (match_operand:V16QI 2 "register_operand" ""))]
[(use (match_operand:V16QI 0 "register_operand"))
(use (match_operand:V16QI 1 "register_operand"))
(use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@ -1004,9 +1004,9 @@
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrghh"
[(use (match_operand:V8HI 0 "register_operand" ""))
(use (match_operand:V8HI 1 "register_operand" ""))
(use (match_operand:V8HI 2 "register_operand" ""))]
[(use (match_operand:V8HI 0 "register_operand"))
(use (match_operand:V8HI 1 "register_operand"))
(use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@ -1060,9 +1060,9 @@
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrghw"
[(use (match_operand:V4SI 0 "register_operand" ""))
(use (match_operand:V4SI 1 "register_operand" ""))
(use (match_operand:V4SI 2 "register_operand" ""))]
[(use (match_operand:V4SI 0 "register_operand"))
(use (match_operand:V4SI 1 "register_operand"))
(use (match_operand:V4SI 2 "register_operand"))]
"VECTOR_MEM_ALTIVEC_P (V4SImode)"
{
rtvec v;
@ -1131,9 +1131,9 @@
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrglb"
[(use (match_operand:V16QI 0 "register_operand" ""))
(use (match_operand:V16QI 1 "register_operand" ""))
(use (match_operand:V16QI 2 "register_operand" ""))]
[(use (match_operand:V16QI 0 "register_operand"))
(use (match_operand:V16QI 1 "register_operand"))
(use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@ -1195,9 +1195,9 @@
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrglh"
[(use (match_operand:V8HI 0 "register_operand" ""))
(use (match_operand:V8HI 1 "register_operand" ""))
(use (match_operand:V8HI 2 "register_operand" ""))]
[(use (match_operand:V8HI 0 "register_operand"))
(use (match_operand:V8HI 1 "register_operand"))
(use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@ -1251,9 +1251,9 @@
[(set_attr "type" "vecperm")])
(define_expand "altivec_vmrglw"
[(use (match_operand:V4SI 0 "register_operand" ""))
(use (match_operand:V4SI 1 "register_operand" ""))
(use (match_operand:V4SI 2 "register_operand" ""))]
[(use (match_operand:V4SI 0 "register_operand"))
(use (match_operand:V4SI 1 "register_operand"))
(use (match_operand:V4SI 2 "register_operand"))]
"VECTOR_MEM_ALTIVEC_P (V4SImode)"
{
rtvec v;
@ -1410,9 +1410,9 @@
[(set_attr "type" "vecperm")])
(define_expand "vec_widen_umult_even_v16qi"
[(use (match_operand:V8HI 0 "register_operand" ""))
(use (match_operand:V16QI 1 "register_operand" ""))
(use (match_operand:V16QI 2 "register_operand" ""))]
[(use (match_operand:V8HI 0 "register_operand"))
(use (match_operand:V16QI 1 "register_operand"))
(use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@ -1423,9 +1423,9 @@
})
(define_expand "vec_widen_smult_even_v16qi"
[(use (match_operand:V8HI 0 "register_operand" ""))
(use (match_operand:V16QI 1 "register_operand" ""))
(use (match_operand:V16QI 2 "register_operand" ""))]
[(use (match_operand:V8HI 0 "register_operand"))
(use (match_operand:V16QI 1 "register_operand"))
(use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@ -1436,9 +1436,9 @@
})
(define_expand "vec_widen_umult_even_v8hi"
[(use (match_operand:V4SI 0 "register_operand" ""))
(use (match_operand:V8HI 1 "register_operand" ""))
(use (match_operand:V8HI 2 "register_operand" ""))]
[(use (match_operand:V4SI 0 "register_operand"))
(use (match_operand:V8HI 1 "register_operand"))
(use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@ -1449,9 +1449,9 @@
})
(define_expand "vec_widen_smult_even_v8hi"
[(use (match_operand:V4SI 0 "register_operand" ""))
(use (match_operand:V8HI 1 "register_operand" ""))
(use (match_operand:V8HI 2 "register_operand" ""))]
[(use (match_operand:V4SI 0 "register_operand"))
(use (match_operand:V8HI 1 "register_operand"))
(use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@ -1488,9 +1488,9 @@
})
(define_expand "vec_widen_umult_odd_v16qi"
[(use (match_operand:V8HI 0 "register_operand" ""))
(use (match_operand:V16QI 1 "register_operand" ""))
(use (match_operand:V16QI 2 "register_operand" ""))]
[(use (match_operand:V8HI 0 "register_operand"))
(use (match_operand:V16QI 1 "register_operand"))
(use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@ -1501,9 +1501,9 @@
})
(define_expand "vec_widen_smult_odd_v16qi"
[(use (match_operand:V8HI 0 "register_operand" ""))
(use (match_operand:V16QI 1 "register_operand" ""))
(use (match_operand:V16QI 2 "register_operand" ""))]
[(use (match_operand:V8HI 0 "register_operand"))
(use (match_operand:V16QI 1 "register_operand"))
(use (match_operand:V16QI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@ -1514,9 +1514,9 @@
})
(define_expand "vec_widen_umult_odd_v8hi"
[(use (match_operand:V4SI 0 "register_operand" ""))
(use (match_operand:V8HI 1 "register_operand" ""))
(use (match_operand:V8HI 2 "register_operand" ""))]
[(use (match_operand:V4SI 0 "register_operand"))
(use (match_operand:V8HI 1 "register_operand"))
(use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@ -1527,9 +1527,9 @@
})
(define_expand "vec_widen_smult_odd_v8hi"
[(use (match_operand:V4SI 0 "register_operand" ""))
(use (match_operand:V8HI 1 "register_operand" ""))
(use (match_operand:V8HI 2 "register_operand" ""))]
[(use (match_operand:V4SI 0 "register_operand"))
(use (match_operand:V8HI 1 "register_operand"))
(use (match_operand:V8HI 2 "register_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@ -1949,9 +1949,9 @@
[(set_attr "type" "veccomplex")])
(define_expand "altivec_vspltb"
[(use (match_operand:V16QI 0 "register_operand" ""))
(use (match_operand:V16QI 1 "register_operand" ""))
(use (match_operand:QI 2 "u5bit_cint_operand" ""))]
[(use (match_operand:V16QI 0 "register_operand"))
(use (match_operand:V16QI 1 "register_operand"))
(use (match_operand:QI 2 "u5bit_cint_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@ -1997,9 +1997,9 @@
[(set_attr "type" "vecperm")])
(define_expand "altivec_vsplth"
[(use (match_operand:V8HI 0 "register_operand" ""))
(use (match_operand:V8HI 1 "register_operand" ""))
(use (match_operand:QI 2 "u5bit_cint_operand" ""))]
[(use (match_operand:V8HI 0 "register_operand"))
(use (match_operand:V8HI 1 "register_operand"))
(use (match_operand:QI 2 "u5bit_cint_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@ -2045,9 +2045,9 @@
[(set_attr "type" "vecperm")])
(define_expand "altivec_vspltw"
[(use (match_operand:V4SI 0 "register_operand" ""))
(use (match_operand:V4SI 1 "register_operand" ""))
(use (match_operand:QI 2 "u5bit_cint_operand" ""))]
[(use (match_operand:V4SI 0 "register_operand"))
(use (match_operand:V4SI 1 "register_operand"))
(use (match_operand:QI 2 "u5bit_cint_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@ -2093,9 +2093,9 @@
[(set_attr "type" "vecperm")])
(define_expand "altivec_vspltsf"
[(use (match_operand:V4SF 0 "register_operand" ""))
(use (match_operand:V4SF 1 "register_operand" ""))
(use (match_operand:QI 2 "u5bit_cint_operand" ""))]
[(use (match_operand:V4SF 0 "register_operand"))
(use (match_operand:V4SF 1 "register_operand"))
(use (match_operand:QI 2 "u5bit_cint_operand"))]
"TARGET_ALTIVEC"
{
rtvec v;
@ -2147,10 +2147,10 @@
[(set_attr "type" "vecfloat")])
(define_expand "altivec_vperm_<mode>"
[(set (match_operand:VM 0 "register_operand" "")
(unspec:VM [(match_operand:VM 1 "register_operand" "")
(match_operand:VM 2 "register_operand" "")
(match_operand:V16QI 3 "register_operand" "")]
[(set (match_operand:VM 0 "register_operand")
(unspec:VM [(match_operand:VM 1 "register_operand")
(match_operand:VM 2 "register_operand")
(match_operand:V16QI 3 "register_operand")]
UNSPEC_VPERM))]
"TARGET_ALTIVEC"
{
@ -2189,10 +2189,10 @@
(set_attr "length" "4")])
(define_expand "altivec_vperm_<mode>_uns"
[(set (match_operand:VM 0 "register_operand" "")
(unspec:VM [(match_operand:VM 1 "register_operand" "")
(match_operand:VM 2 "register_operand" "")
(match_operand:V16QI 3 "register_operand" "")]
[(set (match_operand:VM 0 "register_operand")
(unspec:VM [(match_operand:VM 1 "register_operand")
(match_operand:VM 2 "register_operand")
(match_operand:V16QI 3 "register_operand")]
UNSPEC_VPERM_UNS))]
"TARGET_ALTIVEC"
{
@ -2217,10 +2217,10 @@
(set_attr "length" "4")])
(define_expand "vec_permv16qi"
[(set (match_operand:V16QI 0 "register_operand" "")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
(match_operand:V16QI 2 "register_operand" "")
(match_operand:V16QI 3 "register_operand" "")]
[(set (match_operand:V16QI 0 "register_operand")
(unspec:V16QI [(match_operand:V16QI 1 "register_operand")
(match_operand:V16QI 2 "register_operand")
(match_operand:V16QI 3 "register_operand")]
UNSPEC_VPERM))]
"TARGET_ALTIVEC"
{
@ -2338,9 +2338,9 @@
[(set_attr "type" "vecfloat")])
(define_expand "altivec_copysign_v4sf3"
[(use (match_operand:V4SF 0 "register_operand" ""))
(use (match_operand:V4SF 1 "register_operand" ""))
(use (match_operand:V4SF 2 "register_operand" ""))]
[(use (match_operand:V4SF 0 "register_operand"))
(use (match_operand:V4SF 1 "register_operand"))
(use (match_operand:V4SF 2 "register_operand"))]
"VECTOR_UNIT_ALTIVEC_P (V4SFmode)"
{
rtx mask = gen_reg_rtx (V4SImode);
@ -2584,8 +2584,8 @@
[(set_attr "type" "vecsimple")])
(define_expand "altivec_lvsl"
[(use (match_operand:V16QI 0 "register_operand" ""))
(use (match_operand:V16QI 1 "memory_operand" ""))]
[(use (match_operand:V16QI 0 "register_operand"))
(use (match_operand:V16QI 1 "memory_operand"))]
"TARGET_ALTIVEC"
{
if (VECTOR_ELT_ORDER_BIG)
@ -2660,8 +2660,8 @@
[(set_attr "type" "vecload")])
(define_expand "build_vector_mask_for_load"
[(set (match_operand:V16QI 0 "register_operand" "")
(unspec:V16QI [(match_operand 1 "memory_operand" "")] UNSPEC_LVSR))]
[(set (match_operand:V16QI 0 "register_operand")
(unspec:V16QI [(match_operand 1 "memory_operand")] UNSPEC_LVSR))]
"TARGET_ALTIVEC"
{
rtx addr;
@ -3331,8 +3331,8 @@
[(set_attr "type" "vecsimple")])
(define_expand "neg<mode>2"
[(set (match_operand:VI2 0 "register_operand" "")
(neg:VI2 (match_operand:VI2 1 "register_operand" "")))]
[(set (match_operand:VI2 0 "register_operand")
(neg:VI2 (match_operand:VI2 1 "register_operand")))]
"<VI_unit>"
{
if (!TARGET_P9_VECTOR || (<MODE>mode != V4SImode && <MODE>mode != V2DImode))
@ -3828,8 +3828,8 @@
})
(define_expand "altivec_negv4sf2"
[(use (match_operand:V4SF 0 "register_operand" ""))
(use (match_operand:V4SF 1 "register_operand" ""))]
[(use (match_operand:V4SF 0 "register_operand"))
(use (match_operand:V4SF 1 "register_operand"))]
"TARGET_ALTIVEC"
{
rtx neg0;
@ -3942,8 +3942,8 @@
[(set_attr "type" "vecstore")])
(define_expand "vec_unpacks_float_hi_v8hi"
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
[(set (match_operand:V4SF 0 "register_operand")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand")]
UNSPEC_VUPKHS_V4SF))]
"TARGET_ALTIVEC"
{
@ -3955,8 +3955,8 @@
})
(define_expand "vec_unpacks_float_lo_v8hi"
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
[(set (match_operand:V4SF 0 "register_operand")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand")]
UNSPEC_VUPKLS_V4SF))]
"TARGET_ALTIVEC"
{
@ -3968,8 +3968,8 @@
})
(define_expand "vec_unpacku_float_hi_v8hi"
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
[(set (match_operand:V4SF 0 "register_operand")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand")]
UNSPEC_VUPKHU_V4SF))]
"TARGET_ALTIVEC"
{
@ -3981,8 +3981,8 @@
})
(define_expand "vec_unpacku_float_lo_v8hi"
[(set (match_operand:V4SF 0 "register_operand" "")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand" "")]
[(set (match_operand:V4SF 0 "register_operand")
(unspec:V4SF [(match_operand:V8HI 1 "register_operand")]
UNSPEC_VUPKLU_V4SF))]
"TARGET_ALTIVEC"
{
@ -4498,13 +4498,13 @@
(define_expand "bcd<bcd_add_sub>_<code>"
[(parallel [(set (reg:CCFP CR6_REGNO)
(compare:CCFP
(unspec:V2DF [(match_operand:V1TI 1 "register_operand" "")
(match_operand:V1TI 2 "register_operand" "")
(match_operand:QI 3 "const_0_to_1_operand" "")]
(unspec:V2DF [(match_operand:V1TI 1 "register_operand")
(match_operand:V1TI 2 "register_operand")
(match_operand:QI 3 "const_0_to_1_operand")]
UNSPEC_BCD_ADD_SUB)
(match_dup 4)))
(clobber (match_scratch:V1TI 5 ""))])
(set (match_operand:SI 0 "register_operand" "")
(clobber (match_scratch:V1TI 5))])
(set (match_operand:SI 0 "register_operand")
(BCD_TEST:SI (reg:CCFP CR6_REGNO)
(const_int 0)))]
"TARGET_P8_VECTOR"
@ -4519,10 +4519,10 @@
;; a register class for CR6.
(define_peephole2
[(parallel [(set (match_operand:V1TI 0 "register_operand" "")
(unspec:V1TI [(match_operand:V1TI 1 "register_operand" "")
(match_operand:V1TI 2 "register_operand" "")
(match_operand:QI 3 "const_0_to_1_operand" "")]
[(parallel [(set (match_operand:V1TI 0 "register_operand")
(unspec:V1TI [(match_operand:V1TI 1 "register_operand")
(match_operand:V1TI 2 "register_operand")
(match_operand:QI 3 "const_0_to_1_operand")]
UNSPEC_BCD_ADD_SUB))
(clobber (reg:CCFP CR6_REGNO))])
(parallel [(set (reg:CCFP CR6_REGNO)
@ -4531,8 +4531,8 @@
(match_dup 2)
(match_dup 3)]
UNSPEC_BCD_ADD_SUB)
(match_operand:V2DF 4 "zero_constant" "")))
(clobber (match_operand:V1TI 5 "register_operand" ""))])]
(match_operand:V2DF 4 "zero_constant")))
(clobber (match_operand:V1TI 5 "register_operand"))])]
"TARGET_P8_VECTOR"
[(parallel [(set (match_dup 0)
(unspec:V1TI [(match_dup 1)

30
gcc/config/rs6000/darwin.md
View file

@ -171,8 +171,8 @@ You should have received a copy of the GNU General Public License
;; Mach-O PIC trickery.
(define_expand "macho_high"
[(set (match_operand 0 "" "")
(high (match_operand 1 "" "")))]
[(set (match_operand 0 "")
(high (match_operand 1 "")))]
"TARGET_MACHO"
{
if (TARGET_64BIT)
@ -197,9 +197,9 @@ You should have received a copy of the GNU General Public License
"lis %0,ha16(%1)")
(define_expand "macho_low"
[(set (match_operand 0 "" "")
(lo_sum (match_operand 1 "" "")
(match_operand 2 "" "")))]
[(set (match_operand 0 "")
(lo_sum (match_operand 1 "")
(match_operand 2 "")))]
"TARGET_MACHO"
{
if (TARGET_64BIT)
@ -225,10 +225,10 @@ You should have received a copy of the GNU General Public License
"la %0,lo16(%2)(%1)")
(define_split
[(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")
(match_operand:DI 1 "short_cint_operand" "")))
(match_operand:V4SI 2 "register_operand" ""))
(clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
[(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand")
(match_operand:DI 1 "short_cint_operand")))
(match_operand:V4SI 2 "register_operand"))
(clobber (match_operand:DI 3 "gpc_reg_operand"))]
"TARGET_MACHO && TARGET_64BIT"
[(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1)))
(set (mem:V4SI (match_dup 3))
@ -237,7 +237,7 @@ You should have received a copy of the GNU General Public License
(define_expand "load_macho_picbase"
[(set (reg:SI LR_REGNO)
(unspec [(match_operand 0 "" "")]
(unspec [(match_operand 0 "")]
UNSPEC_LD_MPIC))]
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
{
@ -284,10 +284,10 @@ You should have received a copy of the GNU General Public License
(set_attr "length" "4")])
(define_expand "macho_correct_pic"
[(set (match_operand 0 "" "")
(plus (match_operand 1 "" "")
(unspec [(match_operand 2 "" "")
(match_operand 3 "" "")]
[(set (match_operand 0 "")
(plus (match_operand 1 "")
(unspec [(match_operand 2 "")
(match_operand 3 "")]
UNSPEC_MPIC_CORRECT)))]
"DEFAULT_ABI == ABI_DARWIN"
{
@ -383,7 +383,7 @@ You should have received a copy of the GNU General Public License
(define_expand "reload_macho_picbase"
[(set (reg:SI LR_REGNO)
(unspec [(match_operand 0 "" "")]
(unspec [(match_operand 0 "")]
UNSPEC_RELD_MPIC))]
"(DEFAULT_ABI == ABI_DARWIN) && flag_pic"
{

6
gcc/config/rs6000/dfp.md
View file

@ -344,11 +344,11 @@
[(set (match_dup 3)
(compare:CCFP
(unspec:D64_D128
[(match_operand:SI 1 "const_int_operand" "n")
(match_operand:D64_D128 2 "gpc_reg_operand" "d")]
[(match_operand:SI 1 "const_int_operand")
(match_operand:D64_D128 2 "gpc_reg_operand")]
UNSPEC_DTSTSFI)
(match_dup 4)))
(set (match_operand:SI 0 "register_operand" "")
(set (match_operand:SI 0 "register_operand")
(DFP_TEST:SI (match_dup 3)
(const_int 0)))
]

780
gcc/config/rs6000/rs6000.md
View file

File diff suppressed because it is too large Load diff

92
gcc/config/rs6000/sync.md
View file

@ -38,7 +38,7 @@
(ior "logical_operand") (xor "logical_operand") (and "and_operand")])
(define_expand "mem_thread_fence"
[(match_operand:SI 0 "const_int_operand" "")] ;; model
[(match_operand:SI 0 "const_int_operand")] ;; model
""
{
enum memmodel model = memmodel_base (INTVAL (operands[0]));
@ -136,9 +136,9 @@
(set_attr "length" "4")])
(define_expand "atomic_load<mode>"
[(set (match_operand:AINT 0 "register_operand" "") ;; output
(match_operand:AINT 1 "memory_operand" "")) ;; memory
(use (match_operand:SI 2 "const_int_operand" ""))] ;; model
[(set (match_operand:AINT 0 "register_operand") ;; output
(match_operand:AINT 1 "memory_operand")) ;; memory
(use (match_operand:SI 2 "const_int_operand"))] ;; model
""
{
if (<MODE>mode == TImode && !TARGET_SYNC_TI)
@ -200,9 +200,9 @@
(set_attr "length" "4")])
(define_expand "atomic_store<mode>"
[(set (match_operand:AINT 0 "memory_operand" "") ;; memory
(match_operand:AINT 1 "register_operand" "")) ;; input
(use (match_operand:SI 2 "const_int_operand" ""))] ;; model
[(set (match_operand:AINT 0 "memory_operand") ;; memory
(match_operand:AINT 1 "register_operand")) ;; input
(use (match_operand:SI 2 "const_int_operand"))] ;; model
""
{
if (<MODE>mode == TImode && !TARGET_SYNC_TI)
@ -287,8 +287,8 @@
;; is indexed or indirect before register allocation.
(define_expand "load_lockedti"
[(use (match_operand:TI 0 "quad_int_reg_operand" ""))
(use (match_operand:TI 1 "memory_operand" ""))]
[(use (match_operand:TI 0 "quad_int_reg_operand"))
(use (match_operand:TI 1 "memory_operand"))]
"TARGET_SYNC_TI"
{
rtx op0 = operands[0];
@ -341,9 +341,9 @@
;; is indexed or indirect before register allocation.
(define_expand "store_conditionalti"
[(use (match_operand:CC 0 "cc_reg_operand" ""))
(use (match_operand:TI 1 "memory_operand" ""))
(use (match_operand:TI 2 "quad_int_reg_operand" ""))]
[(use (match_operand:CC 0 "cc_reg_operand"))
(use (match_operand:TI 1 "memory_operand"))
(use (match_operand:TI 2 "quad_int_reg_operand"))]
"TARGET_SYNC_TI"
{
rtx op0 = operands[0];
@ -385,14 +385,14 @@
[(set_attr "type" "store_c")])
(define_expand "atomic_compare_and_swap<mode>"
[(match_operand:SI 0 "int_reg_operand" "") ;; bool out
(match_operand:AINT 1 "int_reg_operand" "") ;; val out
(match_operand:AINT 2 "memory_operand" "") ;; memory
(match_operand:AINT 3 "reg_or_short_operand" "") ;; expected
(match_operand:AINT 4 "int_reg_operand" "") ;; desired
(match_operand:SI 5 "const_int_operand" "") ;; is_weak
(match_operand:SI 6 "const_int_operand" "") ;; model succ
(match_operand:SI 7 "const_int_operand" "")] ;; model fail
[(match_operand:SI 0 "int_reg_operand") ;; bool out
(match_operand:AINT 1 "int_reg_operand") ;; val out
(match_operand:AINT 2 "memory_operand") ;; memory
(match_operand:AINT 3 "reg_or_short_operand") ;; expected
(match_operand:AINT 4 "int_reg_operand") ;; desired
(match_operand:SI 5 "const_int_operand") ;; is_weak
(match_operand:SI 6 "const_int_operand") ;; model succ
(match_operand:SI 7 "const_int_operand")] ;; model fail
""
{
rs6000_expand_atomic_compare_and_swap (operands);
@ -400,10 +400,10 @@
})
(define_expand "atomic_exchange<mode>"
[(match_operand:AINT 0 "int_reg_operand" "") ;; output
(match_operand:AINT 1 "memory_operand" "") ;; memory
(match_operand:AINT 2 "int_reg_operand" "") ;; input
(match_operand:SI 3 "const_int_operand" "")] ;; model
[(match_operand:AINT 0 "int_reg_operand") ;; output
(match_operand:AINT 1 "memory_operand") ;; memory
(match_operand:AINT 2 "int_reg_operand") ;; input
(match_operand:SI 3 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_exchange (operands);
@ -411,10 +411,10 @@
})
(define_expand "atomic_<fetchop_name><mode>"
[(match_operand:AINT 0 "memory_operand" "") ;; memory
[(match_operand:AINT 0 "memory_operand") ;; memory
(FETCHOP:AINT (match_dup 0)
(match_operand:AINT 1 "<fetchop_pred>" "")) ;; operand
(match_operand:SI 2 "const_int_operand" "")] ;; model
(match_operand:AINT 1 "<fetchop_pred>")) ;; operand
(match_operand:SI 2 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_op (<CODE>, operands[0], operands[1],
@ -423,9 +423,9 @@
})
(define_expand "atomic_nand<mode>"
[(match_operand:AINT 0 "memory_operand" "") ;; memory
(match_operand:AINT 1 "int_reg_operand" "") ;; operand
(match_operand:SI 2 "const_int_operand" "")] ;; model
[(match_operand:AINT 0 "memory_operand") ;; memory
(match_operand:AINT 1 "int_reg_operand") ;; operand
(match_operand:SI 2 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_op (NOT, operands[0], operands[1],
@ -434,11 +434,11 @@
})
(define_expand "atomic_fetch_<fetchop_name><mode>"
[(match_operand:AINT 0 "int_reg_operand" "") ;; output
(match_operand:AINT 1 "memory_operand" "") ;; memory
[(match_operand:AINT 0 "int_reg_operand") ;; output
(match_operand:AINT 1 "memory_operand") ;; memory
(FETCHOP:AINT (match_dup 1)
(match_operand:AINT 2 "<fetchop_pred>" "")) ;; operand
(match_operand:SI 3 "const_int_operand" "")] ;; model
(match_operand:AINT 2 "<fetchop_pred>")) ;; operand
(match_operand:SI 3 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_op (<CODE>, operands[1], operands[2],
@ -447,10 +447,10 @@
})
(define_expand "atomic_fetch_nand<mode>"
[(match_operand:AINT 0 "int_reg_operand" "") ;; output
(match_operand:AINT 1 "memory_operand" "") ;; memory
(match_operand:AINT 2 "int_reg_operand" "") ;; operand
(match_operand:SI 3 "const_int_operand" "")] ;; model
[(match_operand:AINT 0 "int_reg_operand") ;; output
(match_operand:AINT 1 "memory_operand") ;; memory
(match_operand:AINT 2 "int_reg_operand") ;; operand
(match_operand:SI 3 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_op (NOT, operands[1], operands[2],
@ -459,11 +459,11 @@
})
(define_expand "atomic_<fetchop_name>_fetch<mode>"
[(match_operand:AINT 0 "int_reg_operand" "") ;; output
(match_operand:AINT 1 "memory_operand" "") ;; memory
[(match_operand:AINT 0 "int_reg_operand") ;; output
(match_operand:AINT 1 "memory_operand") ;; memory
(FETCHOP:AINT (match_dup 1)
(match_operand:AINT 2 "<fetchop_pred>" "")) ;; operand
(match_operand:SI 3 "const_int_operand" "")] ;; model
(match_operand:AINT 2 "<fetchop_pred>")) ;; operand
(match_operand:SI 3 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_op (<CODE>, operands[1], operands[2],
@ -472,10 +472,10 @@
})
(define_expand "atomic_nand_fetch<mode>"
[(match_operand:AINT 0 "int_reg_operand" "") ;; output
(match_operand:AINT 1 "memory_operand" "") ;; memory
(match_operand:AINT 2 "int_reg_operand" "") ;; operand
(match_operand:SI 3 "const_int_operand" "")] ;; model
[(match_operand:AINT 0 "int_reg_operand") ;; output
(match_operand:AINT 1 "memory_operand") ;; memory
(match_operand:AINT 2 "int_reg_operand") ;; operand
(match_operand:SI 3 "const_int_operand")] ;; model
""
{
rs6000_expand_atomic_op (NOT, operands[1], operands[2],

404
gcc/config/rs6000/vector.md
View file

@ -111,8 +111,8 @@
;; Vector move instructions. Little-endian VSX loads and stores require
;; special handling to circumvent "element endianness."
(define_expand "mov<mode>"
[(set (match_operand:VEC_M 0 "nonimmediate_operand" "")
(match_operand:VEC_M 1 "any_operand" ""))]
[(set (match_operand:VEC_M 0 "nonimmediate_operand")
(match_operand:VEC_M 1 "any_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (can_create_pseudo_p ())
@ -147,21 +147,21 @@
;; Generic vector floating point load/store instructions. These will match
;; insns defined in vsx.md or altivec.md depending on the switches.
(define_expand "vector_load_<mode>"
[(set (match_operand:VEC_M 0 "vfloat_operand" "")
(match_operand:VEC_M 1 "memory_operand" ""))]
[(set (match_operand:VEC_M 0 "vfloat_operand")
(match_operand:VEC_M 1 "memory_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_store_<mode>"
[(set (match_operand:VEC_M 0 "memory_operand" "")
(match_operand:VEC_M 1 "vfloat_operand" ""))]
[(set (match_operand:VEC_M 0 "memory_operand")
(match_operand:VEC_M 1 "vfloat_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
;; Splits if a GPR register was chosen for the move
(define_split
[(set (match_operand:VEC_L 0 "nonimmediate_operand" "")
(match_operand:VEC_L 1 "input_operand" ""))]
[(set (match_operand:VEC_L 0 "nonimmediate_operand")
(match_operand:VEC_L 1 "input_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)
&& reload_completed
&& gpr_or_gpr_p (operands[0], operands[1])
@ -178,8 +178,8 @@
;; instructions silently ignore the bottom 3 bits of the address, and VSX does
;; not.
(define_expand "vector_altivec_load_<mode>"
[(set (match_operand:VEC_M 0 "vfloat_operand" "")
(match_operand:VEC_M 1 "memory_operand" ""))]
[(set (match_operand:VEC_M 0 "vfloat_operand")
(match_operand:VEC_M 1 "memory_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
@ -200,8 +200,8 @@
})
(define_expand "vector_altivec_store_<mode>"
[(set (match_operand:VEC_M 0 "memory_operand" "")
(match_operand:VEC_M 1 "vfloat_operand" ""))]
[(set (match_operand:VEC_M 0 "memory_operand")
(match_operand:VEC_M 1 "vfloat_operand"))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
gcc_assert (VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode));
@ -225,23 +225,23 @@
;; Generic floating point vector arithmetic support
(define_expand "add<mode>3"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(plus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")))]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(plus:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
(match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "sub<mode>3"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(minus:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")))]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(minus:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
(match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "mul<mode>3"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")))]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(mult:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
(match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
@ -252,9 +252,9 @@
})
(define_expand "div<mode>3"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(div:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")))]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(div:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
(match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
{
if (RS6000_RECIP_AUTO_RE_P (<MODE>mode)
@ -267,8 +267,8 @@
})
(define_expand "neg<mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(neg:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
@ -279,8 +279,8 @@
})
(define_expand "abs<mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(abs:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
@ -291,23 +291,23 @@
})
(define_expand "smin<mode>3"
[(set (match_operand:VEC_F 0 "register_operand" "")
(smin:VEC_F (match_operand:VEC_F 1 "register_operand" "")
(match_operand:VEC_F 2 "register_operand" "")))]
[(set (match_operand:VEC_F 0 "register_operand")
(smin:VEC_F (match_operand:VEC_F 1 "register_operand")
(match_operand:VEC_F 2 "register_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "smax<mode>3"
[(set (match_operand:VEC_F 0 "register_operand" "")
(smax:VEC_F (match_operand:VEC_F 1 "register_operand" "")
(match_operand:VEC_F 2 "register_operand" "")))]
[(set (match_operand:VEC_F 0 "register_operand")
(smax:VEC_F (match_operand:VEC_F 1 "register_operand")
(match_operand:VEC_F 2 "register_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "sqrt<mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(sqrt:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode
@ -321,49 +321,49 @@
})
(define_expand "rsqrte<mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")]
UNSPEC_RSQRT))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "re<mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "f")]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")]
UNSPEC_FRES))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "ftrunc<mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_ceil<mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")]
UNSPEC_FRIP))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_floor<mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")]
UNSPEC_FRIM))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_btrunc<mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")))]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(fix:VEC_F (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_copysign<mode>3"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")] UNSPEC_COPYSIGN))]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(unspec:VEC_F [(match_operand:VEC_F 1 "vfloat_operand")
(match_operand:VEC_F 2 "vfloat_operand")] UNSPEC_COPYSIGN))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
@ -377,13 +377,13 @@
;; Vector comparisons
(define_expand "vcond<mode><mode>"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
[(set (match_operand:VEC_F 0 "vfloat_operand")
(if_then_else:VEC_F
(match_operator 3 "comparison_operator"
[(match_operand:VEC_F 4 "vfloat_operand" "")
(match_operand:VEC_F 5 "vfloat_operand" "")])
(match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")))]
[(match_operand:VEC_F 4 "vfloat_operand")
(match_operand:VEC_F 5 "vfloat_operand")])
(match_operand:VEC_F 1 "vfloat_operand")
(match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (rs6000_emit_vector_cond_expr (operands[0], operands[1], operands[2],
@ -411,13 +411,13 @@
})
(define_expand "vcondv4sfv4si"
[(set (match_operand:V4SF 0 "vfloat_operand" "")
[(set (match_operand:V4SF 0 "vfloat_operand")
(if_then_else:V4SF
(match_operator 3 "comparison_operator"
[(match_operand:V4SI 4 "vint_operand" "")
(match_operand:V4SI 5 "vint_operand" "")])
(match_operand:V4SF 1 "vfloat_operand" "")
(match_operand:V4SF 2 "vfloat_operand" "")))]
[(match_operand:V4SI 4 "vint_operand")
(match_operand:V4SI 5 "vint_operand")])
(match_operand:V4SF 1 "vfloat_operand")
(match_operand:V4SF 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& VECTOR_UNIT_ALTIVEC_P (V4SImode)"
{
@ -429,13 +429,13 @@
})
(define_expand "vcondv4siv4sf"
[(set (match_operand:V4SI 0 "vint_operand" "")
[(set (match_operand:V4SI 0 "vint_operand")
(if_then_else:V4SI
(match_operator 3 "comparison_operator"
[(match_operand:V4SF 4 "vfloat_operand" "")
(match_operand:V4SF 5 "vfloat_operand" "")])
(match_operand:V4SI 1 "vint_operand" "")
(match_operand:V4SI 2 "vint_operand" "")))]
[(match_operand:V4SF 4 "vfloat_operand")
(match_operand:V4SF 5 "vfloat_operand")])
(match_operand:V4SI 1 "vint_operand")
(match_operand:V4SI 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& VECTOR_UNIT_ALTIVEC_P (V4SImode)"
{
@ -500,13 +500,13 @@
})
(define_expand "vconduv4sfv4si"
[(set (match_operand:V4SF 0 "vfloat_operand" "")
[(set (match_operand:V4SF 0 "vfloat_operand")
(if_then_else:V4SF
(match_operator 3 "comparison_operator"
[(match_operand:V4SI 4 "vint_operand" "")
(match_operand:V4SI 5 "vint_operand" "")])
(match_operand:V4SF 1 "vfloat_operand" "")
(match_operand:V4SF 2 "vfloat_operand" "")))]
[(match_operand:V4SI 4 "vint_operand")
(match_operand:V4SI 5 "vint_operand")])
(match_operand:V4SF 1 "vfloat_operand")
(match_operand:V4SF 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)
&& VECTOR_UNIT_ALTIVEC_P (V4SImode)"
{
@ -536,32 +536,32 @@
})
(define_expand "vector_eq<mode>"
[(set (match_operand:VEC_C 0 "vlogical_operand" "")
(eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
(match_operand:VEC_C 2 "vlogical_operand" "")))]
[(set (match_operand:VEC_C 0 "vlogical_operand")
(eq:VEC_C (match_operand:VEC_C 1 "vlogical_operand")
(match_operand:VEC_C 2 "vlogical_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_gt<mode>"
[(set (match_operand:VEC_C 0 "vlogical_operand" "")
(gt:VEC_C (match_operand:VEC_C 1 "vlogical_operand" "")
(match_operand:VEC_C 2 "vlogical_operand" "")))]
[(set (match_operand:VEC_C 0 "vlogical_operand")
(gt:VEC_C (match_operand:VEC_C 1 "vlogical_operand")
(match_operand:VEC_C 2 "vlogical_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
(define_expand "vector_ge<mode>"
[(set (match_operand:VEC_F 0 "vlogical_operand" "")
(ge:VEC_F (match_operand:VEC_F 1 "vlogical_operand" "")
(match_operand:VEC_F 2 "vlogical_operand" "")))]
[(set (match_operand:VEC_F 0 "vlogical_operand")
(ge:VEC_F (match_operand:VEC_F 1 "vlogical_operand")
(match_operand:VEC_F 2 "vlogical_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
; >= for integer vectors: swap operands and apply not-greater-than
(define_expand "vector_nlt<mode>"
[(set (match_operand:VEC_I 3 "vlogical_operand" "")
(gt:VEC_I (match_operand:VEC_I 2 "vlogical_operand" "")
(match_operand:VEC_I 1 "vlogical_operand" "")))
(set (match_operand:VEC_I 0 "vlogical_operand" "")
[(set (match_operand:VEC_I 3 "vlogical_operand")
(gt:VEC_I (match_operand:VEC_I 2 "vlogical_operand")
(match_operand:VEC_I 1 "vlogical_operand")))
(set (match_operand:VEC_I 0 "vlogical_operand")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
@ -569,18 +569,18 @@
})
(define_expand "vector_gtu<mode>"
[(set (match_operand:VEC_I 0 "vint_operand" "")
(gtu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
(match_operand:VEC_I 2 "vint_operand" "")))]
[(set (match_operand:VEC_I 0 "vint_operand")
(gtu:VEC_I (match_operand:VEC_I 1 "vint_operand")
(match_operand:VEC_I 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
; >= for integer vectors: swap operands and apply not-greater-than
(define_expand "vector_nltu<mode>"
[(set (match_operand:VEC_I 3 "vlogical_operand" "")
(gtu:VEC_I (match_operand:VEC_I 2 "vlogical_operand" "")
(match_operand:VEC_I 1 "vlogical_operand" "")))
(set (match_operand:VEC_I 0 "vlogical_operand" "")
[(set (match_operand:VEC_I 3 "vlogical_operand")
(gtu:VEC_I (match_operand:VEC_I 2 "vlogical_operand")
(match_operand:VEC_I 1 "vlogical_operand")))
(set (match_operand:VEC_I 0 "vlogical_operand")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
@ -588,18 +588,18 @@
})
(define_expand "vector_geu<mode>"
[(set (match_operand:VEC_I 0 "vint_operand" "")
(geu:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
(match_operand:VEC_I 2 "vint_operand" "")))]
[(set (match_operand:VEC_I 0 "vint_operand")
(geu:VEC_I (match_operand:VEC_I 1 "vint_operand")
(match_operand:VEC_I 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
; <= for integer vectors: apply not-greater-than
(define_expand "vector_ngt<mode>"
[(set (match_operand:VEC_I 3 "vlogical_operand" "")
(gt:VEC_I (match_operand:VEC_I 1 "vlogical_operand" "")
(match_operand:VEC_I 2 "vlogical_operand" "")))
(set (match_operand:VEC_I 0 "vlogical_operand" "")
[(set (match_operand:VEC_I 3 "vlogical_operand")
(gt:VEC_I (match_operand:VEC_I 1 "vlogical_operand")
(match_operand:VEC_I 2 "vlogical_operand")))
(set (match_operand:VEC_I 0 "vlogical_operand")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
@ -607,10 +607,10 @@
})
(define_expand "vector_ngtu<mode>"
[(set (match_operand:VEC_I 3 "vlogical_operand" "")
(gtu:VEC_I (match_operand:VEC_I 1 "vlogical_operand" "")
(match_operand:VEC_I 2 "vlogical_operand" "")))
(set (match_operand:VEC_I 0 "vlogical_operand" "")
[(set (match_operand:VEC_I 3 "vlogical_operand")
(gtu:VEC_I (match_operand:VEC_I 1 "vlogical_operand")
(match_operand:VEC_I 2 "vlogical_operand")))
(set (match_operand:VEC_I 0 "vlogical_operand")
(not:VEC_I (match_dup 3)))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
@ -618,9 +618,9 @@
})
(define_insn_and_split "*vector_uneq<mode>"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")))]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(uneq:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
(match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"#"
""
@ -639,9 +639,9 @@
})
(define_insn_and_split "*vector_ltgt<mode>"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")))]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(ltgt:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
(match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"#"
""
@ -660,9 +660,9 @@
})
(define_insn_and_split "*vector_ordered<mode>"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")))]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(ordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
(match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"#"
""
@ -681,9 +681,9 @@
})
(define_insn_and_split "*vector_unordered<mode>"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" "")))]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(unordered:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
(match_operand:VEC_F 2 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"#"
""
@ -704,22 +704,22 @@
;; Note the arguments for __builtin_altivec_vsel are op2, op1, mask
;; which is in the reverse order that we want
(define_expand "vector_select_<mode>"
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
[(set (match_operand:VEC_L 0 "vlogical_operand")
(if_then_else:VEC_L
(ne:CC (match_operand:VEC_L 3 "vlogical_operand" "")
(ne:CC (match_operand:VEC_L 3 "vlogical_operand")
(match_dup 4))
(match_operand:VEC_L 2 "vlogical_operand" "")
(match_operand:VEC_L 1 "vlogical_operand" "")))]
(match_operand:VEC_L 2 "vlogical_operand")
(match_operand:VEC_L 1 "vlogical_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"operands[4] = CONST0_RTX (<MODE>mode);")
(define_expand "vector_select_<mode>_uns"
[(set (match_operand:VEC_L 0 "vlogical_operand" "")
[(set (match_operand:VEC_L 0 "vlogical_operand")
(if_then_else:VEC_L
(ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand" "")
(ne:CCUNS (match_operand:VEC_L 3 "vlogical_operand")
(match_dup 4))
(match_operand:VEC_L 2 "vlogical_operand" "")
(match_operand:VEC_L 1 "vlogical_operand" "")))]
(match_operand:VEC_L 2 "vlogical_operand")
(match_operand:VEC_L 1 "vlogical_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"operands[4] = CONST0_RTX (<MODE>mode);")
@ -728,10 +728,10 @@
(define_expand "vector_eq_<mode>_p"
[(parallel
[(set (reg:CC CR6_REGNO)
(unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand" "")
(match_operand:VEC_A 2 "vlogical_operand" ""))]
(unspec:CC [(eq:CC (match_operand:VEC_A 1 "vlogical_operand")
(match_operand:VEC_A 2 "vlogical_operand"))]
UNSPEC_PREDICATE))
(set (match_operand:VEC_A 0 "vlogical_operand" "")
(set (match_operand:VEC_A 0 "vlogical_operand")
(eq:VEC_A (match_dup 1)
(match_dup 2)))])]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
@ -895,10 +895,10 @@
(define_expand "vector_gt_<mode>_p"
[(parallel
[(set (reg:CC CR6_REGNO)
(unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand" "")
(match_operand:VEC_A 2 "vlogical_operand" ""))]
(unspec:CC [(gt:CC (match_operand:VEC_A 1 "vlogical_operand")
(match_operand:VEC_A 2 "vlogical_operand"))]
UNSPEC_PREDICATE))
(set (match_operand:VEC_A 0 "vlogical_operand" "")
(set (match_operand:VEC_A 0 "vlogical_operand")
(gt:VEC_A (match_dup 1)
(match_dup 2)))])]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
@ -907,10 +907,10 @@
(define_expand "vector_ge_<mode>_p"
[(parallel
[(set (reg:CC CR6_REGNO)
(unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand" "")
(match_operand:VEC_F 2 "vfloat_operand" ""))]
(unspec:CC [(ge:CC (match_operand:VEC_F 1 "vfloat_operand")
(match_operand:VEC_F 2 "vfloat_operand"))]
UNSPEC_PREDICATE))
(set (match_operand:VEC_F 0 "vfloat_operand" "")
(set (match_operand:VEC_F 0 "vfloat_operand")
(ge:VEC_F (match_dup 1)
(match_dup 2)))])]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
@ -919,10 +919,10 @@
(define_expand "vector_gtu_<mode>_p"
[(parallel
[(set (reg:CC CR6_REGNO)
(unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand" "")
(match_operand:VEC_I 2 "vint_operand" ""))]
(unspec:CC [(gtu:CC (match_operand:VEC_I 1 "vint_operand")
(match_operand:VEC_I 2 "vint_operand"))]
UNSPEC_PREDICATE))
(set (match_operand:VEC_I 0 "vlogical_operand" "")
(set (match_operand:VEC_I 0 "vlogical_operand")
(gtu:VEC_I (match_dup 1)
(match_dup 2)))])]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
@ -984,33 +984,33 @@
;; Vector count leading zeros
(define_expand "clz<mode>2"
[(set (match_operand:VEC_I 0 "register_operand" "")
(clz:VEC_I (match_operand:VEC_I 1 "register_operand" "")))]
[(set (match_operand:VEC_I 0 "register_operand")
(clz:VEC_I (match_operand:VEC_I 1 "register_operand")))]
"TARGET_P8_VECTOR")
;; Vector count trailing zeros
(define_expand "ctz<mode>2"
[(set (match_operand:VEC_I 0 "register_operand" "")
(ctz:VEC_I (match_operand:VEC_I 1 "register_operand" "")))]
[(set (match_operand:VEC_I 0 "register_operand")
(ctz:VEC_I (match_operand:VEC_I 1 "register_operand")))]
"TARGET_P9_VECTOR")
;; Vector population count
(define_expand "popcount<mode>2"
[(set (match_operand:VEC_I 0 "register_operand" "")
(popcount:VEC_I (match_operand:VEC_I 1 "register_operand" "")))]
[(set (match_operand:VEC_I 0 "register_operand")
(popcount:VEC_I (match_operand:VEC_I 1 "register_operand")))]
"TARGET_P8_VECTOR")
;; Vector parity
(define_expand "parity<mode>2"
[(set (match_operand:VEC_IP 0 "register_operand" "")
(parity:VEC_IP (match_operand:VEC_IP 1 "register_operand" "")))]
[(set (match_operand:VEC_IP 0 "register_operand")
(parity:VEC_IP (match_operand:VEC_IP 1 "register_operand")))]
"TARGET_P9_VECTOR")
;; Same size conversions
(define_expand "float<VEC_int><mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
@ -1021,8 +1021,8 @@
})
(define_expand "floatuns<VEC_int><mode>2"
[(set (match_operand:VEC_F 0 "vfloat_operand" "")
(unsigned_float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand" "")))]
[(set (match_operand:VEC_F 0 "vfloat_operand")
(unsigned_float:VEC_F (match_operand:<VEC_INT> 1 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
@ -1033,8 +1033,8 @@
})
(define_expand "fix_trunc<mode><VEC_int>2"
[(set (match_operand:<VEC_INT> 0 "vint_operand" "")
(fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
[(set (match_operand:<VEC_INT> 0 "vint_operand")
(fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
@ -1045,8 +1045,8 @@
})
(define_expand "fixuns_trunc<mode><VEC_int>2"
[(set (match_operand:<VEC_INT> 0 "vint_operand" "")
(unsigned_fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand" "")))]
[(set (match_operand:<VEC_INT> 0 "vint_operand")
(unsigned_fix:<VEC_INT> (match_operand:VEC_F 1 "vfloat_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (<MODE>mode == V4SFmode && VECTOR_UNIT_ALTIVEC_P (<MODE>mode))
@ -1059,8 +1059,8 @@
;; Vector initialization, set, extract
(define_expand "vec_init<mode><VEC_base_l>"
[(match_operand:VEC_E 0 "vlogical_operand" "")
(match_operand:VEC_E 1 "" "")]
[(match_operand:VEC_E 0 "vlogical_operand")
(match_operand:VEC_E 1 "")]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
rs6000_expand_vector_init (operands[0], operands[1]);
@ -1068,9 +1068,9 @@
})
(define_expand "vec_set<mode>"
[(match_operand:VEC_E 0 "vlogical_operand" "")
(match_operand:<VEC_base> 1 "register_operand" "")
(match_operand 2 "const_int_operand" "")]
[(match_operand:VEC_E 0 "vlogical_operand")
(match_operand:<VEC_base> 1 "register_operand")
(match_operand 2 "const_int_operand")]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
rs6000_expand_vector_set (operands[0], operands[1], INTVAL (operands[2]));
@ -1078,9 +1078,9 @@
})
(define_expand "vec_extract<mode><VEC_base_l>"
[(match_operand:<VEC_base> 0 "register_operand" "")
(match_operand:VEC_E 1 "vlogical_operand" "")
(match_operand 2 "const_int_operand" "")]
[(match_operand:<VEC_base> 0 "register_operand")
(match_operand:VEC_E 1 "vlogical_operand")
(match_operand 2 "const_int_operand")]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
rs6000_expand_vector_extract (operands[0], operands[1], operands[2]);
@ -1089,9 +1089,9 @@
;; Convert double word types to single word types
(define_expand "vec_pack_trunc_v2df"
[(match_operand:V4SF 0 "vfloat_operand" "")
(match_operand:V2DF 1 "vfloat_operand" "")
(match_operand:V2DF 2 "vfloat_operand" "")]
[(match_operand:V4SF 0 "vfloat_operand")
(match_operand:V2DF 1 "vfloat_operand")
(match_operand:V2DF 2 "vfloat_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
{
rtx r1 = gen_reg_rtx (V4SFmode);
@ -1104,9 +1104,9 @@
})
(define_expand "vec_pack_sfix_trunc_v2df"
[(match_operand:V4SI 0 "vint_operand" "")
(match_operand:V2DF 1 "vfloat_operand" "")
(match_operand:V2DF 2 "vfloat_operand" "")]
[(match_operand:V4SI 0 "vint_operand")
(match_operand:V2DF 1 "vfloat_operand")
(match_operand:V2DF 2 "vfloat_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
{
rtx r1 = gen_reg_rtx (V4SImode);
@ -1119,9 +1119,9 @@
})
(define_expand "vec_pack_ufix_trunc_v2df"
[(match_operand:V4SI 0 "vint_operand" "")
(match_operand:V2DF 1 "vfloat_operand" "")
(match_operand:V2DF 2 "vfloat_operand" "")]
[(match_operand:V4SI 0 "vint_operand")
(match_operand:V2DF 1 "vfloat_operand")
(match_operand:V2DF 2 "vfloat_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && TARGET_ALTIVEC"
{
rtx r1 = gen_reg_rtx (V4SImode);
@ -1135,8 +1135,8 @@
;; Convert single word types to double word
(define_expand "vec_unpacks_hi_v4sf"
[(match_operand:V2DF 0 "vfloat_operand" "")
(match_operand:V4SF 1 "vfloat_operand" "")]
[(match_operand:V2DF 0 "vfloat_operand")
(match_operand:V4SF 1 "vfloat_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
{
rtx reg = gen_reg_rtx (V4SFmode);
@ -1147,8 +1147,8 @@
})
(define_expand "vec_unpacks_lo_v4sf"
[(match_operand:V2DF 0 "vfloat_operand" "")
(match_operand:V4SF 1 "vfloat_operand" "")]
[(match_operand:V2DF 0 "vfloat_operand")
(match_operand:V4SF 1 "vfloat_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)"
{
rtx reg = gen_reg_rtx (V4SFmode);
@ -1159,8 +1159,8 @@
})
(define_expand "vec_unpacks_float_hi_v4si"
[(match_operand:V2DF 0 "vfloat_operand" "")
(match_operand:V4SI 1 "vint_operand" "")]
[(match_operand:V2DF 0 "vfloat_operand")
(match_operand:V4SI 1 "vint_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
{
rtx reg = gen_reg_rtx (V4SImode);
@ -1171,8 +1171,8 @@
})
(define_expand "vec_unpacks_float_lo_v4si"
[(match_operand:V2DF 0 "vfloat_operand" "")
(match_operand:V4SI 1 "vint_operand" "")]
[(match_operand:V2DF 0 "vfloat_operand")
(match_operand:V4SI 1 "vint_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
{
rtx reg = gen_reg_rtx (V4SImode);
@ -1183,8 +1183,8 @@
})
(define_expand "vec_unpacku_float_hi_v4si"
[(match_operand:V2DF 0 "vfloat_operand" "")
(match_operand:V4SI 1 "vint_operand" "")]
[(match_operand:V2DF 0 "vfloat_operand")
(match_operand:V4SI 1 "vint_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
{
rtx reg = gen_reg_rtx (V4SImode);
@ -1195,8 +1195,8 @@
})
(define_expand "vec_unpacku_float_lo_v4si"
[(match_operand:V2DF 0 "vfloat_operand" "")
(match_operand:V4SI 1 "vint_operand" "")]
[(match_operand:V2DF 0 "vfloat_operand")
(match_operand:V4SI 1 "vint_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode) && VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SImode)"
{
rtx reg = gen_reg_rtx (V4SImode);
@ -1209,10 +1209,10 @@
;; Align vector loads with a permute.
(define_expand "vec_realign_load_<mode>"
[(match_operand:VEC_K 0 "vlogical_operand" "")
(match_operand:VEC_K 1 "vlogical_operand" "")
(match_operand:VEC_K 2 "vlogical_operand" "")
(match_operand:V16QI 3 "vlogical_operand" "")]
[(match_operand:VEC_K 0 "vlogical_operand")
(match_operand:VEC_K 1 "vlogical_operand")
(match_operand:VEC_K 2 "vlogical_operand")
(match_operand:V16QI 3 "vlogical_operand")]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
{
if (BYTES_BIG_ENDIAN)
@ -1234,8 +1234,8 @@
;; Under VSX, vectors of 4/8 byte alignments do not need to be aligned
;; since the load already handles it.
(define_expand "movmisalign<mode>"
[(set (match_operand:VEC_N 0 "nonimmediate_operand" "")
(match_operand:VEC_N 1 "any_operand" ""))]
[(set (match_operand:VEC_N 0 "nonimmediate_operand")
(match_operand:VEC_N 1 "any_operand"))]
"VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_ALLOW_MOVMISALIGN"
"")
@ -1247,9 +1247,9 @@
;; Note that the vec_shr operation is actually defined as
;; 'shift toward element 0' so is a shr for LE and shl for BE.
(define_expand "vec_shr_<mode>"
[(match_operand:VEC_L 0 "vlogical_operand" "")
(match_operand:VEC_L 1 "vlogical_operand" "")
(match_operand:QI 2 "reg_or_short_operand" "")]
[(match_operand:VEC_L 0 "vlogical_operand")
(match_operand:VEC_L 1 "vlogical_operand")
(match_operand:QI 2 "reg_or_short_operand")]
"TARGET_ALTIVEC"
{
rtx bitshift = operands[2];
@ -1296,33 +1296,33 @@
;; Expanders for rotate each element in a vector
(define_expand "vrotl<mode>3"
[(set (match_operand:VEC_I 0 "vint_operand" "")
(rotate:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
(match_operand:VEC_I 2 "vint_operand" "")))]
[(set (match_operand:VEC_I 0 "vint_operand")
(rotate:VEC_I (match_operand:VEC_I 1 "vint_operand")
(match_operand:VEC_I 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
;; Expanders for arithmetic shift left on each vector element
(define_expand "vashl<mode>3"
[(set (match_operand:VEC_I 0 "vint_operand" "")
(ashift:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
(match_operand:VEC_I 2 "vint_operand" "")))]
[(set (match_operand:VEC_I 0 "vint_operand")
(ashift:VEC_I (match_operand:VEC_I 1 "vint_operand")
(match_operand:VEC_I 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
;; Expanders for logical shift right on each vector element
(define_expand "vlshr<mode>3"
[(set (match_operand:VEC_I 0 "vint_operand" "")
(lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
(match_operand:VEC_I 2 "vint_operand" "")))]
[(set (match_operand:VEC_I 0 "vint_operand")
(lshiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand")
(match_operand:VEC_I 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
;; Expanders for arithmetic shift right on each vector element
(define_expand "vashr<mode>3"
[(set (match_operand:VEC_I 0 "vint_operand" "")
(ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand" "")
(match_operand:VEC_I 2 "vint_operand" "")))]
[(set (match_operand:VEC_I 0 "vint_operand")
(ashiftrt:VEC_I (match_operand:VEC_I 1 "vint_operand")
(match_operand:VEC_I 2 "vint_operand")))]
"VECTOR_UNIT_ALTIVEC_OR_VSX_P (<MODE>mode)"
"")
@ -1336,8 +1336,8 @@
(define_expand "reduc_<VEC_reduc:VEC_reduc_name>_scal_<VEC_F:mode>"
[(match_operand:<VEC_base> 0 "register_operand" "")
(VEC_reduc:VEC_F (match_operand:VEC_F 1 "vfloat_operand" "")
[(match_operand:<VEC_base> 0 "register_operand")
(VEC_reduc:VEC_F (match_operand:VEC_F 1 "vfloat_operand")
(unspec:VEC_F [(const_int 0)] UNSPEC_REDUC))]
"VECTOR_UNIT_VSX_P (<VEC_F:MODE>mode)"
{

134
gcc/config/rs6000/vsx.md
View file

@ -652,8 +652,8 @@
(set_attr "length" "12")])
(define_split
[(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "")
(match_operand:VSX_D 1 "vsx_register_operand" ""))]
[(set (match_operand:VSX_D 0 "indexed_or_indirect_operand")
(match_operand:VSX_D 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed"
[(set (match_dup 2)
(vec_select:<MODE>
@ -696,8 +696,8 @@
;; The post-reload split requires that we re-permute the source
;; register in case it is still live.
(define_split
[(set (match_operand:VSX_D 0 "indexed_or_indirect_operand" "")
(match_operand:VSX_D 1 "vsx_register_operand" ""))]
[(set (match_operand:VSX_D 0 "indexed_or_indirect_operand")
(match_operand:VSX_D 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed"
[(set (match_dup 1)
(vec_select:<MODE>
@ -722,8 +722,8 @@
(set_attr "length" "12")])
(define_split
[(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "")
(match_operand:VSX_W 1 "vsx_register_operand" ""))]
[(set (match_operand:VSX_W 0 "indexed_or_indirect_operand")
(match_operand:VSX_W 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed"
[(set (match_dup 2)
(vec_select:<MODE>
@ -768,8 +768,8 @@
;; The post-reload split requires that we re-permute the source
;; register in case it is still live.
(define_split
[(set (match_operand:VSX_W 0 "indexed_or_indirect_operand" "")
(match_operand:VSX_W 1 "vsx_register_operand" ""))]
[(set (match_operand:VSX_W 0 "indexed_or_indirect_operand")
(match_operand:VSX_W 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed"
[(set (match_dup 1)
(vec_select:<MODE>
@ -797,8 +797,8 @@
(set_attr "length" "12")])
(define_split
[(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "")
(match_operand:V8HI 1 "vsx_register_operand" ""))]
[(set (match_operand:V8HI 0 "indexed_or_indirect_operand")
(match_operand:V8HI 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed"
[(set (match_dup 2)
(vec_select:V8HI
@ -847,8 +847,8 @@
;; The post-reload split requires that we re-permute the source
;; register in case it is still live.
(define_split
[(set (match_operand:V8HI 0 "indexed_or_indirect_operand" "")
(match_operand:V8HI 1 "vsx_register_operand" ""))]
[(set (match_operand:V8HI 0 "indexed_or_indirect_operand")
(match_operand:V8HI 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed"
[(set (match_dup 1)
(vec_select:V8HI
@ -882,8 +882,8 @@
(set_attr "length" "12")])
(define_split
[(set (match_operand:V16QI 0 "indexed_or_indirect_operand" "")
(match_operand:V16QI 1 "vsx_register_operand" ""))]
[(set (match_operand:V16QI 0 "indexed_or_indirect_operand")
(match_operand:V16QI 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && !reload_completed"
[(set (match_dup 2)
(vec_select:V16QI
@ -940,8 +940,8 @@
;; The post-reload split requires that we re-permute the source
;; register in case it is still live.
(define_split
[(set (match_operand:V16QI 0 "indexed_or_indirect_operand" "")
(match_operand:V16QI 1 "vsx_register_operand" ""))]
[(set (match_operand:V16QI 0 "indexed_or_indirect_operand")
(match_operand:V16QI 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR && reload_completed"
[(set (match_dup 1)
(vec_select:V16QI
@ -1051,8 +1051,8 @@
(set_attr "length" "12,8")])
(define_split
[(set (match_operand:VSX_LE_128 0 "memory_operand" "")
(match_operand:VSX_LE_128 1 "vsx_register_operand" ""))]
[(set (match_operand:VSX_LE_128 0 "memory_operand")
(match_operand:VSX_LE_128 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !reload_completed && !TARGET_P9_VECTOR"
[(const_int 0)]
{
@ -1093,10 +1093,10 @@
;; VSX registers on a little endian system. The vector types and IEEE 128-bit
;; floating point are handled by the more generic swap elimination pass.
(define_peephole2
[(set (match_operand:TI 0 "vsx_register_operand" "")
(rotate:TI (match_operand:TI 1 "vsx_register_operand" "")
[(set (match_operand:TI 0 "vsx_register_operand")
(rotate:TI (match_operand:TI 1 "vsx_register_operand")
(const_int 64)))
(set (match_operand:TI 2 "vsx_register_operand" "")
(set (match_operand:TI 2 "vsx_register_operand")
(rotate:TI (match_dup 0)
(const_int 64)))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && !TARGET_P9_VECTOR
@ -1107,8 +1107,8 @@
;; The post-reload split requires that we re-permute the source
;; register in case it is still live.
(define_split
[(set (match_operand:VSX_LE_128 0 "memory_operand" "")
(match_operand:VSX_LE_128 1 "vsx_register_operand" ""))]
[(set (match_operand:VSX_LE_128 0 "memory_operand")
(match_operand:VSX_LE_128 1 "vsx_register_operand"))]
"!BYTES_BIG_ENDIAN && TARGET_VSX && reload_completed && !TARGET_P9_VECTOR"
[(const_int 0)]
{
@ -1256,8 +1256,8 @@
;; Explicit load/store expanders for the builtin functions
(define_expand "vsx_load_<mode>"
[(set (match_operand:VSX_M 0 "vsx_register_operand" "")
(match_operand:VSX_M 1 "memory_operand" ""))]
[(set (match_operand:VSX_M 0 "vsx_register_operand")
(match_operand:VSX_M 1 "memory_operand"))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
/* Expand to swaps if needed, prior to swap optimization. */
@ -1269,8 +1269,8 @@
})
(define_expand "vsx_store_<mode>"
[(set (match_operand:VSX_M 0 "memory_operand" "")
(match_operand:VSX_M 1 "vsx_register_operand" ""))]
[(set (match_operand:VSX_M 0 "memory_operand")
(match_operand:VSX_M 1 "vsx_register_operand"))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
/* Expand to swaps if needed, prior to swap optimization. */
@ -1767,10 +1767,10 @@
;; *tdiv* instruction returning the FG flag
(define_expand "vsx_tdiv<mode>3_fg"
[(set (match_dup 3)
(unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")
(match_operand:VSX_B 2 "vsx_register_operand" "")]
(unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand")
(match_operand:VSX_B 2 "vsx_register_operand")]
UNSPEC_VSX_TDIV))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(set (match_operand:SI 0 "gpc_reg_operand")
(gt:SI (match_dup 3)
(const_int 0)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
@ -1781,10 +1781,10 @@
;; *tdiv* instruction returning the FE flag
(define_expand "vsx_tdiv<mode>3_fe"
[(set (match_dup 3)
(unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")
(match_operand:VSX_B 2 "vsx_register_operand" "")]
(unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand")
(match_operand:VSX_B 2 "vsx_register_operand")]
UNSPEC_VSX_TDIV))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(set (match_operand:SI 0 "gpc_reg_operand")
(eq:SI (match_dup 3)
(const_int 0)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
@ -1875,9 +1875,9 @@
;; *tsqrt* returning the fg flag
(define_expand "vsx_tsqrt<mode>2_fg"
[(set (match_dup 2)
(unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")]
(unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand")]
UNSPEC_VSX_TSQRT))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(set (match_operand:SI 0 "gpc_reg_operand")
(gt:SI (match_dup 2)
(const_int 0)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
@ -1888,9 +1888,9 @@
;; *tsqrt* returning the fe flag
(define_expand "vsx_tsqrt<mode>2_fe"
[(set (match_dup 2)
(unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand" "")]
(unspec:CCFP [(match_operand:VSX_B 1 "vsx_register_operand")]
UNSPEC_VSX_TSQRT))
(set (match_operand:SI 0 "gpc_reg_operand" "")
(set (match_operand:SI 0 "gpc_reg_operand")
(eq:SI (match_dup 2)
(const_int 0)))]
"VECTOR_UNIT_VSX_P (<MODE>mode)"
@ -2290,9 +2290,9 @@
;; Convert and scale (used by vec_ctf, vec_cts, vec_ctu for double/long long)
(define_expand "vsx_xvcvsxddp_scale"
[(match_operand:V2DF 0 "vsx_register_operand" "")
(match_operand:V2DI 1 "vsx_register_operand" "")
(match_operand:QI 2 "immediate_operand" "")]
[(match_operand:V2DF 0 "vsx_register_operand")
(match_operand:V2DI 1 "vsx_register_operand")
(match_operand:QI 2 "immediate_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode)"
{
rtx op0 = operands[0];
@ -2313,9 +2313,9 @@
[(set_attr "type" "vecdouble")])
(define_expand "vsx_xvcvuxddp_scale"
[(match_operand:V2DF 0 "vsx_register_operand" "")
(match_operand:V2DI 1 "vsx_register_operand" "")
(match_operand:QI 2 "immediate_operand" "")]
[(match_operand:V2DF 0 "vsx_register_operand")
(match_operand:V2DI 1 "vsx_register_operand")
(match_operand:QI 2 "immediate_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode)"
{
rtx op0 = operands[0];
@ -2336,9 +2336,9 @@
[(set_attr "type" "vecdouble")])
(define_expand "vsx_xvcvdpsxds_scale"
[(match_operand:V2DI 0 "vsx_register_operand" "")
(match_operand:V2DF 1 "vsx_register_operand" "")
(match_operand:QI 2 "immediate_operand" "")]
[(match_operand:V2DI 0 "vsx_register_operand")
(match_operand:V2DF 1 "vsx_register_operand")
(match_operand:QI 2 "immediate_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode)"
{
rtx op0 = operands[0];
@ -2379,9 +2379,9 @@
;; convert vector of 64-bit floating point numbers to vector of
;; 64-bit unsigned integer
(define_expand "vsx_xvcvdpuxds_scale"
[(match_operand:V2DI 0 "vsx_register_operand" "")
(match_operand:V2DF 1 "vsx_register_operand" "")
(match_operand:QI 2 "immediate_operand" "")]
[(match_operand:V2DI 0 "vsx_register_operand")
(match_operand:V2DF 1 "vsx_register_operand")
(match_operand:QI 2 "immediate_operand")]
"VECTOR_UNIT_VSX_P (V2DFmode)"
{
rtx op0 = operands[0];
@ -3148,10 +3148,10 @@
;; Convert a TImode value into V1TImode
(define_expand "vsx_set_v1ti"
[(match_operand:V1TI 0 "nonimmediate_operand" "")
(match_operand:V1TI 1 "nonimmediate_operand" "")
(match_operand:TI 2 "input_operand" "")
(match_operand:QI 3 "u5bit_cint_operand" "")]
[(match_operand:V1TI 0 "nonimmediate_operand")
(match_operand:V1TI 1 "nonimmediate_operand")
(match_operand:TI 2 "input_operand")
(match_operand:QI 3 "u5bit_cint_operand")]
"VECTOR_MEM_VSX_P (V1TImode)"
{
if (operands[3] != const0_rtx)
@ -4065,9 +4065,9 @@
;; Expanders for builtins
(define_expand "vsx_mergel_<mode>"
[(use (match_operand:VSX_D 0 "vsx_register_operand" ""))
(use (match_operand:VSX_D 1 "vsx_register_operand" ""))
(use (match_operand:VSX_D 2 "vsx_register_operand" ""))]
[(use (match_operand:VSX_D 0 "vsx_register_operand"))
(use (match_operand:VSX_D 1 "vsx_register_operand"))
(use (match_operand:VSX_D 2 "vsx_register_operand"))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
rtvec v;
@ -4091,9 +4091,9 @@
})
(define_expand "vsx_mergeh_<mode>"
[(use (match_operand:VSX_D 0 "vsx_register_operand" ""))
(use (match_operand:VSX_D 1 "vsx_register_operand" ""))
(use (match_operand:VSX_D 2 "vsx_register_operand" ""))]
[(use (match_operand:VSX_D 0 "vsx_register_operand"))
(use (match_operand:VSX_D 1 "vsx_register_operand"))
(use (match_operand:VSX_D 2 "vsx_register_operand"))]
"VECTOR_MEM_VSX_P (<MODE>mode)"
{
rtvec v;
@ -4445,21 +4445,21 @@
;; Power8 Vector fusion. The fused ops must be physically adjacent.
(define_peephole
[(set (match_operand:P 0 "base_reg_operand" "")
(match_operand:P 1 "short_cint_operand" ""))
(set (match_operand:VSX_M 2 "vsx_register_operand" "")
[(set (match_operand:P 0 "base_reg_operand")
(match_operand:P 1 "short_cint_operand"))
(set (match_operand:VSX_M 2 "vsx_register_operand")
(mem:VSX_M (plus:P (match_dup 0)
(match_operand:P 3 "int_reg_operand" ""))))]
(match_operand:P 3 "int_reg_operand"))))]
"TARGET_VSX && TARGET_P8_FUSION && !TARGET_P9_VECTOR"
"li %0,%1\;lx<VSX_M:VSm>x %x2,%0,%3\t\t\t# vector load fusion"
[(set_attr "length" "8")
(set_attr "type" "vecload")])
(define_peephole
[(set (match_operand:P 0 "base_reg_operand" "")
(match_operand:P 1 "short_cint_operand" ""))
(set (match_operand:VSX_M 2 "vsx_register_operand" "")
(mem:VSX_M (plus:P (match_operand:P 3 "int_reg_operand" "")
[(set (match_operand:P 0 "base_reg_operand")
(match_operand:P 1 "short_cint_operand"))
(set (match_operand:VSX_M 2 "vsx_register_operand")
(mem:VSX_M (plus:P (match_operand:P 3 "int_reg_operand")
(match_dup 0))))]
"TARGET_VSX && TARGET_P8_FUSION && !TARGET_P9_VECTOR"
"li %0,%1\;lx<VSX_M:VSm>x %x2,%0,%3\t\t\t# vector load fusion"