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[AArch64] Don't allow partial SVE modes in GPRs

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With -msve-vector-bits=N, the payload of some partial SVE modes can
be 16 bytes or smaller, which makes them small enough to fit in a
pair of GPRs.  We specifically don't want that, because the payload
is distributed evenly across the SVE register rather than collected
at one end.  Marshalling it into a GPR via register operations would
be expensive.

2019-12-10  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	* config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Don't
	allow SVE modes in GPRs.

gcc/testsuite/
	* gcc.target/aarch64/sve/mixed_size_7.c: New test.

From-SVN: r279174
This commit is contained in:
Richard Sandiford 2019-12-10 16:46:05 +00:00 • committed by Richard Sandiford
parent 30f8bf3d6c
commit aa1a27950a
4 changed files with 40 additions and 1 deletions
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5
gcc/ChangeLog
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@ -1,3 +1,8 @@
2019-12-10 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Don't
allow SVE modes in GPRs.
2019-12-10 Richard Sandiford <richard.sandiford@arm.com>
* config/aarch64/iterators.md (vccore): New iterator.

4
gcc/config/aarch64/aarch64.c
View file

@ -2019,9 +2019,11 @@ aarch64_hard_regno_mode_ok (unsigned regno, machine_mode mode)
if (GP_REGNUM_P (regno))
{
if (vec_flags & VEC_ANY_SVE)
return false;
if (known_le (GET_MODE_SIZE (mode), 8))
return true;
else if (known_le (GET_MODE_SIZE (mode), 16))
if (known_le (GET_MODE_SIZE (mode), 16))
return (regno & 1) == 0;
}
else if (FP_REGNUM_P (regno))

4
gcc/testsuite/ChangeLog
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@ -1,3 +1,7 @@
2019-12-10 Richard Sandiford <richard.sandiford@arm.com>
* gcc.target/aarch64/sve/mixed_size_7.c: New test.
2019-12-10 Richard Sandiford <richard.sandiford@arm.com>
* gcc.target/aarch64/sve/mixed_size_6.c: New test.

28
gcc/testsuite/gcc.target/aarch64/sve/mixed_size_7.c Normal file
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@ -0,0 +1,28 @@
/* Originally gcc.dg/vect/bb-slp-6.c */
/* { dg-options "-O2 -ftree-vectorize -msve-vector-bits=256 -fno-vect-cost-model" } */
#define N 16
unsigned int out[N];
unsigned int in[N] = {0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15};
__attribute__ ((noinline)) int
main1 (unsigned int x, unsigned int y)
{
int i;
unsigned int *pin = &in[0];
unsigned int *pout = &out[0];
unsigned int a0, a1, a2, a3;
a0 = *pin++ + 23;
a1 = *pin++ + 142;
a2 = *pin++ + 2;
a3 = *pin++ + 31;
*pout++ = a0 * x;
*pout++ = a1 * y;
*pout++ = a2 * x;
*pout++ = a3 * y;
return 0;
}