arm.c (output_move_neon): Update comment.
2012-09-17 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org> Ulrich Weigand <ulrich.weigand@linaro.org> * config/arm/arm.c (output_move_neon): Update comment. Use vld1.64/vst1.64 instead of vldm/vstm where possible. (neon_vector_mem_operand): Support double-word modes. * config/arm/neon.md (*neon_mov VD): Call output_move_neon instead of output_move_vfp. Change constraint from Uv to Un. Co-Authored-By: Ulrich Weigand <ulrich.weigand@linaro.org> From-SVN: r191399
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Ramana Radhakrishnan
Ulrich Weigand
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3 changed files with 62 additions and 23 deletions
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@ -1,3 +1,12 @@
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2012-09-17 Ramana Radhakrishnan <ramana.radhakrishnan@linaro.org>
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Ulrich Weigand <ulrich.weigand@linaro.org>
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* config/arm/arm.c (output_move_neon): Update comment.
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Use vld1.64/vst1.64 instead of vldm/vstm where possible.
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(neon_vector_mem_operand): Support double-word modes.
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* config/arm/neon.md (*neon_mov VD): Call output_move_neon
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instead of output_move_vfp. Change constraint from Uv to Un.
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2012-09-17 Richard Guenther <rguenther@suse.de>
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PR lto/54598
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@ -9629,7 +9629,11 @@ neon_vector_mem_operand (rtx op, int type)
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&& REG_MODE_OK_FOR_BASE_P (XEXP (ind, 0), VOIDmode)
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&& CONST_INT_P (XEXP (ind, 1))
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&& INTVAL (XEXP (ind, 1)) > -1024
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&& INTVAL (XEXP (ind, 1)) < 1016
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/* For quad modes, we restrict the constant offset to be slightly less
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than what the instruction format permits. We have no such constraint
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on double mode offsets. (This must match arm_legitimate_index_p.) */
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&& (INTVAL (XEXP (ind, 1))
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< (VALID_NEON_QREG_MODE (GET_MODE (op))? 1016 : 1024))
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&& (INTVAL (XEXP (ind, 1)) & 3) == 0)
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return TRUE;
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@ -14573,15 +14577,16 @@ output_move_vfp (rtx *operands)
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return "";
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}
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/* Output a Neon quad-word load or store, or a load or store for
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larger structure modes.
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/* Output a Neon double-word or quad-word load or store, or a load
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or store for larger structure modes.
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WARNING: The ordering of elements is weird in big-endian mode,
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because we use VSTM, as required by the EABI. GCC RTL defines
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element ordering based on in-memory order. This can be differ
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from the architectural ordering of elements within a NEON register.
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The intrinsics defined in arm_neon.h use the NEON register element
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ordering, not the GCC RTL element ordering.
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because the EABI requires that vectors stored in memory appear
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as though they were stored by a VSTM, as required by the EABI.
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GCC RTL defines element ordering based on in-memory order.
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This can be different from the architectural ordering of elements
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within a NEON register. The intrinsics defined in arm_neon.h use the
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NEON register element ordering, not the GCC RTL element ordering.
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For example, the in-memory ordering of a big-endian a quadword
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vector with 16-bit elements when stored from register pair {d0,d1}
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@ -14595,13 +14600,28 @@ output_move_vfp (rtx *operands)
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dN -> (rN+1, rN), dN+1 -> (rN+3, rN+2)
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So that STM/LDM can be used on vectors in ARM registers, and the
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same memory layout will result as if VSTM/VLDM were used. */
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same memory layout will result as if VSTM/VLDM were used.
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Instead of VSTM/VLDM we prefer to use VST1.64/VLD1.64 where
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possible, which allows use of appropriate alignment tags.
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Note that the choice of "64" is independent of the actual vector
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element size; this size simply ensures that the behavior is
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equivalent to VSTM/VLDM in both little-endian and big-endian mode.
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Due to limitations of those instructions, use of VST1.64/VLD1.64
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is not possible if:
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- the address contains PRE_DEC, or
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- the mode refers to more than 4 double-word registers
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In those cases, it would be possible to replace VSTM/VLDM by a
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sequence of instructions; this is not currently implemented since
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this is not certain to actually improve performance. */
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const char *
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output_move_neon (rtx *operands)
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{
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rtx reg, mem, addr, ops[2];
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int regno, load = REG_P (operands[0]);
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int regno, nregs, load = REG_P (operands[0]);
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const char *templ;
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char buff[50];
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enum machine_mode mode;
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@ -14613,6 +14633,7 @@ output_move_neon (rtx *operands)
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gcc_assert (REG_P (reg));
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regno = REGNO (reg);
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nregs = HARD_REGNO_NREGS (regno, mode) / 2;
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gcc_assert (VFP_REGNO_OK_FOR_DOUBLE (regno)
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|| NEON_REGNO_OK_FOR_QUAD (regno));
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gcc_assert (VALID_NEON_DREG_MODE (mode)
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@ -14629,13 +14650,23 @@ output_move_neon (rtx *operands)
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switch (GET_CODE (addr))
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{
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case POST_INC:
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templ = "v%smia%%?\t%%0!, %%h1";
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ops[0] = XEXP (addr, 0);
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/* We have to use vldm / vstm for too-large modes. */
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if (nregs > 4)
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{
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templ = "v%smia%%?\t%%0!, %%h1";
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ops[0] = XEXP (addr, 0);
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}
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else
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{
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templ = "v%s1.64\t%%h1, %%A0";
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ops[0] = mem;
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}
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ops[1] = reg;
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break;
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case PRE_DEC:
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/* FIXME: We should be using vld1/vst1 here in BE mode? */
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/* We have to use vldm / vstm in this case, since there is no
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pre-decrement form of the vld1 / vst1 instructions. */
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templ = "v%smdb%%?\t%%0!, %%h1";
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ops[0] = XEXP (addr, 0);
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ops[1] = reg;
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@ -14648,7 +14679,6 @@ output_move_neon (rtx *operands)
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case LABEL_REF:
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case PLUS:
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{
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int nregs = HARD_REGNO_NREGS (REGNO (reg), mode) / 2;
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int i;
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int overlap = -1;
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for (i = 0; i < nregs; i++)
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@ -14679,7 +14709,12 @@ output_move_neon (rtx *operands)
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}
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default:
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templ = "v%smia%%?\t%%m0, %%h1";
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/* We have to use vldm / vstm for too-large modes. */
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if (nregs > 4)
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templ = "v%smia%%?\t%%m0, %%h1";
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else
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templ = "v%s1.64\t%%h1, %%A0";
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ops[0] = mem;
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ops[1] = reg;
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}
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@ -156,9 +156,9 @@
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(define_insn "*neon_mov<mode>"
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[(set (match_operand:VDX 0 "nonimmediate_operand"
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"=w,Uv,w, w, ?r,?w,?r,?r, ?Us")
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"=w,Un,w, w, ?r,?w,?r,?r, ?Us")
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(match_operand:VDX 1 "general_operand"
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" w,w, Dn,Uvi, w, r, r, Usi,r"))]
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" w,w, Dn,Uni, w, r, r, Usi,r"))]
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"TARGET_NEON
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&& (register_operand (operands[0], <MODE>mode)
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|| register_operand (operands[1], <MODE>mode))"
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@ -181,15 +181,10 @@
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return templ;
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}
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/* FIXME: If the memory layout is changed in big-endian mode, output_move_vfp
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below must be changed to output_move_neon (which will use the
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element/structure loads/stores), and the constraint changed to 'Um' instead
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of 'Uv'. */
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switch (which_alternative)
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{
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case 0: return "vmov\t%P0, %P1 @ <mode>";
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case 1: case 3: return output_move_vfp (operands);
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case 1: case 3: return output_move_neon (operands);
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case 2: gcc_unreachable ();
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case 4: return "vmov\t%Q0, %R0, %P1 @ <mode>";
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case 5: return "vmov\t%P0, %Q1, %R1 @ <mode>";
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