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rs6000-opts.h (enum processor_type): Add PROCESSOR_PPC8548.

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* config/rs6000/rs6000-opts.h (enum processor_type): Add
        PROCESSOR_PPC8548.
        * config/rs6000/rs6000-cpus.def: Reference it for cpu="8548".
        * config/rs6000/rs6000.md (cpu attribute definition): Add ppc8548.
        * config/rs6000/8540.md: indicate that the units/patterns apply to
        ppc8548 as well.

        * config/rs6000/rs6000.c (rs6000_option_override_internal): Rename
        default_cpu into implicit_cpu, conveying what --with-cpu was passed at
        configure time. Treat implicit_cpu as have_CPU. Pick defaults for SPE
        related flags,  check that what is queried is supported by the selected
        configuration. Rework the single/double_float and MASK_STRING resets to
        hit for all the E500 cores (854x + E500MC variants). Select the ppc8540
        costs for PROCESSOR_PPC8548 as well.
        (rs6000_issue_rate): case CPU_PPC8548 together with CPU_PPC8540.
        (rs6000_use_sched_lookahead): Likewise, rewriting function as a case
        statement instead of a sequence of ifs.

        * config/rs6000/rs6000.h (TARGET_E500): Remove.
        (TARGET_NO_LWSYNC): Adjust accordingly.
        * config/rs6000/e500.h (TARGET_E500): Remove.
        (CHECK_E500_OPTIONS): Adjust accordingly.
        * config/rs6000/eabispe.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Remove.
        (TARGET_DEFAULT): Reformat definition to match the one in linuxspe.h.
        * config/rs6000/linuxspe.h: Likewise.
        * config/rs6000/vxworks.h: Remove bogus TARGET_E500 overrides and
        superfluous comments.
        * config/rs6000/e500-double.h: Remove.

        * config.gcc (pick a default with_cpu): For powerpc*-*-*spe*,
        default to with_cpu=8548 if --enable-e500-double, and to 8540
        otherwise.
        (set misc flags section): For powerpc*|rs6000*, remove inclusion
        of e500-double.h for --enable-e500-double.

From-SVN: r187581
This commit is contained in:
Olivier Hainque 2012-05-16 08:43:41 +00:00 • committed by Olivier Hainque
parent af0a7a9227
commit a7c6c6d64d
14 changed files with 179 additions and 182 deletions
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37
gcc/ChangeLog
View file

@ -1,3 +1,40 @@
2012-05-16 Olivier Hainque <hainque@adacore.com>
* config/rs6000/rs6000-opts.h (enum processor_type): Add
PROCESSOR_PPC8548.
* config/rs6000/rs6000-cpus.def: Reference it for cpu="8548".
* config/rs6000/rs6000.md (cpu attribute definition): Add ppc8548.
* config/rs6000/8540.md: indicate that the units/patterns apply to
ppc8548 as well.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Rename
default_cpu into implicit_cpu, conveying what --with-cpu was passed at
configure time. Treat implicit_cpu as have_CPU. Pick defaults for SPE
related flags, check that what is queried is supported by the selected
configuration. Rework the single/double_float and MASK_STRING resets to
hit for all the E500 cores (854x + E500MC variants). Select the ppc8540
costs for PROCESSOR_PPC8548 as well.
(rs6000_issue_rate): case CPU_PPC8548 together with CPU_PPC8540.
(rs6000_use_sched_lookahead): Likewise, rewriting function as a case
statement instead of a sequence of ifs.
* config/rs6000/rs6000.h (TARGET_E500): Remove.
(TARGET_NO_LWSYNC): Adjust accordingly.
* config/rs6000/e500.h (TARGET_E500): Remove.
(CHECK_E500_OPTIONS): Adjust accordingly.
* config/rs6000/eabispe.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Remove.
(TARGET_DEFAULT): Reformat definition to match the one in linuxspe.h.
* config/rs6000/linuxspe.h: Likewise.
* config/rs6000/vxworks.h: Remove bogus TARGET_E500 overrides and
superfluous comments.
* config/rs6000/e500-double.h: Remove.
* config.gcc (pick a default with_cpu): For powerpc*-*-*spe*,
default to with_cpu=8548 if --enable-e500-double, and to 8540
otherwise.
(set misc flags section): For powerpc*|rs6000*, remove inclusion
of e500-double.h for --enable-e500-double.
2012-05-16 Olivier Hainque <hainque@adacore.com>
* Makefile.in (s-header-vars): Resort to -n instead of trailing

12
gcc/config.gcc
View file

@ -2828,6 +2828,13 @@ if test x$with_cpu = x ; then
mips*-*-vxworks)
with_arch=mips2
;;
powerpc*-*-*spe*)
if test x$enable_e500_double = xyes; then
with_cpu=8548
else
with_cpu=8540
fi
;;
sparc-leon*-*)
with_cpu=v8;
;;
@ -3509,11 +3516,6 @@ case ${target} in
c_target_objs="${c_target_objs} rs6000-c.o"
cxx_target_objs="${cxx_target_objs} rs6000-c.o"
tmake_file="rs6000/t-rs6000 ${tmake_file}"
if test x$enable_e500_double = xyes
then
tm_file="$tm_file rs6000/e500-double.h"
fi
;;
sh[123456ble]*-*-* | sh-*-*)

50
gcc/config/rs6000/8540.md
View file

@ -87,18 +87,18 @@
(and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\
delayed_compare,var_delayed_compare,fast_compare,\
shift,trap,var_shift_rotate,cntlz,exts,isel")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
(define_insn_reservation "ppc8540_two" 1
(and (eq_attr "type" "two")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
(define_insn_reservation "ppc8540_three" 1
(and (eq_attr "type" "three")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
@ -106,13 +106,13 @@
;; Branch. Actually this latency time is not used by the scheduler.
(define_insn_reservation "ppc8540_branch" 1
(and (eq_attr "type" "jmpreg,branch,isync")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_bu,ppc8540_retire")
;; Multiply
(define_insn_reservation "ppc8540_multiply" 4
(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
@ -122,57 +122,57 @@
;; time.
(define_insn_reservation "ppc8540_divide" 14
(and (eq_attr "type" "idiv")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
ppc8540_mu_div*13")
;; CR logical
(define_insn_reservation "ppc8540_cr_logical" 1
(and (eq_attr "type" "cr_logical,delayed_cr")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_bu,ppc8540_retire")
;; Mfcr
(define_insn_reservation "ppc8540_mfcr" 1
(and (eq_attr "type" "mfcr")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
;; Mtcrf
(define_insn_reservation "ppc8540_mtcrf" 1
(and (eq_attr "type" "mtcr")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
;; Mtjmpr
(define_insn_reservation "ppc8540_mtjmpr" 1
(and (eq_attr "type" "mtjmpr,mfjmpr")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
;; Loads
(define_insn_reservation "ppc8540_load" 3
(and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\
load_l,sync")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
;; Stores.
(define_insn_reservation "ppc8540_store" 3
(and (eq_attr "type" "store,store_ux,store_u,store_c")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
;; Simple FP
(define_insn_reservation "ppc8540_simple_float" 1
(and (eq_attr "type" "fpsimple")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
;; FP
(define_insn_reservation "ppc8540_float" 4
(and (eq_attr "type" "fp")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
@ -180,44 +180,44 @@
;; because of the result automata will be huge.
(define_insn_reservation "ppc8540_float_vector_divide" 29
(and (eq_attr "type" "vecfdiv")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
ppc8540_mu_div*28")
;; Brinc
(define_insn_reservation "ppc8540_brinc" 1
(and (eq_attr "type" "brinc")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
;; Simple vector
(define_insn_reservation "ppc8540_simple_vector" 1
(and (eq_attr "type" "vecsimple")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
;; Simple vector compare
(define_insn_reservation "ppc8540_simple_vector_compare" 1
(and (eq_attr "type" "veccmpsimple")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
;; Vector compare
(define_insn_reservation "ppc8540_vector_compare" 1
(and (eq_attr "type" "veccmp")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
;; evsplatfi evsplati
(define_insn_reservation "ppc8540_vector_perm" 1
(and (eq_attr "type" "vecperm")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su1_stage0+ppc8540_retire")
;; Vector float
(define_insn_reservation "ppc8540_float_vector" 4
(and (eq_attr "type" "vecfloat")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
@ -226,25 +226,25 @@
;; of miu_stage3 here because we use the average latency time.
(define_insn_reservation "ppc8540_vector_divide" 14
(and (eq_attr "type" "vecdiv")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0+ppc8540_mu_div,\
ppc8540_mu_div*13")
;; Complex vector.
(define_insn_reservation "ppc8540_complex_vector" 4
(and (eq_attr "type" "veccomplex")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
;; Vector load
(define_insn_reservation "ppc8540_vector_load" 3
(and (eq_attr "type" "vecload")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")
;; Vector store
(define_insn_reservation "ppc8540_vector_store" 3
(and (eq_attr "type" "vecstore")
(eq_attr "cpu" "ppc8540"))
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_lsu,nothing,ppc8540_retire")

24
gcc/config/rs6000/e500-double.h
View file

@ -1,24 +0,0 @@
/* Target definitions for E500 with double precision FP.
Copyright (C) 2004, 2006, 2007, 2011 Free Software Foundation, Inc.
Contributed by Aldy Hernandez (aldyh@redhat.com).
This file is part of GCC.
GCC is free software; you can redistribute it and/or modify it
under the terms of the GNU General Public License as published
by the Free Software Foundation; either version 3, or (at your
option) any later version.
GCC is distributed in the hope that it will be useful, but WITHOUT
ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
License for more details.
You should have received a copy of the GNU General Public License
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
#undef SUB3TARGET_OVERRIDE_OPTIONS
#define SUB3TARGET_OVERRIDE_OPTIONS \
if (!global_options_set.x_rs6000_float_gprs) \
rs6000_float_gprs = 2;

10
gcc/config/rs6000/e500.h
View file

@ -19,7 +19,6 @@
#undef TARGET_SPE_ABI
#undef TARGET_SPE
#undef TARGET_E500
#undef TARGET_FPRS
#undef TARGET_E500_SINGLE
#undef TARGET_E500_DOUBLE
@ -27,21 +26,20 @@
#define TARGET_SPE_ABI rs6000_spe_abi
#define TARGET_SPE rs6000_spe
#define TARGET_E500 (rs6000_cpu == PROCESSOR_PPC8540)
#define TARGET_FPRS (rs6000_float_gprs == 0)
#define TARGET_E500_SINGLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 1)
#define TARGET_E500_DOUBLE (TARGET_HARD_FLOAT && rs6000_float_gprs == 2)
#define CHECK_E500_OPTIONS \
do { \
if (TARGET_E500 || TARGET_SPE || TARGET_SPE_ABI \
if (TARGET_SPE || TARGET_SPE_ABI \
|| TARGET_E500_SINGLE || TARGET_E500_DOUBLE) \
{ \
if (TARGET_ALTIVEC) \
error ("AltiVec and E500 instructions cannot coexist"); \
error ("AltiVec and SPE instructions cannot coexist"); \
if (TARGET_VSX) \
error ("VSX and E500 instructions cannot coexist"); \
error ("VSX and SPE instructions cannot coexist"); \
if (TARGET_64BIT) \
error ("64-bit E500 not supported"); \
error ("64-bit SPE not supported"); \
if (TARGET_HARD_FLOAT && TARGET_FPRS) \
error ("E500 and FPRs not supported"); \
} \

17
gcc/config/rs6000/eabispe.h
View file

@ -21,21 +21,8 @@
<http://www.gnu.org/licenses/>. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_EABI \
| MASK_STRICT_ALIGN)
#undef SUBSUBTARGET_OVERRIDE_OPTIONS
#define SUBSUBTARGET_OVERRIDE_OPTIONS \
if (!global_options_set.x_rs6000_cpu_index) \
rs6000_cpu = PROCESSOR_PPC8540; \
if (!global_options_set.x_rs6000_spe_abi) \
rs6000_spe_abi = 1; \
if (!global_options_set.x_rs6000_float_gprs) \
rs6000_float_gprs = 1; \
if (!global_options_set.x_rs6000_spe) \
rs6000_spe = 1; \
if (target_flags & MASK_64BIT) \
error ("-m64 not supported in this configuration")
#define TARGET_DEFAULT \
(MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN | MASK_EABI)
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mppc -mspe -me500"

16
gcc/config/rs6000/linuxspe.h
View file

@ -22,20 +22,8 @@
/* Override rs6000.h and sysv4.h definition. */
#undef TARGET_DEFAULT
#define TARGET_DEFAULT (MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN)
#undef SUBSUBTARGET_OVERRIDE_OPTIONS
#define SUBSUBTARGET_OVERRIDE_OPTIONS \
if (!global_options_set.x_rs6000_cpu_index) \
rs6000_cpu = PROCESSOR_PPC8540; \
if (!global_options_set.x_rs6000_spe_abi) \
rs6000_spe_abi = 1; \
if (!global_options_set.x_rs6000_float_gprs) \
rs6000_float_gprs = 1; \
if (!global_options_set.x_rs6000_spe) \
rs6000_spe = 1; \
if (target_flags & MASK_64BIT) \
error ("-m64 not supported in this configuration")
#define TARGET_DEFAULT \
(MASK_POWERPC | MASK_NEW_MNEMONICS | MASK_STRICT_ALIGN)
#undef ASM_DEFAULT_SPEC
#define ASM_DEFAULT_SPEC "-mppc -mspe -me500"

3
gcc/config/rs6000/rs6000-cpus.def
View file

@ -76,8 +76,7 @@ RS6000_CPU ("821", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT)
RS6000_CPU ("823", PROCESSOR_MPCCORE, POWERPC_BASE_MASK | MASK_SOFT_FLOAT)
RS6000_CPU ("8540", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN
| MASK_ISEL)
/* 8548 has a dummy entry for now. */
RS6000_CPU ("8548", PROCESSOR_PPC8540, POWERPC_BASE_MASK | MASK_STRICT_ALIGN
RS6000_CPU ("8548", PROCESSOR_PPC8548, POWERPC_BASE_MASK | MASK_STRICT_ALIGN
| MASK_ISEL)
RS6000_CPU ("a2", PROCESSOR_PPCA2,
POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64 | MASK_POPCNTB

1
gcc/config/rs6000/rs6000-opts.h
View file

@ -49,6 +49,7 @@ enum processor_type
PROCESSOR_PPC7400,
PROCESSOR_PPC7450,
PROCESSOR_PPC8540,
PROCESSOR_PPC8548,
PROCESSOR_PPCE300C2,
PROCESSOR_PPCE300C3,
PROCESSOR_PPCE500MC,

157
gcc/config/rs6000/rs6000.c
View file

@ -2592,7 +2592,10 @@ rs6000_option_override_internal (bool global_init_p)
{
bool ret = true;
bool have_cpu = false;
const char *default_cpu = OPTION_TARGET_CPU_DEFAULT;
/* The default cpu requested at configure time, if any. */
const char *implicit_cpu = OPTION_TARGET_CPU_DEFAULT;
int set_masks;
int cpu_index;
int tune_index;
@ -2611,11 +2614,6 @@ rs6000_option_override_internal (bool global_init_p)
warning (0, "-malign-power is not supported for 64-bit Darwin;"
" it is incompatible with the installed C and C++ libraries");
if (global_options_set.x_rs6000_spe_abi
&& rs6000_spe_abi
&& !TARGET_SPE_ABI)
error ("not configured for SPE ABI");
/* Numerous experiment shows that IRA based loop pressure
calculation works better for RTL loop invariant motion on targets
with enough (>= 32) registers. It is an expensive optimization.
@ -2651,7 +2649,8 @@ rs6000_option_override_internal (bool global_init_p)
/* Process the -mcpu=<xxx> and -mtune=<xxx> argument. If the user changed
the cpu in a target attribute or pragma, but did not specify a tuning
option, use the cpu for the tuning option rather than the option specified
with -mtune on the command line. */
with -mtune on the command line. Process a '--with-cpu' configuration
request as an implicit --cpu. */
if (rs6000_cpu_index >= 0)
{
cpu_index = rs6000_cpu_index;
@ -2664,10 +2663,12 @@ rs6000_option_override_internal (bool global_init_p)
}
else
{
if (!default_cpu)
default_cpu = (TARGET_POWERPC64 ? "powerpc64" : "powerpc");
const char *default_cpu =
(implicit_cpu ? implicit_cpu
: (TARGET_POWERPC64 ? "powerpc64" : "powerpc"));
rs6000_cpu_index = cpu_index = rs6000_cpu_name_lookup (default_cpu);
have_cpu = implicit_cpu != 0;
}
gcc_assert (cpu_index >= 0);
@ -2698,6 +2699,42 @@ rs6000_option_override_internal (bool global_init_p)
gcc_assert (tune_index >= 0);
rs6000_cpu = processor_target_table[tune_index].processor;
/* Pick defaults for SPE related control flags. Do this early to make sure
that the TARGET_ macros are representative ASAP. */
{
int spe_capable_cpu =
(rs6000_cpu == PROCESSOR_PPC8540
|| rs6000_cpu == PROCESSOR_PPC8548);
if (!global_options_set.x_rs6000_spe_abi)
rs6000_spe_abi = spe_capable_cpu;
if (!global_options_set.x_rs6000_spe)
rs6000_spe = spe_capable_cpu;
if (!global_options_set.x_rs6000_float_gprs)
rs6000_float_gprs =
(rs6000_cpu == PROCESSOR_PPC8540 ? 1
: rs6000_cpu == PROCESSOR_PPC8548 ? 2
: 0);
}
if (global_options_set.x_rs6000_spe_abi
&& rs6000_spe_abi
&& !TARGET_SPE_ABI)
error ("not configured for SPE ABI");
if (global_options_set.x_rs6000_spe
&& rs6000_spe
&& !TARGET_SPE)
error ("not configured for SPE instruction set");
if (main_target_opt != NULL
&& ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi)
|| (main_target_opt->x_rs6000_spe != rs6000_spe)
|| (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs)))
error ("target attribute or pragma changes SPE ABI");
if (rs6000_cpu == PROCESSOR_PPCE300C2 || rs6000_cpu == PROCESSOR_PPCE300C3
|| rs6000_cpu == PROCESSOR_PPCE500MC || rs6000_cpu == PROCESSOR_PPCE500MC64)
{
@ -2933,35 +2970,44 @@ rs6000_option_override_internal (bool global_init_p)
SUB3TARGET_OVERRIDE_OPTIONS;
#endif
if (TARGET_E500 || rs6000_cpu == PROCESSOR_PPCE500MC
|| rs6000_cpu == PROCESSOR_PPCE500MC64)
/* For the E500 family of cores, reset the single/double FP flags to let us
check that they remain constant across attributes or pragmas. Also,
clear a possible request for string instructions, not supported and which
we might have silently queried above for -Os.
For other families, clear ISEL in case it was set implicitly.
*/
switch (rs6000_cpu)
{
/* The e500 and e500mc do not have string instructions, and we set
MASK_STRING above when optimizing for size. */
if ((target_flags & MASK_STRING) != 0)
target_flags = target_flags & ~MASK_STRING;
}
else if (global_options_set.x_rs6000_cpu_index)
{
/* For the powerpc-eabispe configuration, we set all these by
default, so let's unset them if we manually set another
CPU that is not the E500. */
if (main_target_opt != NULL
&& ((main_target_opt->x_rs6000_spe_abi != rs6000_spe_abi)
|| (main_target_opt->x_rs6000_spe != rs6000_spe)
|| (main_target_opt->x_rs6000_float_gprs != rs6000_float_gprs)))
error ("target attribute or pragma changes SPE ABI");
else
{
if (!global_options_set.x_rs6000_spe_abi)
rs6000_spe_abi = 0;
if (!global_options_set.x_rs6000_spe)
rs6000_spe = 0;
if (!global_options_set.x_rs6000_float_gprs)
rs6000_float_gprs = 0;
}
if (!(target_flags_explicit & MASK_ISEL))
case PROCESSOR_PPC8540:
case PROCESSOR_PPC8548:
case PROCESSOR_PPCE500MC:
case PROCESSOR_PPCE500MC64:
rs6000_single_float = TARGET_E500_SINGLE || TARGET_E500_DOUBLE;
rs6000_double_float = TARGET_E500_DOUBLE;
target_flags &= ~MASK_STRING;
break;
default:
if (have_cpu && !(target_flags_explicit & MASK_ISEL))
target_flags &= ~MASK_ISEL;
break;
}
if (main_target_opt)
{
if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
error ("target attribute or pragma changes single precision floating "
"point");
if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
error ("target attribute or pragma changes double precision floating "
"point");
}
/* Detect invalid option combinations with E500. */
@ -3188,6 +3234,7 @@ rs6000_option_override_internal (bool global_init_p)
break;
case PROCESSOR_PPC8540:
case PROCESSOR_PPC8548:
rs6000_cost = &ppc8540_cost;
break;
@ -3260,26 +3307,6 @@ rs6000_option_override_internal (bool global_init_p)
&& rs6000_single_float == 0 && rs6000_double_float == 0)
rs6000_single_float = rs6000_double_float = 1;
/* Reset single and double FP flags if target is E500. */
if (TARGET_E500)
{
rs6000_single_float = rs6000_double_float = 0;
if (TARGET_E500_SINGLE)
rs6000_single_float = 1;
if (TARGET_E500_DOUBLE)
rs6000_single_float = rs6000_double_float = 1;
}
if (main_target_opt)
{
if (main_target_opt->x_rs6000_single_float != rs6000_single_float)
error ("target attribute or pragma changes single precision floating "
"point");
if (main_target_opt->x_rs6000_double_float != rs6000_double_float)
error ("target attribute or pragma changes double precision floating "
"point");
}
/* If not explicitly specified via option, decide whether to generate indexed
load/store instructions. */
if (TARGET_AVOID_XFORM == -1)
@ -23126,6 +23153,7 @@ rs6000_issue_rate (void)
case CPU_PPC750:
case CPU_PPC7400:
case CPU_PPC8540:
case CPU_PPC8548:
case CPU_CELL:
case CPU_PPCE300C2:
case CPU_PPCE300C3:
@ -23156,11 +23184,18 @@ rs6000_issue_rate (void)
static int
rs6000_use_sched_lookahead (void)
{
if (rs6000_cpu_attr == CPU_PPC8540)
return 4;
if (rs6000_cpu_attr == CPU_CELL)
return (reload_completed ? 8 : 0);
return 0;
switch (rs6000_cpu_attr)
{
case CPU_PPC8540:
case CPU_PPC8548:
return 4;
case CPU_CELL:
return (reload_completed ? 8 : 0);
default:
return 0;
}
}
/* We are choosing insn from the ready queue. Return nonzero if INSN can be chosen. */

7
gcc/config/rs6000/rs6000.h
View file

@ -457,7 +457,6 @@ extern int rs6000_vector_align[];
#define TARGET_SPE_ABI 0
#define TARGET_SPE 0
#define TARGET_E500 0
#define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64)
#define TARGET_FPRS 1
#define TARGET_E500_SINGLE 0
@ -500,11 +499,11 @@ extern int rs6000_vector_align[];
|| TARGET_ALTIVEC \
|| TARGET_VSX)))
/* E500 cores only support plain "sync", not lwsync. */
#define TARGET_NO_LWSYNC (rs6000_cpu == PROCESSOR_PPC8540 \
|| rs6000_cpu == PROCESSOR_PPC8548)
/* E500 processors only support plain "sync", not lwsync. */
#define TARGET_NO_LWSYNC TARGET_E500
/* Which machine supports the various reciprocal estimate instructions. */
#define TARGET_FRES (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
&& TARGET_FPRS && TARGET_SINGLE_FLOAT)

2
gcc/config/rs6000/rs6000.md
View file

@ -165,7 +165,7 @@
;; Processor type -- this attribute must exactly match the processor_type
;; enumeration in rs6000.h.
(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan"
(define_attr "cpu" "rios1,rios2,rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,power4,power5,power6,power7,cell,ppca2,titan"
(const (symbol_ref "rs6000_cpu_attr")))

14
gcc/config/rs6000/rtems.h
View file

@ -55,17 +55,3 @@
#undef SUBSUBTARGET_EXTRA_SPECS
#define SUBSUBTARGET_EXTRA_SPECS \
{ "cpp_os_rtems", CPP_OS_RTEMS_SPEC }
#undef SUBSUBTARGET_OVERRIDE_OPTIONS
#define SUBSUBTARGET_OVERRIDE_OPTIONS \
do { \
if (TARGET_E500) \
{ \
if (TARGET_HARD_FLOAT && !global_options_set.x_rs6000_float_gprs) \
rs6000_float_gprs = 1; \
if (rs6000_float_gprs != 0 && !global_options_set.x_rs6000_spe) \
rs6000_spe = 1; \
if (rs6000_spe && !global_options_set.x_rs6000_spe_abi) \
rs6000_spe_abi = 1; \
} \
} while(0)

11
gcc/config/rs6000/vxworks.h
View file

@ -122,19 +122,8 @@ VXWORKS_ADDITIONAL_CPP_SPEC
#undef ABI_STACK_BOUNDARY
/* Make -mcpu=8540 imply SPE. ISEL is automatically enabled, the
others must be done by hand. Handle -mrtp. Disable -fPIC
for -mrtp - the VxWorks PIC model is not compatible with it. */
#undef SUBSUBTARGET_OVERRIDE_OPTIONS
#define SUBSUBTARGET_OVERRIDE_OPTIONS \
do { \
if (TARGET_E500) \
{ \
rs6000_spe = 1; \
rs6000_spe_abi = 1; \
rs6000_float_gprs = 1; \
} \
\
if (!global_options_set.x_g_switch_value) \
g_switch_value = SDATA_DEFAULT_SIZE; \
VXWORKS_OVERRIDE_OPTIONS; \