LoongArch:Implement avg and sad standard names.
gcc/ChangeLog: * config/loongarch/lasx.md (avg<mode>3_ceil): New patterns. (uavg<mode>3_ceil): Ditto. (avg<mode>3_floor): Ditto. (uavg<mode>3_floor): Ditto. (usadv32qi): Ditto. (ssadv32qi): Ditto. * config/loongarch/lsx.md (avg<mode>3_ceil): New patterns. (uavg<mode>3_ceil): Ditto. (avg<mode>3_floor): Ditto. (uavg<mode>3_floor): Ditto. (usadv16qi): Ditto. (ssadv16qi): Ditto. gcc/testsuite/ChangeLog: * gcc.target/loongarch/avg-ceil-lasx.c: New test. * gcc.target/loongarch/avg-ceil-lsx.c: New test. * gcc.target/loongarch/avg-floor-lasx.c: New test. * gcc.target/loongarch/avg-floor-lsx.c: New test. * gcc.target/loongarch/sad-lasx.c: New test. * gcc.target/loongarch/sad-lsx.c: New test.
This commit is contained in:
Jiahao Xu
Lulu Cheng
parent
0308461d9d
commit
a7b7284fe1
8 changed files with 284 additions and 0 deletions
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@ -5171,3 +5171,81 @@
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const0_rtx));
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DONE;
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})
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(define_expand "avg<mode>3_ceil"
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[(match_operand:ILASX_WHB 0 "register_operand")
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(match_operand:ILASX_WHB 1 "register_operand")
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(match_operand:ILASX_WHB 2 "register_operand")]
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"ISA_HAS_LASX"
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{
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emit_insn (gen_lasx_xvavgr_s_<lasxfmt> (operands[0],
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operands[1], operands[2]));
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DONE;
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})
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(define_expand "uavg<mode>3_ceil"
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[(match_operand:ILASX_WHB 0 "register_operand")
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(match_operand:ILASX_WHB 1 "register_operand")
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(match_operand:ILASX_WHB 2 "register_operand")]
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"ISA_HAS_LASX"
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{
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emit_insn (gen_lasx_xvavgr_u_<lasxfmt_u> (operands[0],
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operands[1], operands[2]));
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DONE;
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})
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(define_expand "avg<mode>3_floor"
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[(match_operand:ILASX_WHB 0 "register_operand")
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(match_operand:ILASX_WHB 1 "register_operand")
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(match_operand:ILASX_WHB 2 "register_operand")]
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"ISA_HAS_LASX"
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{
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emit_insn (gen_lasx_xvavg_s_<lasxfmt> (operands[0],
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operands[1], operands[2]));
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DONE;
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})
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(define_expand "uavg<mode>3_floor"
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[(match_operand:ILASX_WHB 0 "register_operand")
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(match_operand:ILASX_WHB 1 "register_operand")
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(match_operand:ILASX_WHB 2 "register_operand")]
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"ISA_HAS_LASX"
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{
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emit_insn (gen_lasx_xvavg_u_<lasxfmt_u> (operands[0],
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operands[1], operands[2]));
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DONE;
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})
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(define_expand "usadv32qi"
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[(match_operand:V8SI 0 "register_operand")
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(match_operand:V32QI 1 "register_operand")
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(match_operand:V32QI 2 "register_operand")
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(match_operand:V8SI 3 "register_operand")]
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"ISA_HAS_LASX"
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{
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rtx t1 = gen_reg_rtx (V32QImode);
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rtx t2 = gen_reg_rtx (V16HImode);
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rtx t3 = gen_reg_rtx (V8SImode);
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emit_insn (gen_lasx_xvabsd_u_bu (t1, operands[1], operands[2]));
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emit_insn (gen_lasx_xvhaddw_h_b (t2, t1, t1));
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emit_insn (gen_lasx_xvhaddw_w_h (t3, t2, t2));
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emit_insn (gen_addv8si3 (operands[0], t3, operands[3]));
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DONE;
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})
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(define_expand "ssadv32qi"
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[(match_operand:V8SI 0 "register_operand")
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(match_operand:V32QI 1 "register_operand")
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(match_operand:V32QI 2 "register_operand")
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(match_operand:V8SI 3 "register_operand")]
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"ISA_HAS_LASX"
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{
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rtx t1 = gen_reg_rtx (V32QImode);
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rtx t2 = gen_reg_rtx (V16HImode);
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rtx t3 = gen_reg_rtx (V8SImode);
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emit_insn (gen_lasx_xvabsd_s_b (t1, operands[1], operands[2]));
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emit_insn (gen_lasx_xvhaddw_h_b (t2, t1, t1));
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emit_insn (gen_lasx_xvhaddw_w_h (t3, t2, t2));
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emit_insn (gen_addv8si3 (operands[0], t3, operands[3]));
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DONE;
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})
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@ -3581,6 +3581,84 @@
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DONE;
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})
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(define_expand "avg<mode>3_ceil"
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[(match_operand:ILSX_WHB 0 "register_operand")
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(match_operand:ILSX_WHB 1 "register_operand")
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(match_operand:ILSX_WHB 2 "register_operand")]
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"ISA_HAS_LSX"
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{
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emit_insn (gen_lsx_vavgr_s_<lsxfmt> (operands[0],
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operands[1], operands[2]));
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DONE;
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})
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(define_expand "uavg<mode>3_ceil"
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[(match_operand:ILSX_WHB 0 "register_operand")
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(match_operand:ILSX_WHB 1 "register_operand")
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(match_operand:ILSX_WHB 2 "register_operand")]
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"ISA_HAS_LSX"
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{
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emit_insn (gen_lsx_vavgr_u_<lsxfmt_u> (operands[0],
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operands[1], operands[2]));
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DONE;
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})
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(define_expand "avg<mode>3_floor"
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[(match_operand:ILSX_WHB 0 "register_operand")
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(match_operand:ILSX_WHB 1 "register_operand")
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(match_operand:ILSX_WHB 2 "register_operand")]
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"ISA_HAS_LSX"
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{
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emit_insn (gen_lsx_vavg_s_<lsxfmt> (operands[0],
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operands[1], operands[2]));
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DONE;
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})
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(define_expand "uavg<mode>3_floor"
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[(match_operand:ILSX_WHB 0 "register_operand")
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(match_operand:ILSX_WHB 1 "register_operand")
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(match_operand:ILSX_WHB 2 "register_operand")]
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"ISA_HAS_LSX"
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{
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emit_insn (gen_lsx_vavg_u_<lsxfmt_u> (operands[0],
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operands[1], operands[2]));
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DONE;
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})
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(define_expand "usadv16qi"
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[(match_operand:V4SI 0 "register_operand")
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(match_operand:V16QI 1 "register_operand")
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(match_operand:V16QI 2 "register_operand")
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(match_operand:V4SI 3 "register_operand")]
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"ISA_HAS_LSX"
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{
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rtx t1 = gen_reg_rtx (V16QImode);
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rtx t2 = gen_reg_rtx (V8HImode);
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rtx t3 = gen_reg_rtx (V4SImode);
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emit_insn (gen_lsx_vabsd_u_bu (t1, operands[1], operands[2]));
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emit_insn (gen_lsx_vhaddw_h_b (t2, t1, t1));
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emit_insn (gen_lsx_vhaddw_w_h (t3, t2, t2));
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emit_insn (gen_addv4si3 (operands[0], t3, operands[3]));
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DONE;
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})
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(define_expand "ssadv16qi"
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[(match_operand:V4SI 0 "register_operand")
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(match_operand:V16QI 1 "register_operand")
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(match_operand:V16QI 2 "register_operand")
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(match_operand:V4SI 3 "register_operand")]
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"ISA_HAS_LSX"
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{
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rtx t1 = gen_reg_rtx (V16QImode);
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rtx t2 = gen_reg_rtx (V8HImode);
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rtx t3 = gen_reg_rtx (V4SImode);
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emit_insn (gen_lsx_vabsd_s_b (t1, operands[1], operands[2]));
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emit_insn (gen_lsx_vhaddw_h_b (t2, t1, t1));
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emit_insn (gen_lsx_vhaddw_w_h (t3, t2, t2));
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emit_insn (gen_addv4si3 (operands[0], t3, operands[3]));
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DONE;
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})
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(define_insn "lsx_v<optab>wev_d_w<u>"
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[(set (match_operand:V2DI 0 "register_operand" "=f")
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(addsubmul:V2DI
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22
gcc/testsuite/gcc.target/loongarch/avg-ceil-lasx.c
Normal file
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gcc/testsuite/gcc.target/loongarch/avg-ceil-lasx.c
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@ -0,0 +1,22 @@
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/* { dg-do compile } */
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/* { dg-options "-O3 -mlasx" } */
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/* { dg-final { scan-assembler "xvavgr.b" } } */
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/* { dg-final { scan-assembler "xvavgr.bu" } } */
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/* { dg-final { scan-assembler "xvavgr.hu" } } */
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/* { dg-final { scan-assembler "xvavgr.h" } } */
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#define N 1024
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#define TEST(TYPE, NAME) \
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TYPE a_##NAME[N], b_##NAME[N], c_##NAME[N]; \
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void f_##NAME (void) \
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{ \
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int i; \
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for (i = 0; i < N; i++) \
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a_##NAME[i] = (b_##NAME[i] + c_##NAME[i] + 1) >> 1; \
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}
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TEST(char, 1);
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TEST(short, 2);
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TEST(unsigned char, 3);
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TEST(unsigned short, 4);
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22
gcc/testsuite/gcc.target/loongarch/avg-ceil-lsx.c
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gcc/testsuite/gcc.target/loongarch/avg-ceil-lsx.c
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@ -0,0 +1,22 @@
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/* { dg-do compile } */
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/* { dg-options "-O3 -mlsx" } */
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/* { dg-final { scan-assembler "vavgr.b" } } */
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/* { dg-final { scan-assembler "vavgr.bu" } } */
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/* { dg-final { scan-assembler "vavgr.hu" } } */
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/* { dg-final { scan-assembler "vavgr.h" } } */
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#define N 1024
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#define TEST(TYPE, NAME) \
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TYPE a_##NAME[N], b_##NAME[N], c_##NAME[N]; \
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void f_##NAME (void) \
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{ \
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int i; \
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for (i = 0; i < N; i++) \
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a_##NAME[i] = (b_##NAME[i] + c_##NAME[i] + 1) >> 1; \
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}
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TEST(char, 1);
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TEST(short, 2);
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TEST(unsigned char, 3);
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TEST(unsigned short, 4);
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22
gcc/testsuite/gcc.target/loongarch/avg-floor-lasx.c
Normal file
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gcc/testsuite/gcc.target/loongarch/avg-floor-lasx.c
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@ -0,0 +1,22 @@
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/* { dg-do compile } */
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/* { dg-options "-O3 -mlasx" } */
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/* { dg-final { scan-assembler "xvavg.b" } } */
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/* { dg-final { scan-assembler "xvavg.bu" } } */
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/* { dg-final { scan-assembler "xvavg.hu" } } */
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/* { dg-final { scan-assembler "xvavg.h" } } */
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#define N 1024
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#define TEST(TYPE, NAME) \
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TYPE a_##NAME[N], b_##NAME[N], c_##NAME[N]; \
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void f_##NAME (void) \
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{ \
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int i; \
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for (i = 0; i < N; i++) \
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a_##NAME[i] = (b_##NAME[i] + c_##NAME[i]) >> 1; \
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}
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TEST(char, 1);
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TEST(short, 2);
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TEST(unsigned char, 3);
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TEST(unsigned short, 4);
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22
gcc/testsuite/gcc.target/loongarch/avg-floor-lsx.c
Normal file
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gcc/testsuite/gcc.target/loongarch/avg-floor-lsx.c
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@ -0,0 +1,22 @@
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/* { dg-do compile } */
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/* { dg-options "-O3 -mlsx" } */
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/* { dg-final { scan-assembler "vavg.b" } } */
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/* { dg-final { scan-assembler "vavg.bu" } } */
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/* { dg-final { scan-assembler "vavg.hu" } } */
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/* { dg-final { scan-assembler "vavg.h" } } */
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#define N 1024
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#define TEST(TYPE, NAME) \
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TYPE a_##NAME[N], b_##NAME[N], c_##NAME[N]; \
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void f_##NAME (void) \
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{ \
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int i; \
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for (i = 0; i < N; i++) \
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a_##NAME[i] = (b_##NAME[i] + c_##NAME[i]) >> 1; \
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}
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TEST(char, 1);
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TEST(short, 2);
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TEST(unsigned char, 3);
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TEST(unsigned short, 4);
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20
gcc/testsuite/gcc.target/loongarch/sad-lasx.c
Normal file
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gcc/testsuite/gcc.target/loongarch/sad-lasx.c
Normal file
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@ -0,0 +1,20 @@
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/* { dg-do compile } */
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/* { dg-options "-O3 -mlasx" } */
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#define N 1024
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#define TEST(SIGN) \
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SIGN char a_##SIGN[N], b_##SIGN[N]; \
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int f_##SIGN (void) \
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{ \
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int i, sum = 0; \
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for (i = 0; i < N; i++) \
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sum += __builtin_abs (a_##SIGN[i] - b_##SIGN[i]);; \
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return sum; \
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}
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TEST(signed);
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TEST(unsigned);
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/* { dg-final { scan-assembler {\txvabsd.bu\t} } } */
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/* { dg-final { scan-assembler {\txvabsd.b\t} } } */
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20
gcc/testsuite/gcc.target/loongarch/sad-lsx.c
Normal file
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gcc/testsuite/gcc.target/loongarch/sad-lsx.c
Normal file
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/* { dg-do compile } */
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/* { dg-options "-O3 -mlsx" } */
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#define N 1024
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#define TEST(SIGN) \
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SIGN char a_##SIGN[N], b_##SIGN[N]; \
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int f_##SIGN (void) \
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{ \
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int i, sum = 0; \
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for (i = 0; i < N; i++) \
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sum += __builtin_abs (a_##SIGN[i] - b_##SIGN[i]);; \
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return sum; \
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}
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TEST(signed);
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TEST(unsigned);
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/* { dg-final { scan-assembler {\tvabsd.bu\t} } } */
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/* { dg-final { scan-assembler {\tvabsd.b\t} } } */
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