re PR target/19293 (avr-gcc crashes when using shifts with negative shift count)
PR target/19293 PR target/19329 * config/avr/avr.c (notice_update_cc): Only set condition code for ashrqi3 if shift count > 0. (out_shift_with_cnt): Handle shift count <= 0 as a no-op. (ashlqi3_out, ashlhi3_out, ashlsi3_out, ashrqi3_out, ashrhi3_out, ashrsi3_out, lshrqi3_out, lshrhi3_out, lshrsi3_out): Handle shift count <= 0 as a no-op, and shift count >= width by copying zero or sign bit to all bits of the result. * config/avr/avr.md (all shifts): Add alternatives for zero shift count, with attribute "length" set to 0 and "cc" set to "none". From-SVN: r94288
This commit is contained in:
Marek Michalkiewicz
Marek Michalkiewicz
parent
d487e3c10a
commit
a3cf59927a
3 changed files with 170 additions and 81 deletions
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@ -1,3 +1,17 @@
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2005-01-26 Marek Michalkiewicz <marekm@amelek.gda.pl>
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PR target/19293
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PR target/19329
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* config/avr/avr.c (notice_update_cc): Only set condition code for
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ashrqi3 if shift count > 0.
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(out_shift_with_cnt): Handle shift count <= 0 as a no-op.
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(ashlqi3_out, ashlhi3_out, ashlsi3_out, ashrqi3_out, ashrhi3_out,
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ashrsi3_out, lshrqi3_out, lshrhi3_out, lshrsi3_out): Handle shift
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count <= 0 as a no-op, and shift count >= width by copying zero
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or sign bit to all bits of the result.
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* config/avr/avr.md (all shifts): Add alternatives for zero shift
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count, with attribute "length" set to 0 and "cc" set to "none".
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2005-01-26 Aldy Hernandez <aldyh@redhat.com>
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* doc/invoke.texi: Document -mTLS.
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@ -1229,6 +1229,7 @@ notice_update_cc (rtx body ATTRIBUTE_UNUSED, rtx insn)
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rtx x = XEXP (src, 1);
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if (GET_CODE (x) == CONST_INT
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&& INTVAL (x) > 0
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&& INTVAL (x) != 6)
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{
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cc_status.value1 = SET_DEST (set);
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@ -2749,6 +2750,13 @@ out_shift_with_cnt (const char *template, rtx insn, rtx operands[],
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int count = INTVAL (operands[2]);
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int max_len = 10; /* If larger than this, always use a loop. */
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if (count <= 0)
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{
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if (len)
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*len = 0;
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return;
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}
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if (count < 8 && !scratch)
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use_zero_reg = 1;
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@ -2871,6 +2879,9 @@ ashlqi3_out (rtx insn, rtx operands[], int *len)
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switch (INTVAL (operands[2]))
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{
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default:
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if (INTVAL (operands[2]) < 8)
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break;
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*len = 1;
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return AS1 (clr,%0);
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@ -2967,6 +2978,14 @@ ashlhi3_out (rtx insn, rtx operands[], int *len)
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switch (INTVAL (operands[2]))
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{
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default:
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if (INTVAL (operands[2]) < 16)
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break;
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*len = 2;
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return (AS1 (clr,%B0) CR_TAB
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AS1 (clr,%A0));
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case 4:
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if (optimize_size && scratch)
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break; /* 5 */
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@ -3218,6 +3237,20 @@ ashlsi3_out (rtx insn, rtx operands[], int *len)
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switch (INTVAL (operands[2]))
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{
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default:
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if (INTVAL (operands[2]) < 32)
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break;
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if (AVR_ENHANCED)
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return *len = 3, (AS1 (clr,%D0) CR_TAB
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AS1 (clr,%C0) CR_TAB
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AS2 (movw,%A0,%C0));
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*len = 4;
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return (AS1 (clr,%D0) CR_TAB
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AS1 (clr,%C0) CR_TAB
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AS1 (clr,%B0) CR_TAB
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AS1 (clr,%A0));
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case 8:
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{
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int reg0 = true_regnum (operands[0]);
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@ -3356,6 +3389,11 @@ ashrqi3_out (rtx insn, rtx operands[], int *len)
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AS2 (bld,%0,0));
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default:
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if (INTVAL (operands[2]) < 8)
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break;
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/* fall through */
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case 7:
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*len = 2;
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return (AS1 (lsl,%0) CR_TAB
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@ -3519,6 +3557,12 @@ ashrhi3_out (rtx insn, rtx operands[], int *len)
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AS2 (mov,%B0,%A0) CR_TAB
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AS1 (rol,%A0));
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default:
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if (INTVAL (operands[2]) < 16)
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break;
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/* fall through */
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case 15:
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return *len = 3, (AS1 (lsl,%B0) CR_TAB
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AS2 (sbc,%A0,%A0) CR_TAB
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@ -3626,6 +3670,12 @@ ashrsi3_out (rtx insn, rtx operands[], int *len)
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AS2 (mov,%B0,%D0) CR_TAB
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AS2 (mov,%C0,%D0));
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default:
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if (INTVAL (operands[2]) < 32)
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break;
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/* fall through */
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case 31:
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if (AVR_ENHANCED)
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return *len = 4, (AS1 (lsl,%D0) CR_TAB
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@ -3664,6 +3714,9 @@ lshrqi3_out (rtx insn, rtx operands[], int *len)
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switch (INTVAL (operands[2]))
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{
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default:
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if (INTVAL (operands[2]) < 8)
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break;
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*len = 1;
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return AS1 (clr,%0);
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@ -3758,6 +3811,14 @@ lshrhi3_out (rtx insn, rtx operands[], int *len)
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switch (INTVAL (operands[2]))
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{
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default:
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if (INTVAL (operands[2]) < 16)
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break;
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*len = 2;
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return (AS1 (clr,%B0) CR_TAB
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AS1 (clr,%A0));
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case 4:
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if (optimize_size && scratch)
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break; /* 5 */
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@ -4008,6 +4069,20 @@ lshrsi3_out (rtx insn, rtx operands[], int *len)
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switch (INTVAL (operands[2]))
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{
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default:
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if (INTVAL (operands[2]) < 32)
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break;
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if (AVR_ENHANCED)
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return *len = 3, (AS1 (clr,%D0) CR_TAB
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AS1 (clr,%C0) CR_TAB
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AS2 (movw,%A0,%C0));
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*len = 4;
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return (AS1 (clr,%D0) CR_TAB
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AS1 (clr,%C0) CR_TAB
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AS1 (clr,%B0) CR_TAB
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AS1 (clr,%A0));
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case 8:
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{
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int reg0 = true_regnum (operands[0]);
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@ -1167,31 +1167,31 @@
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;; arithmetic shift left
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(define_insn "ashlqi3"
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[(set (match_operand:QI 0 "register_operand" "=r,r,r,!d,r,r")
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(ashift:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
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(match_operand:QI 2 "general_operand" "r,P,K,n,n,Qm")))]
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[(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
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(ashift:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
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(match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
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""
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"* return ashlqi3_out (insn, operands, NULL);"
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[(set_attr "length" "5,1,2,4,6,9")
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(set_attr "cc" "clobber,set_czn,set_czn,set_czn,set_czn,clobber")])
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[(set_attr "length" "5,0,1,2,4,6,9")
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(set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
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(define_insn "ashlhi3"
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[(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
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(ashift:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0,0")
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(match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
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[(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
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(ashift:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
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(match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
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""
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"* return ashlhi3_out (insn, operands, NULL);"
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[(set_attr "length" "6,2,2,4,10,10")
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(set_attr "cc" "clobber,set_n,clobber,set_n,clobber,clobber")])
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[(set_attr "length" "6,0,2,2,4,10,10")
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(set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
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(define_insn "ashlsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
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(ashift:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0,0")
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(match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
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(ashift:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
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(match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
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""
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"* return ashlsi3_out (insn, operands, NULL);"
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[(set_attr "length" "8,4,4,8,10,12")
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(set_attr "cc" "clobber,set_n,clobber,set_n,clobber,clobber")])
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[(set_attr "length" "8,0,4,4,8,10,12")
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(set_attr "cc" "clobber,none,set_n,clobber,set_n,clobber,clobber")])
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;; Optimize if a scratch register from LD_REGS happens to be available.
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@ -1207,14 +1207,14 @@
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FAIL;")
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(define_insn "*ashlhi3_const"
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[(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
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(ashift:HI (match_operand:HI 1 "register_operand" "0,r,0,0")
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(match_operand:QI 2 "const_int_operand" "P,O,K,n")))
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(clobber (match_scratch:QI 3 "=X,X,X,&d"))]
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[(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
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(ashift:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
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(match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
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(clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
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"reload_completed"
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"* return ashlhi3_out (insn, operands, NULL);"
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[(set_attr "length" "2,2,4,10")
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(set_attr "cc" "set_n,clobber,set_n,clobber")])
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[(set_attr "length" "0,2,2,4,10")
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(set_attr "cc" "none,set_n,clobber,set_n,clobber")])
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(define_peephole2
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[(match_scratch:QI 3 "d")
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@ -1228,44 +1228,44 @@
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FAIL;")
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(define_insn "*ashlsi3_const"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r")
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(ashift:SI (match_operand:SI 1 "register_operand" "0,r,0")
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(match_operand:QI 2 "const_int_operand" "P,O,n")))
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(clobber (match_scratch:QI 3 "=X,X,&d"))]
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
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(ashift:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
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(match_operand:QI 2 "const_int_operand" "L,P,O,n")))
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(clobber (match_scratch:QI 3 "=X,X,X,&d"))]
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"reload_completed"
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"* return ashlsi3_out (insn, operands, NULL);"
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[(set_attr "length" "4,4,10")
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(set_attr "cc" "set_n,clobber,clobber")])
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[(set_attr "length" "0,4,4,10")
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(set_attr "cc" "none,set_n,clobber,clobber")])
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;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
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;; arithmetic shift right
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(define_insn "ashrqi3"
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[(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r")
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(ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0")
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(match_operand:QI 2 "general_operand" "r,P,K,n,Qm")))]
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[(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
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(ashiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
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(match_operand:QI 2 "general_operand" "r,L,P,K,n,Qm")))]
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""
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"* return ashrqi3_out (insn, operands, NULL);"
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[(set_attr "length" "5,1,2,5,9")
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(set_attr "cc" "clobber,clobber,clobber,clobber,clobber")])
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[(set_attr "length" "5,0,1,2,5,9")
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(set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber")])
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(define_insn "ashrhi3"
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[(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
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(ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0,0")
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(match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
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[(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
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(ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
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(match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
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""
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"* return ashrhi3_out (insn, operands, NULL);"
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[(set_attr "length" "6,2,4,4,10,10")
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(set_attr "cc" "clobber,clobber,set_n,clobber,clobber,clobber")])
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[(set_attr "length" "6,0,2,4,4,10,10")
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(set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
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(define_insn "ashrsi3"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
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(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0,0")
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(match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
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(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
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(match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
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""
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"* return ashrsi3_out (insn, operands, NULL);"
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[(set_attr "length" "8,4,6,8,10,12")
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(set_attr "cc" "clobber,clobber,set_n,clobber,clobber,clobber")])
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[(set_attr "length" "8,0,4,6,8,10,12")
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(set_attr "cc" "clobber,none,clobber,set_n,clobber,clobber,clobber")])
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;; Optimize if a scratch register from LD_REGS happens to be available.
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@ -1281,14 +1281,14 @@
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FAIL;")
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(define_insn "*ashrhi3_const"
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[(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
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(ashiftrt:HI (match_operand:HI 1 "register_operand" "0,r,0,0")
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(match_operand:QI 2 "const_int_operand" "P,O,K,n")))
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(clobber (match_scratch:QI 3 "=X,X,X,&d"))]
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[(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
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(ashiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
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(match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
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(clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
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"reload_completed"
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"* return ashrhi3_out (insn, operands, NULL);"
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[(set_attr "length" "2,4,4,10")
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(set_attr "cc" "clobber,set_n,clobber,clobber")])
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[(set_attr "length" "0,2,4,4,10")
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(set_attr "cc" "none,clobber,set_n,clobber,clobber")])
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(define_peephole2
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[(match_scratch:QI 3 "d")
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@ -1302,44 +1302,44 @@
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FAIL;")
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(define_insn "*ashrsi3_const"
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[(set (match_operand:SI 0 "register_operand" "=r,r,r")
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(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,r,0")
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(match_operand:QI 2 "const_int_operand" "P,O,n")))
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(clobber (match_scratch:QI 3 "=X,X,&d"))]
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[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
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(ashiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
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(match_operand:QI 2 "const_int_operand" "L,P,O,n")))
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||||
(clobber (match_scratch:QI 3 "=X,X,X,&d"))]
|
||||
"reload_completed"
|
||||
"* return ashrsi3_out (insn, operands, NULL);"
|
||||
[(set_attr "length" "4,4,10")
|
||||
(set_attr "cc" "clobber,set_n,clobber")])
|
||||
[(set_attr "length" "0,4,4,10")
|
||||
(set_attr "cc" "none,clobber,set_n,clobber")])
|
||||
|
||||
;; >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >> >>
|
||||
;; logical shift right
|
||||
|
||||
(define_insn "lshrqi3"
|
||||
[(set (match_operand:QI 0 "register_operand" "=r,r,r,!d,r,r")
|
||||
(lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0")
|
||||
(match_operand:QI 2 "general_operand" "r,P,K,n,n,Qm")))]
|
||||
[(set (match_operand:QI 0 "register_operand" "=r,r,r,r,!d,r,r")
|
||||
(lshiftrt:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,0,0")
|
||||
(match_operand:QI 2 "general_operand" "r,L,P,K,n,n,Qm")))]
|
||||
""
|
||||
"* return lshrqi3_out (insn, operands, NULL);"
|
||||
[(set_attr "length" "5,1,2,4,6,9")
|
||||
(set_attr "cc" "clobber,set_czn,set_czn,set_czn,set_czn,clobber")])
|
||||
[(set_attr "length" "5,0,1,2,4,6,9")
|
||||
(set_attr "cc" "clobber,none,set_czn,set_czn,set_czn,set_czn,clobber")])
|
||||
|
||||
(define_insn "lshrhi3"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
|
||||
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0,0")
|
||||
(match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
|
||||
[(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
|
||||
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,0,r,0,0,0")
|
||||
(match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
|
||||
""
|
||||
"* return lshrhi3_out (insn, operands, NULL);"
|
||||
[(set_attr "length" "6,2,2,4,10,10")
|
||||
(set_attr "cc" "clobber,clobber,clobber,clobber,clobber,clobber")])
|
||||
[(set_attr "length" "6,0,2,2,4,10,10")
|
||||
(set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
|
||||
|
||||
(define_insn "lshrsi3"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
|
||||
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0,0,0")
|
||||
(match_operand:QI 2 "general_operand" "r,P,O,K,n,Qm")))]
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r")
|
||||
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,0,r,0,0,0")
|
||||
(match_operand:QI 2 "general_operand" "r,L,P,O,K,n,Qm")))]
|
||||
""
|
||||
"* return lshrsi3_out (insn, operands, NULL);"
|
||||
[(set_attr "length" "8,4,4,8,10,12")
|
||||
(set_attr "cc" "clobber,clobber,clobber,clobber,clobber,clobber")])
|
||||
[(set_attr "length" "8,0,4,4,8,10,12")
|
||||
(set_attr "cc" "clobber,none,clobber,clobber,clobber,clobber,clobber")])
|
||||
|
||||
;; Optimize if a scratch register from LD_REGS happens to be available.
|
||||
|
||||
|
|
@ -1355,14 +1355,14 @@
|
|||
FAIL;")
|
||||
|
||||
(define_insn "*lshrhi3_const"
|
||||
[(set (match_operand:HI 0 "register_operand" "=r,r,r,r")
|
||||
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0,r,0,0")
|
||||
(match_operand:QI 2 "const_int_operand" "P,O,K,n")))
|
||||
(clobber (match_scratch:QI 3 "=X,X,X,&d"))]
|
||||
[(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r")
|
||||
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0,0,r,0,0")
|
||||
(match_operand:QI 2 "const_int_operand" "L,P,O,K,n")))
|
||||
(clobber (match_scratch:QI 3 "=X,X,X,X,&d"))]
|
||||
"reload_completed"
|
||||
"* return lshrhi3_out (insn, operands, NULL);"
|
||||
[(set_attr "length" "2,2,4,10")
|
||||
(set_attr "cc" "clobber,clobber,clobber,clobber")])
|
||||
[(set_attr "length" "0,2,2,4,10")
|
||||
(set_attr "cc" "none,clobber,clobber,clobber,clobber")])
|
||||
|
||||
(define_peephole2
|
||||
[(match_scratch:QI 3 "d")
|
||||
|
|
@ -1376,14 +1376,14 @@
|
|||
FAIL;")
|
||||
|
||||
(define_insn "*lshrsi3_const"
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r,r")
|
||||
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,r,0")
|
||||
(match_operand:QI 2 "const_int_operand" "P,O,n")))
|
||||
(clobber (match_scratch:QI 3 "=X,X,&d"))]
|
||||
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
|
||||
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0,0,r,0")
|
||||
(match_operand:QI 2 "const_int_operand" "L,P,O,n")))
|
||||
(clobber (match_scratch:QI 3 "=X,X,X,&d"))]
|
||||
"reload_completed"
|
||||
"* return lshrsi3_out (insn, operands, NULL);"
|
||||
[(set_attr "length" "4,4,10")
|
||||
(set_attr "cc" "clobber,clobber,clobber")])
|
||||
[(set_attr "length" "0,4,4,10")
|
||||
(set_attr "cc" "none,clobber,clobber,clobber")])
|
||||
|
||||
;; abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x) abs(x)
|
||||
;; abs
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue