libphobos: Push all callee-save registers on the stack before GC scan on ARM

This is the library fix for PR103520 that also prevents the garbage
collector from releasing live memory.  However this requires that the
host compiler has been patched with this fix, so the GC will remain
disabled in the D front-end for now until enough time has passed for
this to have trickled down into enough releases.

libphobos/ChangeLog:

	* libdruntime/core/thread/osthread.d (callWithStackShell): Push all
	callee-save registers on the stack for AArch64 and ARM.
This commit is contained in:
Iain Buclaw 2021-12-02 01:53:51 +01:00
parent 9b8830b6f3
commit a27940feff

View file

@ -1487,6 +1487,35 @@ in (fn)
}}
sp = cast(void*)&regs[0];
}
else version (AArch64)
{
// Callee-save registers, x19-x28 according to AAPCS64, section
// 5.1.1. Include x29 fp because it optionally can be a callee
// saved reg
size_t[11] regs = void;
// store the registers in pairs
asm pure nothrow @nogc
{
"stp x19, x20, %0" : "=m" (regs[ 0]), "=m" (regs[1]);
"stp x21, x22, %0" : "=m" (regs[ 2]), "=m" (regs[3]);
"stp x23, x24, %0" : "=m" (regs[ 4]), "=m" (regs[5]);
"stp x25, x26, %0" : "=m" (regs[ 6]), "=m" (regs[7]);
"stp x27, x28, %0" : "=m" (regs[ 8]), "=m" (regs[9]);
"str x29, %0" : "=m" (regs[10]);
"mov %0, sp" : "=r" (sp);
}
}
else version (ARM)
{
// Callee-save registers, according to AAPCS, section 5.1.1.
// arm and thumb2 instructions
size_t[8] regs = void;
asm pure nothrow @nogc
{
"stm %0, {r4-r11}" : : "r" (regs.ptr) : "memory";
"mov %0, sp" : "=r" (sp);
}
}
else
{
__builtin_unwind_init();