RISC-V: Keep vlmax vector operators in simple form until split1 pass
This patch keep vlmax vector pattern in simple before split1 pass which will allow more optimization (e.g. combine) before split1 pass. This patch changes the vlmax pattern in autovec.md to define_insn_and_split as much as possible and clean up some combine patterns that are no longer needed. This patch also fixed PR111232 bug which was caused by a combined failed. PR target/111232 gcc/ChangeLog: * config/riscv/autovec-opt.md (@pred_single_widen_mul<any_extend:su><mode>): Delete. (*pred_widen_mulsu<mode>): Delete. (*pred_single_widen_mul<mode>): Delete. (*dual_widen_<any_widen_binop:optab><any_extend:su><mode>): Add new combine patterns. (*single_widen_sub<any_extend:su><mode>): Ditto. (*single_widen_add<any_extend:su><mode>): Ditto. (*single_widen_mult<any_extend:su><mode>): Ditto. (*dual_widen_mulsu<mode>): Ditto. (*dual_widen_mulus<mode>): Ditto. (*dual_widen_<optab><mode>): Ditto. (*single_widen_add<mode>): Ditto. (*single_widen_sub<mode>): Ditto. (*single_widen_mult<mode>): Ditto. * config/riscv/autovec.md (<optab><mode>3): Change define_expand to define_insn_and_split. (<optab><mode>2): Ditto. (abs<mode>2): Ditto. (smul<mode>3_highpart): Ditto. (umul<mode>3_highpart): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/widen/widen-4.c: Add more testcases. * gcc.target/riscv/rvv/autovec/widen/widen-complicate-4.c: Ditto. * gcc.target/riscv/rvv/autovec/pr111232.c: New test.
This commit is contained in:
Lehua Ding
parent
4abcc5009c
commit
9ee40b9a7b
5 changed files with 276 additions and 136 deletions
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@ -18,67 +18,6 @@
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;; along with GCC; see the file COPYING3. If not see
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;; <http://www.gnu.org/licenses/>.
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;; We don't have vwmul.wv instruction like vwadd.wv in RVV.
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;; This pattern is an intermediate RTL IR as a pseudo vwmul.wv to enhance
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;; optimization of instructions combine.
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(define_insn_and_split "@pred_single_widen_mul<any_extend:su><mode>"
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[(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
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(if_then_else:VWEXTI
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(unspec:<VM>
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[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
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(match_operand 5 "vector_length_operand" " rK, rK")
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(match_operand 6 "const_int_operand" " i, i")
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(match_operand 7 "const_int_operand" " i, i")
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(match_operand 8 "const_int_operand" " i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(mult:VWEXTI
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(any_extend:VWEXTI
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(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr"))
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(match_operand:VWEXTI 3 "register_operand" " vr, vr"))
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(match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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insn_code icode = code_for_pred_vf2 (<CODE>, <MODE>mode);
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rtx tmp = gen_reg_rtx (<MODE>mode);
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rtx ops[] = {tmp, operands[4]};
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riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ops);
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emit_insn (gen_pred (MULT, <MODE>mode, operands[0], operands[1], operands[2],
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operands[3], tmp, operands[5], operands[6],
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operands[7], operands[8]));
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DONE;
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}
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[(set_attr "type" "viwmul")
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(set_attr "mode" "<MODE>")])
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;; This pattern it to enchance the instruction combine optimizations for complicate
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;; sign and unsigned widening multiplication operations.
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(define_insn "*pred_widen_mulsu<mode>"
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[(set (match_operand:VWEXTI 0 "register_operand" "=&vr,&vr")
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(if_then_else:VWEXTI
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(unspec:<VM>
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[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
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(match_operand 5 "vector_length_operand" " rK, rK")
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(match_operand 6 "const_int_operand" " i, i")
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(match_operand 7 "const_int_operand" " i, i")
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(match_operand 8 "const_int_operand" " i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
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(mult:VWEXTI
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(zero_extend:VWEXTI
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(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr"))
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(sign_extend:VWEXTI
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(match_operand:<V_DOUBLE_TRUNC> 3 "register_operand" " vr, vr")))
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(match_operand:VWEXTI 2 "vector_merge_operand" " vu, 0")))]
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"TARGET_VECTOR"
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"vwmulsu.vv\t%0,%3,%4%p1"
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[(set_attr "type" "viwmul")
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(set_attr "mode" "<V_DOUBLE_TRUNC>")])
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;; -----------------------------------------------------------------------------
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;; ---- Integer Compare Instructions Simplification
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;; -----------------------------------------------------------------------------
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@ -406,45 +345,6 @@
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[(set_attr "type" "vimovvx")
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(set_attr "mode" "<MODE>")])
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;; We don't have vfwmul.wv instruction like vfwadd.wv in RVV.
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;; This pattern is an intermediate RTL IR as a pseudo vfwmul.wv to enhance
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;; optimization of instructions combine.
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(define_insn_and_split "*pred_single_widen_mul<mode>"
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[(set (match_operand:VWEXTF 0 "register_operand" "=&vr, &vr")
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(if_then_else:VWEXTF
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(unspec:<VM>
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[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
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(match_operand 5 "vector_length_operand" " rK, rK")
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(match_operand 6 "const_int_operand" " i, i")
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(match_operand 7 "const_int_operand" " i, i")
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(match_operand 8 "const_int_operand" " i, i")
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(match_operand 9 "const_int_operand" " i, i")
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(reg:SI VL_REGNUM)
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(reg:SI VTYPE_REGNUM)
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(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
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(mult:VWEXTF
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(float_extend:VWEXTF
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(match_operand:<V_DOUBLE_TRUNC> 4 "register_operand" " vr, vr"))
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(match_operand:VWEXTF 3 "register_operand" " vr, vr"))
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(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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insn_code icode = code_for_pred_extend (<MODE>mode);
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rtx tmp = gen_reg_rtx (<MODE>mode);
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rtx ops[] = {tmp, operands[4]};
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riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, ops);
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emit_insn (gen_pred (MULT, <MODE>mode, operands[0], operands[1], operands[2],
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operands[3], tmp, operands[5], operands[6],
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operands[7], operands[8], operands[9]));
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DONE;
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}
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[(set_attr "type" "vfwmul")
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(set_attr "mode" "<MODE>")])
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;; -------------------------------------------------------------------------
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;; ---- [FP] VFWMACC
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;; -------------------------------------------------------------------------
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@ -845,7 +745,7 @@
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DONE;
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})
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;; Combine FP sign_extend/zero_extend(vf2) and vcond_mask
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;; Combine FP extend(vf2) and vcond_mask
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(define_insn_and_split "*cond_extend<v_double_trunc><mode>"
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[(set (match_operand:VWEXTF_ZVFHMIN 0 "register_operand")
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(if_then_else:VWEXTF_ZVFHMIN
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@ -1003,3 +903,195 @@
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riscv_vector::expand_cond_len_unop (icode, ops);
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DONE;
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})
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;; =============================================================================
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;; Combine extend + binop to widen_binop
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;; =============================================================================
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(define_insn_and_split "*dual_widen_<any_widen_binop:optab><any_extend:su><mode>"
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[(set (match_operand:VWEXTI 0 "register_operand")
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(any_widen_binop:VWEXTI
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(any_extend:VWEXTI
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(match_operand:<V_DOUBLE_TRUNC> 1 "register_operand"))
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(any_extend:VWEXTI
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(match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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insn_code icode = code_for_pred_dual_widen (<any_widen_binop:CODE>,
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<any_extend:CODE>,
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<MODE>mode);
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riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
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DONE;
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})
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(define_insn_and_split "*single_widen_sub<any_extend:su><mode>"
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[(set (match_operand:VWEXTI 0 "register_operand")
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(minus:VWEXTI
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(match_operand:VWEXTI 1 "register_operand")
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(any_extend:VWEXTI
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(match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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insn_code icode = code_for_pred_single_widen_sub (<any_extend:CODE>,
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<MODE>mode);
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riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
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DONE;
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})
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(define_insn_and_split "*single_widen_add<any_extend:su><mode>"
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[(set (match_operand:VWEXTI 0 "register_operand")
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(plus:VWEXTI
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(any_extend:VWEXTI
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(match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
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(match_operand:VWEXTI 1 "register_operand")))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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insn_code icode = code_for_pred_single_widen_add (<any_extend:CODE>,
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<MODE>mode);
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riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
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DONE;
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})
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;; This combine pattern does not correspond to an single instruction,
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;; i.e. there is no vwmul.wv instruction. This is a temporary pattern
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;; produced by a combine pass and if there is no further combine into
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;; vwmul.vv pattern, then fall back to extend pattern and vmul.vv pattern.
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(define_insn_and_split "*single_widen_mult<any_extend:su><mode>"
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[(set (match_operand:VWEXTI 0 "register_operand")
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(mult:VWEXTI
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(any_extend:VWEXTI
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(match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
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(match_operand:VWEXTI 1 "register_operand")))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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insn_code extend_icode = code_for_pred_vf2 (<any_extend:CODE>, <MODE>mode);
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rtx tmp = gen_reg_rtx (<MODE>mode);
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rtx extend_ops[] = {tmp, operands[2]};
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riscv_vector::emit_vlmax_insn (extend_icode, riscv_vector::UNARY_OP, extend_ops);
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rtx ops[] = {operands[0], operands[1], tmp};
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insn_code icode = code_for_pred (MULT, <MODE>mode);
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riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, ops);
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DONE;
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})
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(define_insn_and_split "*dual_widen_mulsu<mode>"
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[(set (match_operand:VWEXTI 0 "register_operand")
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(mult:VWEXTI
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(sign_extend:VWEXTI
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(match_operand:<V_DOUBLE_TRUNC> 1 "register_operand"))
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(zero_extend:VWEXTI
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(match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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insn_code icode = code_for_pred_widen_mulsu (<MODE>mode);
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riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
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DONE;
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})
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(define_insn_and_split "*dual_widen_mulus<mode>"
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[(set (match_operand:VWEXTI 0 "register_operand")
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(mult:VWEXTI
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(zero_extend:VWEXTI
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(match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
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(sign_extend:VWEXTI
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(match_operand:<V_DOUBLE_TRUNC> 1 "register_operand"))))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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insn_code icode = code_for_pred_widen_mulsu (<MODE>mode);
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riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
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DONE;
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})
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(define_insn_and_split "*dual_widen_<optab><mode>"
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[(set (match_operand:VWEXTF 0 "register_operand")
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(any_widen_binop:VWEXTF
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(float_extend:VWEXTF
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(match_operand:<V_DOUBLE_TRUNC> 1 "register_operand"))
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(float_extend:VWEXTF
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(match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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insn_code icode = code_for_pred_dual_widen (<CODE>, <MODE>mode);
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riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP_FRM_DYN, operands);
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DONE;
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})
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(define_insn_and_split "*single_widen_add<mode>"
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[(set (match_operand:VWEXTF 0 "register_operand")
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(plus:VWEXTF
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(float_extend:VWEXTF
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(match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
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(match_operand:VWEXTF 1 "register_operand")))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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insn_code icode = code_for_pred_single_widen_add (<MODE>mode);
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riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP_FRM_DYN, operands);
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DONE;
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})
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(define_insn_and_split "*single_widen_sub<mode>"
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[(set (match_operand:VWEXTF 0 "register_operand")
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(minus:VWEXTF
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(match_operand:VWEXTF 1 "register_operand")
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(float_extend:VWEXTF
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(match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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insn_code icode = code_for_pred_single_widen_sub (<MODE>mode);
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riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP_FRM_DYN, operands);
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DONE;
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})
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;; This combine pattern does not correspond to an single instruction,
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;; i.e. there is no vfwmul.wv instruction. This is a temporary pattern
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;; produced by a combine pass and if there is no further combine into
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;; vfwmul.vv pattern, then fall back to extend pattern and vfmul.vv pattern.
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(define_insn_and_split "*single_widen_mult<mode>"
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[(set (match_operand:VWEXTF 0 "register_operand")
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(mult:VWEXTF
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(float_extend:VWEXTF
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(match_operand:<V_DOUBLE_TRUNC> 2 "register_operand"))
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(match_operand:VWEXTF 1 "register_operand")))]
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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insn_code extend_icode = code_for_pred_extend (<MODE>mode);
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rtx tmp = gen_reg_rtx (<MODE>mode);
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rtx extend_ops[] = {tmp, operands[2]};
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riscv_vector::emit_vlmax_insn (extend_icode, riscv_vector::UNARY_OP, extend_ops);
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rtx ops[] = {operands[0], operands[1], tmp};
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riscv_vector::emit_vlmax_insn (code_for_pred (MULT, <MODE>mode),
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riscv_vector::BINARY_OP_FRM_DYN, ops);
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DONE;
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})
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@ -419,12 +419,15 @@
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;; - vadd.vi/vsub.vi/...
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;; -------------------------------------------------------------------------
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(define_expand "<optab><mode>3"
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(define_insn_and_split "<optab><mode>3"
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[(set (match_operand:VI 0 "register_operand")
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(any_int_binop_no_shift:VI
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(match_operand:VI 1 "<binop_rhs1_predicate>")
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(match_operand:VI 2 "<binop_rhs2_predicate>")))]
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"TARGET_VECTOR"
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
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riscv_vector::BINARY_OP, operands);
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@ -937,11 +940,14 @@
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;; Includes:
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;; - vneg.v/vnot.v
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;; -------------------------------------------------------------------------------
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(define_expand "<optab><mode>2"
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(define_insn_and_split "<optab><mode>2"
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[(set (match_operand:VI 0 "register_operand")
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(any_int_unop:VI
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(match_operand:VI 1 "register_operand")))]
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"TARGET_VECTOR"
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"TARGET_VECTOR && can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
|
||||
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
|
||||
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
|
||||
|
|
@ -952,10 +958,14 @@
|
|||
;; - [INT] ABS expansion to vmslt and vneg.
|
||||
;; -------------------------------------------------------------------------------
|
||||
|
||||
(define_expand "abs<mode>2"
|
||||
(define_insn_and_split "abs<mode>2"
|
||||
[(set (match_operand:VI 0 "register_operand")
|
||||
(match_operand:VI 1 "register_operand"))]
|
||||
"TARGET_VECTOR"
|
||||
(abs:VI
|
||||
(match_operand:VI 1 "register_operand")))]
|
||||
"TARGET_VECTOR && can_create_pseudo_p ()"
|
||||
"#"
|
||||
"&& 1"
|
||||
[(const_int 0)]
|
||||
{
|
||||
rtx zero = gen_const_vec_duplicate (<MODE>mode, GEN_INT (0));
|
||||
machine_mode mask_mode = riscv_vector::get_mask_mode (<MODE>mode);
|
||||
|
|
@ -1457,12 +1467,15 @@
|
|||
;; - vfadd.vv/vfsub.vv/...
|
||||
;; - vfadd.vf/vfsub.vf/...
|
||||
;; -------------------------------------------------------------------------
|
||||
(define_expand "<optab><mode>3"
|
||||
[(match_operand:VF 0 "register_operand")
|
||||
(any_float_binop:VF
|
||||
(match_operand:VF 1 "register_operand")
|
||||
(match_operand:VF 2 "register_operand"))]
|
||||
"TARGET_VECTOR"
|
||||
(define_insn_and_split "<optab><mode>3"
|
||||
[(set (match_operand:VF 0 "register_operand")
|
||||
(any_float_binop:VF
|
||||
(match_operand:VF 1 "register_operand")
|
||||
(match_operand:VF 2 "register_operand")))]
|
||||
"TARGET_VECTOR && can_create_pseudo_p ()"
|
||||
"#"
|
||||
"&& 1"
|
||||
[(const_int 0)]
|
||||
{
|
||||
riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
|
||||
riscv_vector::BINARY_OP_FRM_DYN, operands);
|
||||
|
|
@ -1474,12 +1487,15 @@
|
|||
;; - vfmin.vv/vfmax.vv
|
||||
;; - vfmin.vf/vfmax.vf
|
||||
;; -------------------------------------------------------------------------
|
||||
(define_expand "<optab><mode>3"
|
||||
[(match_operand:VF 0 "register_operand")
|
||||
(any_float_binop_nofrm:VF
|
||||
(match_operand:VF 1 "register_operand")
|
||||
(match_operand:VF 2 "register_operand"))]
|
||||
"TARGET_VECTOR"
|
||||
(define_insn_and_split "<optab><mode>3"
|
||||
[(set (match_operand:VF 0 "register_operand")
|
||||
(any_float_binop_nofrm:VF
|
||||
(match_operand:VF 1 "register_operand")
|
||||
(match_operand:VF 2 "register_operand")))]
|
||||
"TARGET_VECTOR && can_create_pseudo_p ()"
|
||||
"#"
|
||||
"&& 1"
|
||||
[(const_int 0)]
|
||||
{
|
||||
riscv_vector::emit_vlmax_insn (code_for_pred (<CODE>, <MODE>mode),
|
||||
riscv_vector::BINARY_OP, operands);
|
||||
|
|
@ -1537,22 +1553,30 @@
|
|||
;; - vmulhu.vv
|
||||
;; -------------------------------------------------------------------------
|
||||
|
||||
(define_expand "smul<mode>3_highpart"
|
||||
[(match_operand:VFULLI 0 "register_operand")
|
||||
(match_operand:VFULLI 1 "register_operand")
|
||||
(match_operand:VFULLI 2 "register_operand")]
|
||||
"TARGET_VECTOR"
|
||||
(define_insn_and_split "smul<mode>3_highpart"
|
||||
[(set (match_operand:VFULLI 0 "register_operand")
|
||||
(smul_highpart:VFULLI
|
||||
(match_operand:VFULLI 1 "register_operand")
|
||||
(match_operand:VFULLI 2 "register_operand")))]
|
||||
"TARGET_VECTOR && can_create_pseudo_p ()"
|
||||
"#"
|
||||
"&& 1"
|
||||
[(const_int 0)]
|
||||
{
|
||||
insn_code icode = code_for_pred_mulh (UNSPEC_VMULHS, <MODE>mode);
|
||||
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
|
||||
DONE;
|
||||
})
|
||||
|
||||
(define_expand "umul<mode>3_highpart"
|
||||
[(match_operand:VFULLI 0 "register_operand")
|
||||
(match_operand:VFULLI 1 "register_operand")
|
||||
(match_operand:VFULLI 2 "register_operand")]
|
||||
"TARGET_VECTOR"
|
||||
(define_insn_and_split "umul<mode>3_highpart"
|
||||
[(set (match_operand:VFULLI 0 "register_operand")
|
||||
(umul_highpart:VFULLI
|
||||
(match_operand:VFULLI 1 "register_operand")
|
||||
(match_operand:VFULLI 2 "register_operand")))]
|
||||
"TARGET_VECTOR && can_create_pseudo_p ()"
|
||||
"#"
|
||||
"&& 1"
|
||||
[(const_int 0)]
|
||||
{
|
||||
insn_code icode = code_for_pred_mulh (UNSPEC_VMULHU, <MODE>mode);
|
||||
riscv_vector::emit_vlmax_insn (icode, riscv_vector::BINARY_OP, operands);
|
||||
|
|
|
|||
18
gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c
Normal file
18
gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111232.c
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-autovec-preference=scalable -Ofast -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
int16_t
|
||||
foo (int8_t *restrict x, int8_t *restrict y, int n)
|
||||
{
|
||||
int16_t result = 0;
|
||||
|
||||
for (int i = 0; i < n; i++)
|
||||
{
|
||||
result += (x[i] * y[i]);
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler {\tvwmacc\.vv\tv[0-9]+,v[0-9]+,v[0-9]+} } } */
|
||||
|
|
@ -16,8 +16,11 @@
|
|||
#define TEST_ALL() \
|
||||
TEST_TYPE (int16_t, int8_t, uint8_t) \
|
||||
TEST_TYPE (int32_t, int16_t, uint16_t) \
|
||||
TEST_TYPE (int64_t, int32_t, uint32_t)
|
||||
TEST_TYPE (int64_t, int32_t, uint32_t) \
|
||||
TEST_TYPE (int16_t, uint8_t, int8_t) \
|
||||
TEST_TYPE (int32_t, uint16_t, int16_t) \
|
||||
TEST_TYPE (int64_t, uint32_t, int32_t)
|
||||
|
||||
TEST_ALL ()
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tvwmulsu\.vv} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tvwmulsu\.vv} 6 } } */
|
||||
|
|
|
|||
|
|
@ -21,11 +21,14 @@
|
|||
#define TEST_ALL() \
|
||||
TEST_TYPE (int16_t, int8_t, uint8_t) \
|
||||
TEST_TYPE (int32_t, int16_t, uint16_t) \
|
||||
TEST_TYPE (int64_t, int32_t, uint32_t)
|
||||
TEST_TYPE (int64_t, int32_t, uint32_t) \
|
||||
TEST_TYPE (int16_t, uint8_t, int8_t) \
|
||||
TEST_TYPE (int32_t, uint16_t, int16_t) \
|
||||
TEST_TYPE (int64_t, uint32_t, int32_t)
|
||||
|
||||
TEST_ALL ()
|
||||
|
||||
/* { dg-final { scan-assembler-times {\tvwmulsu\.vv} 6 } } */
|
||||
/* { dg-final { scan-assembler-times {\tvwmul\.vv} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 3 } } */
|
||||
/* { dg-final { scan-assembler-times {\tvwmulsu\.vv} 12 } } */
|
||||
/* { dg-final { scan-assembler-times {\tvwmul\.vv} 6 } } */
|
||||
/* { dg-final { scan-assembler-times {\tvwmulu\.vv} 6 } } */
|
||||
/* { dg-final { scan-assembler-not {\tvmul} } } */
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue