Move some external functions used by machine description patterns to nds32-md-auxiliary.c module.
gcc/ * config/nds32/nds32.c (nds32_byte_to_size): Move to ... (nds32_output_casesi_pc_relative): Move to ... (nds32_output_casesi): Move to ... (nds32_mem_format): Move to ... (nds32_output_16bit_store): Move to ... (nds32_output_16bit_load): Move to ... (nds32_output_32bit_store): Move to ... (nds32_output_32bit_load): Move to ... (nds32_output_32bit_load_s): Move to ... (nds32_output_stack_push): Move to ... (nds32_output_stack_pop): Move to ... * config/nds32/nds32-md-auxiliary.c: ... here. Co-Authored-By: Kito Cheng <kito@0xlab.org> Co-Authored-By: Monk Chiang <sh.chiang04@gmail.com> From-SVN: r212286
This commit is contained in:
Chung-Ju Wu
Chung-Ju Wu
parent
c65cef1051
commit
9e9dbc429c
3 changed files with 832 additions and 779 deletions
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@ -1,3 +1,20 @@
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2014-07-04 Chung-Ju Wu <jasonwucj@gmail.com>
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Kito Cheng <kito@0xlab.org>
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Monk Chiang <sh.chiang04@gmail.com>
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* config/nds32/nds32.c (nds32_byte_to_size): Move to ...
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(nds32_output_casesi_pc_relative): Move to ...
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(nds32_output_casesi): Move to ...
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(nds32_mem_format): Move to ...
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(nds32_output_16bit_store): Move to ...
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(nds32_output_16bit_load): Move to ...
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(nds32_output_32bit_store): Move to ...
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(nds32_output_32bit_load): Move to ...
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(nds32_output_32bit_load_s): Move to ...
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(nds32_output_stack_push): Move to ...
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(nds32_output_stack_pop): Move to ...
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* config/nds32/nds32-md-auxiliary.c: ... here.
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2014-07-04 Chung-Ju Wu <jasonwucj@gmail.com>
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Ling-Hua Tseng <uranus@tinlans.org>
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@ -18,3 +18,818 @@
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You should have received a copy of the GNU General Public License
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along with GCC; see the file COPYING3. If not see
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<http://www.gnu.org/licenses/>. */
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/* ------------------------------------------------------------------------ */
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#include "config.h"
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#include "system.h"
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#include "coretypes.h"
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#include "tm.h"
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#include "tree.h"
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#include "stor-layout.h"
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#include "varasm.h"
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#include "calls.h"
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#include "rtl.h"
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#include "regs.h"
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#include "hard-reg-set.h"
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#include "insn-config.h" /* Required by recog.h. */
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#include "conditions.h"
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#include "output.h"
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#include "insn-attr.h" /* For DFA state_t. */
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#include "insn-codes.h" /* For CODE_FOR_xxx. */
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#include "reload.h" /* For push_reload(). */
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#include "flags.h"
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#include "function.h"
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#include "expr.h"
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#include "recog.h"
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#include "diagnostic-core.h"
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#include "df.h"
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#include "tm_p.h"
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#include "tm-constrs.h"
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#include "optabs.h" /* For GEN_FCN. */
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#include "target.h"
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#include "target-def.h"
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#include "langhooks.h" /* For add_builtin_function(). */
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#include "ggc.h"
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#include "builtins.h"
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/* ------------------------------------------------------------------------ */
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/* A helper function to return character based on byte size. */
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static char
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nds32_byte_to_size (int byte)
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{
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switch (byte)
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{
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case 4:
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return 'w';
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case 2:
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return 'h';
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case 1:
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return 'b';
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default:
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/* Normally it should not be here. */
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gcc_unreachable ();
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}
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}
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/* A helper function to return memory format. */
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enum nds32_16bit_address_type
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nds32_mem_format (rtx op)
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{
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enum machine_mode mode_test;
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int val;
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int regno;
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if (!TARGET_16_BIT)
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return ADDRESS_NOT_16BIT_FORMAT;
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mode_test = GET_MODE (op);
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op = XEXP (op, 0);
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/* 45 format. */
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if (GET_CODE (op) == REG && (mode_test == SImode))
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return ADDRESS_REG;
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/* 333 format for QI/HImode. */
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if (GET_CODE (op) == REG && (REGNO (op) < R8_REGNUM))
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return ADDRESS_LO_REG_IMM3U;
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/* post_inc 333 format. */
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if ((GET_CODE (op) == POST_INC) && (mode_test == SImode))
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{
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regno = REGNO(XEXP (op, 0));
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if (regno < 8)
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return ADDRESS_POST_INC_LO_REG_IMM3U;
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}
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/* post_inc 333 format. */
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if ((GET_CODE (op) == POST_MODIFY)
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&& (mode_test == SImode)
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&& (REG_P (XEXP (XEXP (op, 1), 0)))
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&& (CONST_INT_P (XEXP (XEXP (op, 1), 1))))
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{
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regno = REGNO (XEXP (XEXP (op, 1), 0));
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val = INTVAL (XEXP (XEXP (op, 1), 1));
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if (regno < 8 && val < 32)
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return ADDRESS_POST_INC_LO_REG_IMM3U;
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}
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if ((GET_CODE (op) == PLUS)
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&& (GET_CODE (XEXP (op, 0)) == REG)
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&& (GET_CODE (XEXP (op, 1)) == CONST_INT))
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{
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val = INTVAL (XEXP (op, 1));
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regno = REGNO(XEXP (op, 0));
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if (regno > 7
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&& regno != SP_REGNUM
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&& regno != FP_REGNUM)
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return ADDRESS_NOT_16BIT_FORMAT;
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switch (mode_test)
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{
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case QImode:
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/* 333 format. */
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if (val >= 0 && val < 8 && regno < 8)
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return ADDRESS_LO_REG_IMM3U;
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break;
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case HImode:
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/* 333 format. */
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if (val >= 0 && val < 16 && (val % 2 == 0) && regno < 8)
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return ADDRESS_LO_REG_IMM3U;
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break;
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case SImode:
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case SFmode:
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case DFmode:
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/* fp imply 37 format. */
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if ((regno == FP_REGNUM) &&
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(val >= 0 && val < 512 && (val % 4 == 0)))
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return ADDRESS_FP_IMM7U;
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/* sp imply 37 format. */
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else if ((regno == SP_REGNUM) &&
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(val >= 0 && val < 512 && (val % 4 == 0)))
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return ADDRESS_SP_IMM7U;
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/* 333 format. */
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else if (val >= 0 && val < 32 && (val % 4 == 0) && regno < 8)
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return ADDRESS_LO_REG_IMM3U;
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break;
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default:
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break;
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}
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}
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return ADDRESS_NOT_16BIT_FORMAT;
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}
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/* Output 16-bit store. */
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const char *
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nds32_output_16bit_store (rtx *operands, int byte)
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{
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char pattern[100];
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char size;
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rtx code = XEXP (operands[0], 0);
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size = nds32_byte_to_size (byte);
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switch (nds32_mem_format (operands[0]))
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{
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case ADDRESS_REG:
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operands[0] = code;
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output_asm_insn ("swi450\t%1, [%0]", operands);
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break;
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case ADDRESS_LO_REG_IMM3U:
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snprintf (pattern, sizeof (pattern), "s%ci333\t%%1, %%0", size);
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output_asm_insn (pattern, operands);
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break;
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case ADDRESS_POST_INC_LO_REG_IMM3U:
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snprintf (pattern, sizeof (pattern), "s%ci333.bi\t%%1, %%0", size);
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output_asm_insn (pattern, operands);
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break;
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case ADDRESS_FP_IMM7U:
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output_asm_insn ("swi37\t%1, %0", operands);
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break;
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case ADDRESS_SP_IMM7U:
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/* Get immediate value and set back to operands[1]. */
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operands[0] = XEXP (code, 1);
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output_asm_insn ("swi37.sp\t%1, [ + (%0)]", operands);
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break;
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default:
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break;
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}
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return "";
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}
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/* Output 16-bit load. */
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const char *
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nds32_output_16bit_load (rtx *operands, int byte)
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{
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char pattern[100];
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unsigned char size;
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rtx code = XEXP (operands[1], 0);
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size = nds32_byte_to_size (byte);
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switch (nds32_mem_format (operands[1]))
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{
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case ADDRESS_REG:
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operands[1] = code;
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output_asm_insn ("lwi450\t%0, [%1]", operands);
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break;
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case ADDRESS_LO_REG_IMM3U:
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snprintf (pattern, sizeof (pattern), "l%ci333\t%%0, %%1", size);
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output_asm_insn (pattern, operands);
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break;
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case ADDRESS_POST_INC_LO_REG_IMM3U:
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snprintf (pattern, sizeof (pattern), "l%ci333.bi\t%%0, %%1", size);
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output_asm_insn (pattern, operands);
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break;
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case ADDRESS_FP_IMM7U:
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output_asm_insn ("lwi37\t%0, %1", operands);
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break;
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case ADDRESS_SP_IMM7U:
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/* Get immediate value and set back to operands[0]. */
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operands[1] = XEXP (code, 1);
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output_asm_insn ("lwi37.sp\t%0, [ + (%1)]", operands);
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break;
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default:
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break;
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}
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return "";
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}
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/* Output 32-bit store. */
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const char *
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nds32_output_32bit_store (rtx *operands, int byte)
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{
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char pattern[100];
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unsigned char size;
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rtx code = XEXP (operands[0], 0);
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size = nds32_byte_to_size (byte);
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switch (GET_CODE (code))
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{
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case REG:
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/* (mem (reg X))
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=> access location by using register,
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use "sbi / shi / swi" */
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snprintf (pattern, sizeof (pattern), "s%ci\t%%1, %%0", size);
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break;
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case SYMBOL_REF:
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case CONST:
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/* (mem (symbol_ref X))
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(mem (const (...)))
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=> access global variables,
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use "sbi.gp / shi.gp / swi.gp" */
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operands[0] = XEXP (operands[0], 0);
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snprintf (pattern, sizeof (pattern), "s%ci.gp\t%%1, [ + %%0]", size);
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break;
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case POST_INC:
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/* (mem (post_inc reg))
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=> access location by using register which will be post increment,
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use "sbi.bi / shi.bi / swi.bi" */
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snprintf (pattern, sizeof (pattern),
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"s%ci.bi\t%%1, %%0, %d", size, byte);
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break;
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case POST_DEC:
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/* (mem (post_dec reg))
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=> access location by using register which will be post decrement,
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use "sbi.bi / shi.bi / swi.bi" */
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snprintf (pattern, sizeof (pattern),
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"s%ci.bi\t%%1, %%0, -%d", size, byte);
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break;
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case POST_MODIFY:
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switch (GET_CODE (XEXP (XEXP (code, 1), 1)))
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{
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case REG:
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case SUBREG:
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/* (mem (post_modify (reg) (plus (reg) (reg))))
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=> access location by using register which will be
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post modified with reg,
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use "sb.bi/ sh.bi / sw.bi" */
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snprintf (pattern, sizeof (pattern), "s%c.bi\t%%1, %%0", size);
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break;
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case CONST_INT:
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/* (mem (post_modify (reg) (plus (reg) (const_int))))
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=> access location by using register which will be
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post modified with const_int,
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use "sbi.bi/ shi.bi / swi.bi" */
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snprintf (pattern, sizeof (pattern), "s%ci.bi\t%%1, %%0", size);
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break;
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default:
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abort ();
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}
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break;
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case PLUS:
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switch (GET_CODE (XEXP (code, 1)))
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{
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case REG:
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case SUBREG:
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/* (mem (plus reg reg)) or (mem (plus (mult reg const_int) reg))
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=> access location by adding two registers,
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use "sb / sh / sw" */
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snprintf (pattern, sizeof (pattern), "s%c\t%%1, %%0", size);
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break;
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case CONST_INT:
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/* (mem (plus reg const_int))
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=> access location by adding one register with const_int,
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use "sbi / shi / swi" */
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snprintf (pattern, sizeof (pattern), "s%ci\t%%1, %%0", size);
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break;
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default:
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abort ();
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}
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break;
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case LO_SUM:
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operands[2] = XEXP (code, 1);
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operands[0] = XEXP (code, 0);
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snprintf (pattern, sizeof (pattern),
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"s%ci\t%%1, [%%0 + lo12(%%2)]", size);
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break;
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default:
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abort ();
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}
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output_asm_insn (pattern, operands);
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return "";
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}
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/* Output 32-bit load. */
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const char *
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nds32_output_32bit_load (rtx *operands, int byte)
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{
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char pattern[100];
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unsigned char size;
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rtx code;
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code = XEXP (operands[1], 0);
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size = nds32_byte_to_size (byte);
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switch (GET_CODE (code))
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{
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case REG:
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/* (mem (reg X))
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=> access location by using register,
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use "lbi / lhi / lwi" */
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snprintf (pattern, sizeof (pattern), "l%ci\t%%0, %%1", size);
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break;
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case SYMBOL_REF:
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case CONST:
|
||||
/* (mem (symbol_ref X))
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(mem (const (...)))
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=> access global variables,
|
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use "lbi.gp / lhi.gp / lwi.gp" */
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operands[1] = XEXP (operands[1], 0);
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snprintf (pattern, sizeof (pattern), "l%ci.gp\t%%0, [ + %%1]", size);
|
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break;
|
||||
|
||||
case POST_INC:
|
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/* (mem (post_inc reg))
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=> access location by using register which will be post increment,
|
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use "lbi.bi / lhi.bi / lwi.bi" */
|
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snprintf (pattern, sizeof (pattern),
|
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"l%ci.bi\t%%0, %%1, %d", size, byte);
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break;
|
||||
|
||||
case POST_DEC:
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/* (mem (post_dec reg))
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=> access location by using register which will be post decrement,
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use "lbi.bi / lhi.bi / lwi.bi" */
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snprintf (pattern, sizeof (pattern),
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"l%ci.bi\t%%0, %%1, -%d", size, byte);
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break;
|
||||
|
||||
case POST_MODIFY:
|
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switch (GET_CODE (XEXP (XEXP (code, 1), 1)))
|
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{
|
||||
case REG:
|
||||
case SUBREG:
|
||||
/* (mem (post_modify (reg) (plus (reg) (reg))))
|
||||
=> access location by using register which will be
|
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post modified with reg,
|
||||
use "lb.bi/ lh.bi / lw.bi" */
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snprintf (pattern, sizeof (pattern), "l%c.bi\t%%0, %%1", size);
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||||
break;
|
||||
case CONST_INT:
|
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/* (mem (post_modify (reg) (plus (reg) (const_int))))
|
||||
=> access location by using register which will be
|
||||
post modified with const_int,
|
||||
use "lbi.bi/ lhi.bi / lwi.bi" */
|
||||
snprintf (pattern, sizeof (pattern), "l%ci.bi\t%%0, %%1", size);
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
break;
|
||||
|
||||
case PLUS:
|
||||
switch (GET_CODE (XEXP (code, 1)))
|
||||
{
|
||||
case REG:
|
||||
case SUBREG:
|
||||
/* (mem (plus reg reg)) or (mem (plus (mult reg const_int) reg))
|
||||
use "lb / lh / lw" */
|
||||
snprintf (pattern, sizeof (pattern), "l%c\t%%0, %%1", size);
|
||||
break;
|
||||
case CONST_INT:
|
||||
/* (mem (plus reg const_int))
|
||||
=> access location by adding one register with const_int,
|
||||
use "lbi / lhi / lwi" */
|
||||
snprintf (pattern, sizeof (pattern), "l%ci\t%%0, %%1", size);
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
break;
|
||||
|
||||
case LO_SUM:
|
||||
operands[2] = XEXP (code, 1);
|
||||
operands[1] = XEXP (code, 0);
|
||||
snprintf (pattern, sizeof (pattern),
|
||||
"l%ci\t%%0, [%%1 + lo12(%%2)]", size);
|
||||
break;
|
||||
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
|
||||
output_asm_insn (pattern, operands);
|
||||
return "";
|
||||
}
|
||||
|
||||
/* Output 32-bit load with signed extension. */
|
||||
const char *
|
||||
nds32_output_32bit_load_s (rtx *operands, int byte)
|
||||
{
|
||||
char pattern[100];
|
||||
unsigned char size;
|
||||
rtx code;
|
||||
|
||||
code = XEXP (operands[1], 0);
|
||||
|
||||
size = nds32_byte_to_size (byte);
|
||||
|
||||
switch (GET_CODE (code))
|
||||
{
|
||||
case REG:
|
||||
/* (mem (reg X))
|
||||
=> access location by using register,
|
||||
use "lbsi / lhsi" */
|
||||
snprintf (pattern, sizeof (pattern), "l%csi\t%%0, %%1", size);
|
||||
break;
|
||||
|
||||
case SYMBOL_REF:
|
||||
case CONST:
|
||||
/* (mem (symbol_ref X))
|
||||
(mem (const (...)))
|
||||
=> access global variables,
|
||||
use "lbsi.gp / lhsi.gp" */
|
||||
operands[1] = XEXP (operands[1], 0);
|
||||
snprintf (pattern, sizeof (pattern), "l%csi.gp\t%%0, [ + %%1]", size);
|
||||
break;
|
||||
|
||||
case POST_INC:
|
||||
/* (mem (post_inc reg))
|
||||
=> access location by using register which will be post increment,
|
||||
use "lbsi.bi / lhsi.bi" */
|
||||
snprintf (pattern, sizeof (pattern),
|
||||
"l%csi.bi\t%%0, %%1, %d", size, byte);
|
||||
break;
|
||||
|
||||
case POST_DEC:
|
||||
/* (mem (post_dec reg))
|
||||
=> access location by using register which will be post decrement,
|
||||
use "lbsi.bi / lhsi.bi" */
|
||||
snprintf (pattern, sizeof (pattern),
|
||||
"l%csi.bi\t%%0, %%1, -%d", size, byte);
|
||||
break;
|
||||
|
||||
case POST_MODIFY:
|
||||
switch (GET_CODE (XEXP (XEXP (code, 1), 1)))
|
||||
{
|
||||
case REG:
|
||||
case SUBREG:
|
||||
/* (mem (post_modify (reg) (plus (reg) (reg))))
|
||||
=> access location by using register which will be
|
||||
post modified with reg,
|
||||
use "lbs.bi/ lhs.bi" */
|
||||
snprintf (pattern, sizeof (pattern), "l%cs.bi\t%%0, %%1", size);
|
||||
break;
|
||||
case CONST_INT:
|
||||
/* (mem (post_modify (reg) (plus (reg) (const_int))))
|
||||
=> access location by using register which will be
|
||||
post modified with const_int,
|
||||
use "lbsi.bi/ lhsi.bi" */
|
||||
snprintf (pattern, sizeof (pattern), "l%csi.bi\t%%0, %%1", size);
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
break;
|
||||
|
||||
case PLUS:
|
||||
switch (GET_CODE (XEXP (code, 1)))
|
||||
{
|
||||
case REG:
|
||||
case SUBREG:
|
||||
/* (mem (plus reg reg)) or (mem (plus (mult reg const_int) reg))
|
||||
use "lbs / lhs" */
|
||||
snprintf (pattern, sizeof (pattern), "l%cs\t%%0, %%1", size);
|
||||
break;
|
||||
case CONST_INT:
|
||||
/* (mem (plus reg const_int))
|
||||
=> access location by adding one register with const_int,
|
||||
use "lbsi / lhsi" */
|
||||
snprintf (pattern, sizeof (pattern), "l%csi\t%%0, %%1", size);
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
break;
|
||||
|
||||
case LO_SUM:
|
||||
operands[2] = XEXP (code, 1);
|
||||
operands[1] = XEXP (code, 0);
|
||||
snprintf (pattern, sizeof (pattern),
|
||||
"l%csi\t%%0, [%%1 + lo12(%%2)]", size);
|
||||
break;
|
||||
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
|
||||
output_asm_insn (pattern, operands);
|
||||
return "";
|
||||
}
|
||||
|
||||
/* Function to output stack push operation.
|
||||
We need to deal with normal stack push multiple or stack v3push. */
|
||||
const char *
|
||||
nds32_output_stack_push (void)
|
||||
{
|
||||
/* A string pattern for output_asm_insn(). */
|
||||
char pattern[100];
|
||||
/* The operands array which will be used in output_asm_insn(). */
|
||||
rtx operands[3];
|
||||
/* Pick up callee-saved first regno and last regno for further use. */
|
||||
int rb_regno = cfun->machine->callee_saved_regs_first_regno;
|
||||
int re_regno = cfun->machine->callee_saved_regs_last_regno;
|
||||
|
||||
if (TARGET_V3PUSH)
|
||||
{
|
||||
/* For stack v3push:
|
||||
operands[0]: Re
|
||||
operands[1]: imm8u */
|
||||
|
||||
/* This variable is to check if 'push25 Re,imm8u' is available. */
|
||||
int sp_adjust;
|
||||
|
||||
/* Set operands[0]. */
|
||||
operands[0] = gen_rtx_REG (SImode, re_regno);
|
||||
|
||||
/* Check if we can generate 'push25 Re,imm8u',
|
||||
otherwise, generate 'push25 Re,0'. */
|
||||
sp_adjust = cfun->machine->local_size
|
||||
+ cfun->machine->out_args_size
|
||||
+ cfun->machine->callee_saved_area_padding_bytes;
|
||||
if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
|
||||
&& NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust))
|
||||
operands[1] = GEN_INT (sp_adjust);
|
||||
else
|
||||
operands[1] = GEN_INT (0);
|
||||
|
||||
/* Create assembly code pattern. */
|
||||
snprintf (pattern, sizeof (pattern), "push25\t%%0, %%1");
|
||||
}
|
||||
else
|
||||
{
|
||||
/* For normal stack push multiple:
|
||||
operands[0]: Rb
|
||||
operands[1]: Re
|
||||
operands[2]: En4 */
|
||||
|
||||
/* This variable is used to check if we only need to generate En4 field.
|
||||
As long as Rb==Re=SP_REGNUM, we set this variable to 1. */
|
||||
int push_en4_only_p = 0;
|
||||
|
||||
/* Set operands[0] and operands[1]. */
|
||||
operands[0] = gen_rtx_REG (SImode, rb_regno);
|
||||
operands[1] = gen_rtx_REG (SImode, re_regno);
|
||||
|
||||
/* 'smw.adm $sp,[$sp],$sp,0' means push nothing. */
|
||||
if (!cfun->machine->fp_size
|
||||
&& !cfun->machine->gp_size
|
||||
&& !cfun->machine->lp_size
|
||||
&& REGNO (operands[0]) == SP_REGNUM
|
||||
&& REGNO (operands[1]) == SP_REGNUM)
|
||||
{
|
||||
/* No need to generate instruction. */
|
||||
return "";
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If Rb==Re=SP_REGNUM, we only need to generate En4 field. */
|
||||
if (REGNO (operands[0]) == SP_REGNUM
|
||||
&& REGNO (operands[1]) == SP_REGNUM)
|
||||
push_en4_only_p = 1;
|
||||
|
||||
/* Create assembly code pattern.
|
||||
We need to handle the form: "Rb, Re, { $fp $gp $lp }". */
|
||||
snprintf (pattern, sizeof (pattern),
|
||||
"push.s\t%s{%s%s%s }",
|
||||
push_en4_only_p ? "" : "%0, %1, ",
|
||||
cfun->machine->fp_size ? " $fp" : "",
|
||||
cfun->machine->gp_size ? " $gp" : "",
|
||||
cfun->machine->lp_size ? " $lp" : "");
|
||||
}
|
||||
}
|
||||
|
||||
/* We use output_asm_insn() to output assembly code by ourself. */
|
||||
output_asm_insn (pattern, operands);
|
||||
return "";
|
||||
}
|
||||
|
||||
/* Function to output stack pop operation.
|
||||
We need to deal with normal stack pop multiple or stack v3pop. */
|
||||
const char *
|
||||
nds32_output_stack_pop (void)
|
||||
{
|
||||
/* A string pattern for output_asm_insn(). */
|
||||
char pattern[100];
|
||||
/* The operands array which will be used in output_asm_insn(). */
|
||||
rtx operands[3];
|
||||
/* Pick up callee-saved first regno and last regno for further use. */
|
||||
int rb_regno = cfun->machine->callee_saved_regs_first_regno;
|
||||
int re_regno = cfun->machine->callee_saved_regs_last_regno;
|
||||
|
||||
if (TARGET_V3PUSH)
|
||||
{
|
||||
/* For stack v3pop:
|
||||
operands[0]: Re
|
||||
operands[1]: imm8u */
|
||||
|
||||
/* This variable is to check if 'pop25 Re,imm8u' is available. */
|
||||
int sp_adjust;
|
||||
|
||||
/* Set operands[0]. */
|
||||
operands[0] = gen_rtx_REG (SImode, re_regno);
|
||||
|
||||
/* Check if we can generate 'pop25 Re,imm8u',
|
||||
otherwise, generate 'pop25 Re,0'.
|
||||
We have to consider alloca issue as well.
|
||||
If the function does call alloca(), the stack pointer is not fixed.
|
||||
In that case, we cannot use 'pop25 Re,imm8u' directly.
|
||||
We have to caculate stack pointer from frame pointer
|
||||
and then use 'pop25 Re,0'. */
|
||||
sp_adjust = cfun->machine->local_size
|
||||
+ cfun->machine->out_args_size
|
||||
+ cfun->machine->callee_saved_area_padding_bytes;
|
||||
if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
|
||||
&& NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)
|
||||
&& !cfun->calls_alloca)
|
||||
operands[1] = GEN_INT (sp_adjust);
|
||||
else
|
||||
operands[1] = GEN_INT (0);
|
||||
|
||||
/* Create assembly code pattern. */
|
||||
snprintf (pattern, sizeof (pattern), "pop25\t%%0, %%1");
|
||||
}
|
||||
else
|
||||
{
|
||||
/* For normal stack pop multiple:
|
||||
operands[0]: Rb
|
||||
operands[1]: Re
|
||||
operands[2]: En4 */
|
||||
|
||||
/* This variable is used to check if we only need to generate En4 field.
|
||||
As long as Rb==Re=SP_REGNUM, we set this variable to 1. */
|
||||
int pop_en4_only_p = 0;
|
||||
|
||||
/* Set operands[0] and operands[1]. */
|
||||
operands[0] = gen_rtx_REG (SImode, rb_regno);
|
||||
operands[1] = gen_rtx_REG (SImode, re_regno);
|
||||
|
||||
/* 'lmw.bim $sp,[$sp],$sp,0' means pop nothing. */
|
||||
if (!cfun->machine->fp_size
|
||||
&& !cfun->machine->gp_size
|
||||
&& !cfun->machine->lp_size
|
||||
&& REGNO (operands[0]) == SP_REGNUM
|
||||
&& REGNO (operands[1]) == SP_REGNUM)
|
||||
{
|
||||
/* No need to generate instruction. */
|
||||
return "";
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If Rb==Re=SP_REGNUM, we only need to generate En4 field. */
|
||||
if (REGNO (operands[0]) == SP_REGNUM
|
||||
&& REGNO (operands[1]) == SP_REGNUM)
|
||||
pop_en4_only_p = 1;
|
||||
|
||||
/* Create assembly code pattern.
|
||||
We need to handle the form: "Rb, Re, { $fp $gp $lp }". */
|
||||
snprintf (pattern, sizeof (pattern),
|
||||
"pop.s\t%s{%s%s%s }",
|
||||
pop_en4_only_p ? "" : "%0, %1, ",
|
||||
cfun->machine->fp_size ? " $fp" : "",
|
||||
cfun->machine->gp_size ? " $gp" : "",
|
||||
cfun->machine->lp_size ? " $lp" : "");
|
||||
}
|
||||
}
|
||||
|
||||
/* We use output_asm_insn() to output assembly code by ourself. */
|
||||
output_asm_insn (pattern, operands);
|
||||
return "";
|
||||
}
|
||||
|
||||
/* Function to generate PC relative jump table.
|
||||
Refer to nds32.md for more details.
|
||||
|
||||
The following is the sample for the case that diff value
|
||||
can be presented in '.short' size.
|
||||
|
||||
addi $r1, $r1, -(case_lower_bound)
|
||||
slti $ta, $r1, (case_number)
|
||||
beqz $ta, .L_skip_label
|
||||
|
||||
la $ta, .L35 ! get jump table address
|
||||
lh $r1, [$ta + $r1 << 1] ! load symbol diff from jump table entry
|
||||
addi $ta, $r1, $ta
|
||||
jr5 $ta
|
||||
|
||||
! jump table entry
|
||||
L35:
|
||||
.short .L25-.L35
|
||||
.short .L26-.L35
|
||||
.short .L27-.L35
|
||||
.short .L28-.L35
|
||||
.short .L29-.L35
|
||||
.short .L30-.L35
|
||||
.short .L31-.L35
|
||||
.short .L32-.L35
|
||||
.short .L33-.L35
|
||||
.short .L34-.L35 */
|
||||
const char *
|
||||
nds32_output_casesi_pc_relative (rtx *operands)
|
||||
{
|
||||
enum machine_mode mode;
|
||||
rtx diff_vec;
|
||||
|
||||
diff_vec = PATTERN (NEXT_INSN (operands[1]));
|
||||
|
||||
gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
|
||||
|
||||
/* Step C: "t <-- operands[1]". */
|
||||
output_asm_insn ("la\t$ta, %l1", operands);
|
||||
|
||||
/* Get the mode of each element in the difference vector. */
|
||||
mode = GET_MODE (diff_vec);
|
||||
|
||||
/* Step D: "z <-- (mem (plus (operands[0] << m) t))",
|
||||
where m is 0, 1, or 2 to load address-diff value from table. */
|
||||
switch (mode)
|
||||
{
|
||||
case QImode:
|
||||
output_asm_insn ("lb\t%2, [$ta + %0 << 0]", operands);
|
||||
break;
|
||||
case HImode:
|
||||
output_asm_insn ("lh\t%2, [$ta + %0 << 1]", operands);
|
||||
break;
|
||||
case SImode:
|
||||
output_asm_insn ("lw\t%2, [$ta + %0 << 2]", operands);
|
||||
break;
|
||||
default:
|
||||
gcc_unreachable ();
|
||||
}
|
||||
|
||||
/* Step E: "t <-- z + t".
|
||||
Add table label_ref with address-diff value to
|
||||
obtain target case address. */
|
||||
output_asm_insn ("add\t$ta, %2, $ta", operands);
|
||||
|
||||
/* Step F: jump to target with register t. */
|
||||
if (TARGET_16_BIT)
|
||||
return "jr5\t$ta";
|
||||
else
|
||||
return "jr\t$ta";
|
||||
}
|
||||
|
||||
/* Function to generate normal jump table. */
|
||||
const char *
|
||||
nds32_output_casesi (rtx *operands)
|
||||
{
|
||||
/* Step C: "t <-- operands[1]". */
|
||||
output_asm_insn ("la\t$ta, %l1", operands);
|
||||
|
||||
/* Step D: "z <-- (mem (plus (operands[0] << 2) t))". */
|
||||
output_asm_insn ("lw\t%2, [$ta + %0 << 2]", operands);
|
||||
|
||||
/* No need to perform Step E, which is only used for
|
||||
pc relative jump table. */
|
||||
|
||||
/* Step F: jump to target with register z. */
|
||||
if (TARGET_16_BIT)
|
||||
return "jr5\t%2";
|
||||
else
|
||||
return "jr\t%2";
|
||||
}
|
||||
|
||||
/* ------------------------------------------------------------------------ */
|
||||
|
|
|
|||
|
|
@ -1106,24 +1106,6 @@ nds32_legitimate_index_p (enum machine_mode outer_mode,
|
|||
}
|
||||
}
|
||||
|
||||
/* A helper function to return character based on byte size. */
|
||||
static char
|
||||
nds32_byte_to_size (int byte)
|
||||
{
|
||||
switch (byte)
|
||||
{
|
||||
case 4:
|
||||
return 'w';
|
||||
case 2:
|
||||
return 'h';
|
||||
case 1:
|
||||
return 'b';
|
||||
default:
|
||||
/* Normally it should not be here. */
|
||||
gcc_unreachable ();
|
||||
}
|
||||
}
|
||||
|
||||
/* A helper function to check if this function should contain prologue. */
|
||||
static int
|
||||
nds32_have_prologue_p (void)
|
||||
|
|
@ -3436,767 +3418,6 @@ nds32_fp_as_gp_check_available (void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
|
||||
/* Function to generate PC relative jump table.
|
||||
Refer to nds32.md for more details.
|
||||
|
||||
The following is the sample for the case that diff value
|
||||
can be presented in '.short' size.
|
||||
|
||||
addi $r1, $r1, -(case_lower_bound)
|
||||
slti $ta, $r1, (case_number)
|
||||
beqz $ta, .L_skip_label
|
||||
|
||||
la $ta, .L35 ! get jump table address
|
||||
lh $r1, [$ta + $r1 << 1] ! load symbol diff from jump table entry
|
||||
addi $ta, $r1, $ta
|
||||
jr5 $ta
|
||||
|
||||
! jump table entry
|
||||
L35:
|
||||
.short .L25-.L35
|
||||
.short .L26-.L35
|
||||
.short .L27-.L35
|
||||
.short .L28-.L35
|
||||
.short .L29-.L35
|
||||
.short .L30-.L35
|
||||
.short .L31-.L35
|
||||
.short .L32-.L35
|
||||
.short .L33-.L35
|
||||
.short .L34-.L35 */
|
||||
const char *
|
||||
nds32_output_casesi_pc_relative (rtx *operands)
|
||||
{
|
||||
enum machine_mode mode;
|
||||
rtx diff_vec;
|
||||
|
||||
diff_vec = PATTERN (NEXT_INSN (operands[1]));
|
||||
|
||||
gcc_assert (GET_CODE (diff_vec) == ADDR_DIFF_VEC);
|
||||
|
||||
/* Step C: "t <-- operands[1]". */
|
||||
output_asm_insn ("la\t$ta, %l1", operands);
|
||||
|
||||
/* Get the mode of each element in the difference vector. */
|
||||
mode = GET_MODE (diff_vec);
|
||||
|
||||
/* Step D: "z <-- (mem (plus (operands[0] << m) t))",
|
||||
where m is 0, 1, or 2 to load address-diff value from table. */
|
||||
switch (mode)
|
||||
{
|
||||
case QImode:
|
||||
output_asm_insn ("lb\t%2, [$ta + %0 << 0]", operands);
|
||||
break;
|
||||
case HImode:
|
||||
output_asm_insn ("lh\t%2, [$ta + %0 << 1]", operands);
|
||||
break;
|
||||
case SImode:
|
||||
output_asm_insn ("lw\t%2, [$ta + %0 << 2]", operands);
|
||||
break;
|
||||
default:
|
||||
gcc_unreachable ();
|
||||
}
|
||||
|
||||
/* Step E: "t <-- z + t".
|
||||
Add table label_ref with address-diff value to
|
||||
obtain target case address. */
|
||||
output_asm_insn ("add\t$ta, %2, $ta", operands);
|
||||
|
||||
/* Step F: jump to target with register t. */
|
||||
if (TARGET_16_BIT)
|
||||
return "jr5\t$ta";
|
||||
else
|
||||
return "jr\t$ta";
|
||||
}
|
||||
|
||||
/* Function to generate normal jump table. */
|
||||
const char *
|
||||
nds32_output_casesi (rtx *operands)
|
||||
{
|
||||
/* Step C: "t <-- operands[1]". */
|
||||
output_asm_insn ("la\t$ta, %l1", operands);
|
||||
|
||||
/* Step D: "z <-- (mem (plus (operands[0] << 2) t))". */
|
||||
output_asm_insn ("lw\t%2, [$ta + %0 << 2]", operands);
|
||||
|
||||
/* No need to perform Step E, which is only used for
|
||||
pc relative jump table. */
|
||||
|
||||
/* Step F: jump to target with register z. */
|
||||
if (TARGET_16_BIT)
|
||||
return "jr5\t%2";
|
||||
else
|
||||
return "jr\t%2";
|
||||
}
|
||||
|
||||
|
||||
/* Function to return memory format. */
|
||||
enum nds32_16bit_address_type
|
||||
nds32_mem_format (rtx op)
|
||||
{
|
||||
enum machine_mode mode_test;
|
||||
int val;
|
||||
int regno;
|
||||
|
||||
if (!TARGET_16_BIT)
|
||||
return ADDRESS_NOT_16BIT_FORMAT;
|
||||
|
||||
mode_test = GET_MODE (op);
|
||||
|
||||
op = XEXP (op, 0);
|
||||
|
||||
/* 45 format. */
|
||||
if (GET_CODE (op) == REG && (mode_test == SImode))
|
||||
return ADDRESS_REG;
|
||||
|
||||
/* 333 format for QI/HImode. */
|
||||
if (GET_CODE (op) == REG && (REGNO (op) < R8_REGNUM))
|
||||
return ADDRESS_LO_REG_IMM3U;
|
||||
|
||||
/* post_inc 333 format. */
|
||||
if ((GET_CODE (op) == POST_INC) && (mode_test == SImode))
|
||||
{
|
||||
regno = REGNO(XEXP (op, 0));
|
||||
|
||||
if (regno < 8)
|
||||
return ADDRESS_POST_INC_LO_REG_IMM3U;
|
||||
}
|
||||
|
||||
/* post_inc 333 format. */
|
||||
if ((GET_CODE (op) == POST_MODIFY)
|
||||
&& (mode_test == SImode)
|
||||
&& (REG_P (XEXP (XEXP (op, 1), 0)))
|
||||
&& (CONST_INT_P (XEXP (XEXP (op, 1), 1))))
|
||||
{
|
||||
regno = REGNO (XEXP (XEXP (op, 1), 0));
|
||||
val = INTVAL (XEXP (XEXP (op, 1), 1));
|
||||
if (regno < 8 && val < 32)
|
||||
return ADDRESS_POST_INC_LO_REG_IMM3U;
|
||||
}
|
||||
|
||||
if ((GET_CODE (op) == PLUS)
|
||||
&& (GET_CODE (XEXP (op, 0)) == REG)
|
||||
&& (GET_CODE (XEXP (op, 1)) == CONST_INT))
|
||||
{
|
||||
val = INTVAL (XEXP (op, 1));
|
||||
|
||||
regno = REGNO(XEXP (op, 0));
|
||||
|
||||
if (regno > 7
|
||||
&& regno != SP_REGNUM
|
||||
&& regno != FP_REGNUM)
|
||||
return ADDRESS_NOT_16BIT_FORMAT;
|
||||
|
||||
switch (mode_test)
|
||||
{
|
||||
case QImode:
|
||||
/* 333 format. */
|
||||
if (val >= 0 && val < 8 && regno < 8)
|
||||
return ADDRESS_LO_REG_IMM3U;
|
||||
break;
|
||||
|
||||
case HImode:
|
||||
/* 333 format. */
|
||||
if (val >= 0 && val < 16 && (val % 2 == 0) && regno < 8)
|
||||
return ADDRESS_LO_REG_IMM3U;
|
||||
break;
|
||||
|
||||
case SImode:
|
||||
case SFmode:
|
||||
case DFmode:
|
||||
/* fp imply 37 format. */
|
||||
if ((regno == FP_REGNUM) &&
|
||||
(val >= 0 && val < 512 && (val % 4 == 0)))
|
||||
return ADDRESS_FP_IMM7U;
|
||||
/* sp imply 37 format. */
|
||||
else if ((regno == SP_REGNUM) &&
|
||||
(val >= 0 && val < 512 && (val % 4 == 0)))
|
||||
return ADDRESS_SP_IMM7U;
|
||||
/* 333 format. */
|
||||
else if (val >= 0 && val < 32 && (val % 4 == 0) && regno < 8)
|
||||
return ADDRESS_LO_REG_IMM3U;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return ADDRESS_NOT_16BIT_FORMAT;
|
||||
}
|
||||
|
||||
/* Output 16-bit store. */
|
||||
const char *
|
||||
nds32_output_16bit_store (rtx *operands, int byte)
|
||||
{
|
||||
char pattern[100];
|
||||
char size;
|
||||
rtx code = XEXP (operands[0], 0);
|
||||
|
||||
size = nds32_byte_to_size (byte);
|
||||
|
||||
switch (nds32_mem_format (operands[0]))
|
||||
{
|
||||
case ADDRESS_REG:
|
||||
operands[0] = code;
|
||||
output_asm_insn ("swi450\t%1, [%0]", operands);
|
||||
break;
|
||||
case ADDRESS_LO_REG_IMM3U:
|
||||
snprintf (pattern, sizeof (pattern), "s%ci333\t%%1, %%0", size);
|
||||
output_asm_insn (pattern, operands);
|
||||
break;
|
||||
case ADDRESS_POST_INC_LO_REG_IMM3U:
|
||||
snprintf (pattern, sizeof (pattern), "s%ci333.bi\t%%1, %%0", size);
|
||||
output_asm_insn (pattern, operands);
|
||||
break;
|
||||
case ADDRESS_FP_IMM7U:
|
||||
output_asm_insn ("swi37\t%1, %0", operands);
|
||||
break;
|
||||
case ADDRESS_SP_IMM7U:
|
||||
/* Get immediate value and set back to operands[1]. */
|
||||
operands[0] = XEXP (code, 1);
|
||||
output_asm_insn ("swi37.sp\t%1, [ + (%0)]", operands);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return "";
|
||||
}
|
||||
|
||||
/* Output 16-bit load. */
|
||||
const char *
|
||||
nds32_output_16bit_load (rtx *operands, int byte)
|
||||
{
|
||||
char pattern[100];
|
||||
unsigned char size;
|
||||
rtx code = XEXP (operands[1], 0);
|
||||
|
||||
size = nds32_byte_to_size (byte);
|
||||
|
||||
switch (nds32_mem_format (operands[1]))
|
||||
{
|
||||
case ADDRESS_REG:
|
||||
operands[1] = code;
|
||||
output_asm_insn ("lwi450\t%0, [%1]", operands);
|
||||
break;
|
||||
case ADDRESS_LO_REG_IMM3U:
|
||||
snprintf (pattern, sizeof (pattern), "l%ci333\t%%0, %%1", size);
|
||||
output_asm_insn (pattern, operands);
|
||||
break;
|
||||
case ADDRESS_POST_INC_LO_REG_IMM3U:
|
||||
snprintf (pattern, sizeof (pattern), "l%ci333.bi\t%%0, %%1", size);
|
||||
output_asm_insn (pattern, operands);
|
||||
break;
|
||||
case ADDRESS_FP_IMM7U:
|
||||
output_asm_insn ("lwi37\t%0, %1", operands);
|
||||
break;
|
||||
case ADDRESS_SP_IMM7U:
|
||||
/* Get immediate value and set back to operands[0]. */
|
||||
operands[1] = XEXP (code, 1);
|
||||
output_asm_insn ("lwi37.sp\t%0, [ + (%1)]", operands);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return "";
|
||||
}
|
||||
|
||||
/* Output 32-bit store. */
|
||||
const char *
|
||||
nds32_output_32bit_store (rtx *operands, int byte)
|
||||
{
|
||||
char pattern[100];
|
||||
unsigned char size;
|
||||
rtx code = XEXP (operands[0], 0);
|
||||
|
||||
size = nds32_byte_to_size (byte);
|
||||
|
||||
switch (GET_CODE (code))
|
||||
{
|
||||
case REG:
|
||||
/* (mem (reg X))
|
||||
=> access location by using register,
|
||||
use "sbi / shi / swi" */
|
||||
snprintf (pattern, sizeof (pattern), "s%ci\t%%1, %%0", size);
|
||||
break;
|
||||
|
||||
case SYMBOL_REF:
|
||||
case CONST:
|
||||
/* (mem (symbol_ref X))
|
||||
(mem (const (...)))
|
||||
=> access global variables,
|
||||
use "sbi.gp / shi.gp / swi.gp" */
|
||||
operands[0] = XEXP (operands[0], 0);
|
||||
snprintf (pattern, sizeof (pattern), "s%ci.gp\t%%1, [ + %%0]", size);
|
||||
break;
|
||||
|
||||
case POST_INC:
|
||||
/* (mem (post_inc reg))
|
||||
=> access location by using register which will be post increment,
|
||||
use "sbi.bi / shi.bi / swi.bi" */
|
||||
snprintf (pattern, sizeof (pattern),
|
||||
"s%ci.bi\t%%1, %%0, %d", size, byte);
|
||||
break;
|
||||
|
||||
case POST_DEC:
|
||||
/* (mem (post_dec reg))
|
||||
=> access location by using register which will be post decrement,
|
||||
use "sbi.bi / shi.bi / swi.bi" */
|
||||
snprintf (pattern, sizeof (pattern),
|
||||
"s%ci.bi\t%%1, %%0, -%d", size, byte);
|
||||
break;
|
||||
|
||||
case POST_MODIFY:
|
||||
switch (GET_CODE (XEXP (XEXP (code, 1), 1)))
|
||||
{
|
||||
case REG:
|
||||
case SUBREG:
|
||||
/* (mem (post_modify (reg) (plus (reg) (reg))))
|
||||
=> access location by using register which will be
|
||||
post modified with reg,
|
||||
use "sb.bi/ sh.bi / sw.bi" */
|
||||
snprintf (pattern, sizeof (pattern), "s%c.bi\t%%1, %%0", size);
|
||||
break;
|
||||
case CONST_INT:
|
||||
/* (mem (post_modify (reg) (plus (reg) (const_int))))
|
||||
=> access location by using register which will be
|
||||
post modified with const_int,
|
||||
use "sbi.bi/ shi.bi / swi.bi" */
|
||||
snprintf (pattern, sizeof (pattern), "s%ci.bi\t%%1, %%0", size);
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
break;
|
||||
|
||||
case PLUS:
|
||||
switch (GET_CODE (XEXP (code, 1)))
|
||||
{
|
||||
case REG:
|
||||
case SUBREG:
|
||||
/* (mem (plus reg reg)) or (mem (plus (mult reg const_int) reg))
|
||||
=> access location by adding two registers,
|
||||
use "sb / sh / sw" */
|
||||
snprintf (pattern, sizeof (pattern), "s%c\t%%1, %%0", size);
|
||||
break;
|
||||
case CONST_INT:
|
||||
/* (mem (plus reg const_int))
|
||||
=> access location by adding one register with const_int,
|
||||
use "sbi / shi / swi" */
|
||||
snprintf (pattern, sizeof (pattern), "s%ci\t%%1, %%0", size);
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
break;
|
||||
|
||||
case LO_SUM:
|
||||
operands[2] = XEXP (code, 1);
|
||||
operands[0] = XEXP (code, 0);
|
||||
snprintf (pattern, sizeof (pattern),
|
||||
"s%ci\t%%1, [%%0 + lo12(%%2)]", size);
|
||||
break;
|
||||
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
|
||||
output_asm_insn (pattern, operands);
|
||||
return "";
|
||||
}
|
||||
|
||||
/* Output 32-bit load. */
|
||||
const char *
|
||||
nds32_output_32bit_load (rtx *operands, int byte)
|
||||
{
|
||||
char pattern[100];
|
||||
unsigned char size;
|
||||
rtx code;
|
||||
|
||||
code = XEXP (operands[1], 0);
|
||||
|
||||
size = nds32_byte_to_size (byte);
|
||||
|
||||
switch (GET_CODE (code))
|
||||
{
|
||||
case REG:
|
||||
/* (mem (reg X))
|
||||
=> access location by using register,
|
||||
use "lbi / lhi / lwi" */
|
||||
snprintf (pattern, sizeof (pattern), "l%ci\t%%0, %%1", size);
|
||||
break;
|
||||
|
||||
case SYMBOL_REF:
|
||||
case CONST:
|
||||
/* (mem (symbol_ref X))
|
||||
(mem (const (...)))
|
||||
=> access global variables,
|
||||
use "lbi.gp / lhi.gp / lwi.gp" */
|
||||
operands[1] = XEXP (operands[1], 0);
|
||||
snprintf (pattern, sizeof (pattern), "l%ci.gp\t%%0, [ + %%1]", size);
|
||||
break;
|
||||
|
||||
case POST_INC:
|
||||
/* (mem (post_inc reg))
|
||||
=> access location by using register which will be post increment,
|
||||
use "lbi.bi / lhi.bi / lwi.bi" */
|
||||
snprintf (pattern, sizeof (pattern),
|
||||
"l%ci.bi\t%%0, %%1, %d", size, byte);
|
||||
break;
|
||||
|
||||
case POST_DEC:
|
||||
/* (mem (post_dec reg))
|
||||
=> access location by using register which will be post decrement,
|
||||
use "lbi.bi / lhi.bi / lwi.bi" */
|
||||
snprintf (pattern, sizeof (pattern),
|
||||
"l%ci.bi\t%%0, %%1, -%d", size, byte);
|
||||
break;
|
||||
|
||||
case POST_MODIFY:
|
||||
switch (GET_CODE (XEXP (XEXP (code, 1), 1)))
|
||||
{
|
||||
case REG:
|
||||
case SUBREG:
|
||||
/* (mem (post_modify (reg) (plus (reg) (reg))))
|
||||
=> access location by using register which will be
|
||||
post modified with reg,
|
||||
use "lb.bi/ lh.bi / lw.bi" */
|
||||
snprintf (pattern, sizeof (pattern), "l%c.bi\t%%0, %%1", size);
|
||||
break;
|
||||
case CONST_INT:
|
||||
/* (mem (post_modify (reg) (plus (reg) (const_int))))
|
||||
=> access location by using register which will be
|
||||
post modified with const_int,
|
||||
use "lbi.bi/ lhi.bi / lwi.bi" */
|
||||
snprintf (pattern, sizeof (pattern), "l%ci.bi\t%%0, %%1", size);
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
break;
|
||||
|
||||
case PLUS:
|
||||
switch (GET_CODE (XEXP (code, 1)))
|
||||
{
|
||||
case REG:
|
||||
case SUBREG:
|
||||
/* (mem (plus reg reg)) or (mem (plus (mult reg const_int) reg))
|
||||
use "lb / lh / lw" */
|
||||
snprintf (pattern, sizeof (pattern), "l%c\t%%0, %%1", size);
|
||||
break;
|
||||
case CONST_INT:
|
||||
/* (mem (plus reg const_int))
|
||||
=> access location by adding one register with const_int,
|
||||
use "lbi / lhi / lwi" */
|
||||
snprintf (pattern, sizeof (pattern), "l%ci\t%%0, %%1", size);
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
break;
|
||||
|
||||
case LO_SUM:
|
||||
operands[2] = XEXP (code, 1);
|
||||
operands[1] = XEXP (code, 0);
|
||||
snprintf (pattern, sizeof (pattern),
|
||||
"l%ci\t%%0, [%%1 + lo12(%%2)]", size);
|
||||
break;
|
||||
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
|
||||
output_asm_insn (pattern, operands);
|
||||
return "";
|
||||
}
|
||||
|
||||
/* Output 32-bit load with signed extension. */
|
||||
const char *
|
||||
nds32_output_32bit_load_s (rtx *operands, int byte)
|
||||
{
|
||||
char pattern[100];
|
||||
unsigned char size;
|
||||
rtx code;
|
||||
|
||||
code = XEXP (operands[1], 0);
|
||||
|
||||
size = nds32_byte_to_size (byte);
|
||||
|
||||
switch (GET_CODE (code))
|
||||
{
|
||||
case REG:
|
||||
/* (mem (reg X))
|
||||
=> access location by using register,
|
||||
use "lbsi / lhsi" */
|
||||
snprintf (pattern, sizeof (pattern), "l%csi\t%%0, %%1", size);
|
||||
break;
|
||||
|
||||
case SYMBOL_REF:
|
||||
case CONST:
|
||||
/* (mem (symbol_ref X))
|
||||
(mem (const (...)))
|
||||
=> access global variables,
|
||||
use "lbsi.gp / lhsi.gp" */
|
||||
operands[1] = XEXP (operands[1], 0);
|
||||
snprintf (pattern, sizeof (pattern), "l%csi.gp\t%%0, [ + %%1]", size);
|
||||
break;
|
||||
|
||||
case POST_INC:
|
||||
/* (mem (post_inc reg))
|
||||
=> access location by using register which will be post increment,
|
||||
use "lbsi.bi / lhsi.bi" */
|
||||
snprintf (pattern, sizeof (pattern),
|
||||
"l%csi.bi\t%%0, %%1, %d", size, byte);
|
||||
break;
|
||||
|
||||
case POST_DEC:
|
||||
/* (mem (post_dec reg))
|
||||
=> access location by using register which will be post decrement,
|
||||
use "lbsi.bi / lhsi.bi" */
|
||||
snprintf (pattern, sizeof (pattern),
|
||||
"l%csi.bi\t%%0, %%1, -%d", size, byte);
|
||||
break;
|
||||
|
||||
case POST_MODIFY:
|
||||
switch (GET_CODE (XEXP (XEXP (code, 1), 1)))
|
||||
{
|
||||
case REG:
|
||||
case SUBREG:
|
||||
/* (mem (post_modify (reg) (plus (reg) (reg))))
|
||||
=> access location by using register which will be
|
||||
post modified with reg,
|
||||
use "lbs.bi/ lhs.bi" */
|
||||
snprintf (pattern, sizeof (pattern), "l%cs.bi\t%%0, %%1", size);
|
||||
break;
|
||||
case CONST_INT:
|
||||
/* (mem (post_modify (reg) (plus (reg) (const_int))))
|
||||
=> access location by using register which will be
|
||||
post modified with const_int,
|
||||
use "lbsi.bi/ lhsi.bi" */
|
||||
snprintf (pattern, sizeof (pattern), "l%csi.bi\t%%0, %%1", size);
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
break;
|
||||
|
||||
case PLUS:
|
||||
switch (GET_CODE (XEXP (code, 1)))
|
||||
{
|
||||
case REG:
|
||||
case SUBREG:
|
||||
/* (mem (plus reg reg)) or (mem (plus (mult reg const_int) reg))
|
||||
use "lbs / lhs" */
|
||||
snprintf (pattern, sizeof (pattern), "l%cs\t%%0, %%1", size);
|
||||
break;
|
||||
case CONST_INT:
|
||||
/* (mem (plus reg const_int))
|
||||
=> access location by adding one register with const_int,
|
||||
use "lbsi / lhsi" */
|
||||
snprintf (pattern, sizeof (pattern), "l%csi\t%%0, %%1", size);
|
||||
break;
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
break;
|
||||
|
||||
case LO_SUM:
|
||||
operands[2] = XEXP (code, 1);
|
||||
operands[1] = XEXP (code, 0);
|
||||
snprintf (pattern, sizeof (pattern),
|
||||
"l%csi\t%%0, [%%1 + lo12(%%2)]", size);
|
||||
break;
|
||||
|
||||
default:
|
||||
abort ();
|
||||
}
|
||||
|
||||
output_asm_insn (pattern, operands);
|
||||
return "";
|
||||
}
|
||||
|
||||
/* Function to output stack push operation.
|
||||
We need to deal with normal stack push multiple or stack v3push. */
|
||||
const char *
|
||||
nds32_output_stack_push (void)
|
||||
{
|
||||
/* A string pattern for output_asm_insn(). */
|
||||
char pattern[100];
|
||||
/* The operands array which will be used in output_asm_insn(). */
|
||||
rtx operands[3];
|
||||
/* Pick up callee-saved first regno and last regno for further use. */
|
||||
int rb_regno = cfun->machine->callee_saved_regs_first_regno;
|
||||
int re_regno = cfun->machine->callee_saved_regs_last_regno;
|
||||
|
||||
if (TARGET_V3PUSH)
|
||||
{
|
||||
/* For stack v3push:
|
||||
operands[0]: Re
|
||||
operands[1]: imm8u */
|
||||
|
||||
/* This variable is to check if 'push25 Re,imm8u' is available. */
|
||||
int sp_adjust;
|
||||
|
||||
/* Set operands[0]. */
|
||||
operands[0] = gen_rtx_REG (SImode, re_regno);
|
||||
|
||||
/* Check if we can generate 'push25 Re,imm8u',
|
||||
otherwise, generate 'push25 Re,0'. */
|
||||
sp_adjust = cfun->machine->local_size
|
||||
+ cfun->machine->out_args_size
|
||||
+ cfun->machine->callee_saved_area_padding_bytes;
|
||||
if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
|
||||
&& NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust))
|
||||
operands[1] = GEN_INT (sp_adjust);
|
||||
else
|
||||
operands[1] = GEN_INT (0);
|
||||
|
||||
/* Create assembly code pattern. */
|
||||
snprintf (pattern, sizeof (pattern), "push25\t%%0, %%1");
|
||||
}
|
||||
else
|
||||
{
|
||||
/* For normal stack push multiple:
|
||||
operands[0]: Rb
|
||||
operands[1]: Re
|
||||
operands[2]: En4 */
|
||||
|
||||
/* This variable is used to check if we only need to generate En4 field.
|
||||
As long as Rb==Re=SP_REGNUM, we set this variable to 1. */
|
||||
int push_en4_only_p = 0;
|
||||
|
||||
/* Set operands[0] and operands[1]. */
|
||||
operands[0] = gen_rtx_REG (SImode, rb_regno);
|
||||
operands[1] = gen_rtx_REG (SImode, re_regno);
|
||||
|
||||
/* 'smw.adm $sp,[$sp],$sp,0' means push nothing. */
|
||||
if (!cfun->machine->fp_size
|
||||
&& !cfun->machine->gp_size
|
||||
&& !cfun->machine->lp_size
|
||||
&& REGNO (operands[0]) == SP_REGNUM
|
||||
&& REGNO (operands[1]) == SP_REGNUM)
|
||||
{
|
||||
/* No need to generate instruction. */
|
||||
return "";
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If Rb==Re=SP_REGNUM, we only need to generate En4 field. */
|
||||
if (REGNO (operands[0]) == SP_REGNUM
|
||||
&& REGNO (operands[1]) == SP_REGNUM)
|
||||
push_en4_only_p = 1;
|
||||
|
||||
/* Create assembly code pattern.
|
||||
We need to handle the form: "Rb, Re, { $fp $gp $lp }". */
|
||||
snprintf (pattern, sizeof (pattern),
|
||||
"push.s\t%s{%s%s%s }",
|
||||
push_en4_only_p ? "" : "%0, %1, ",
|
||||
cfun->machine->fp_size ? " $fp" : "",
|
||||
cfun->machine->gp_size ? " $gp" : "",
|
||||
cfun->machine->lp_size ? " $lp" : "");
|
||||
}
|
||||
}
|
||||
|
||||
/* We use output_asm_insn() to output assembly code by ourself. */
|
||||
output_asm_insn (pattern, operands);
|
||||
return "";
|
||||
}
|
||||
|
||||
/* Function to output stack pop operation.
|
||||
We need to deal with normal stack pop multiple or stack v3pop. */
|
||||
const char *
|
||||
nds32_output_stack_pop (void)
|
||||
{
|
||||
/* A string pattern for output_asm_insn(). */
|
||||
char pattern[100];
|
||||
/* The operands array which will be used in output_asm_insn(). */
|
||||
rtx operands[3];
|
||||
/* Pick up callee-saved first regno and last regno for further use. */
|
||||
int rb_regno = cfun->machine->callee_saved_regs_first_regno;
|
||||
int re_regno = cfun->machine->callee_saved_regs_last_regno;
|
||||
|
||||
if (TARGET_V3PUSH)
|
||||
{
|
||||
/* For stack v3pop:
|
||||
operands[0]: Re
|
||||
operands[1]: imm8u */
|
||||
|
||||
/* This variable is to check if 'pop25 Re,imm8u' is available. */
|
||||
int sp_adjust;
|
||||
|
||||
/* Set operands[0]. */
|
||||
operands[0] = gen_rtx_REG (SImode, re_regno);
|
||||
|
||||
/* Check if we can generate 'pop25 Re,imm8u',
|
||||
otherwise, generate 'pop25 Re,0'.
|
||||
We have to consider alloca issue as well.
|
||||
If the function does call alloca(), the stack pointer is not fixed.
|
||||
In that case, we cannot use 'pop25 Re,imm8u' directly.
|
||||
We have to caculate stack pointer from frame pointer
|
||||
and then use 'pop25 Re,0'. */
|
||||
sp_adjust = cfun->machine->local_size
|
||||
+ cfun->machine->out_args_size
|
||||
+ cfun->machine->callee_saved_area_padding_bytes;
|
||||
if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust))
|
||||
&& NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)
|
||||
&& !cfun->calls_alloca)
|
||||
operands[1] = GEN_INT (sp_adjust);
|
||||
else
|
||||
operands[1] = GEN_INT (0);
|
||||
|
||||
/* Create assembly code pattern. */
|
||||
snprintf (pattern, sizeof (pattern), "pop25\t%%0, %%1");
|
||||
}
|
||||
else
|
||||
{
|
||||
/* For normal stack pop multiple:
|
||||
operands[0]: Rb
|
||||
operands[1]: Re
|
||||
operands[2]: En4 */
|
||||
|
||||
/* This variable is used to check if we only need to generate En4 field.
|
||||
As long as Rb==Re=SP_REGNUM, we set this variable to 1. */
|
||||
int pop_en4_only_p = 0;
|
||||
|
||||
/* Set operands[0] and operands[1]. */
|
||||
operands[0] = gen_rtx_REG (SImode, rb_regno);
|
||||
operands[1] = gen_rtx_REG (SImode, re_regno);
|
||||
|
||||
/* 'lmw.bim $sp,[$sp],$sp,0' means pop nothing. */
|
||||
if (!cfun->machine->fp_size
|
||||
&& !cfun->machine->gp_size
|
||||
&& !cfun->machine->lp_size
|
||||
&& REGNO (operands[0]) == SP_REGNUM
|
||||
&& REGNO (operands[1]) == SP_REGNUM)
|
||||
{
|
||||
/* No need to generate instruction. */
|
||||
return "";
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If Rb==Re=SP_REGNUM, we only need to generate En4 field. */
|
||||
if (REGNO (operands[0]) == SP_REGNUM
|
||||
&& REGNO (operands[1]) == SP_REGNUM)
|
||||
pop_en4_only_p = 1;
|
||||
|
||||
/* Create assembly code pattern.
|
||||
We need to handle the form: "Rb, Re, { $fp $gp $lp }". */
|
||||
snprintf (pattern, sizeof (pattern),
|
||||
"pop.s\t%s{%s%s%s }",
|
||||
pop_en4_only_p ? "" : "%0, %1, ",
|
||||
cfun->machine->fp_size ? " $fp" : "",
|
||||
cfun->machine->gp_size ? " $gp" : "",
|
||||
cfun->machine->lp_size ? " $lp" : "");
|
||||
}
|
||||
}
|
||||
|
||||
/* We use output_asm_insn() to output assembly code by ourself. */
|
||||
output_asm_insn (pattern, operands);
|
||||
return "";
|
||||
}
|
||||
|
||||
/* Return align 2 (log base 2) if the next instruction of LABEL is 4 byte. */
|
||||
int
|
||||
nds32_target_alignment (rtx label)
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue