i386: Use parametrized pattern names some more.
Use parameterized pattern names to simplify calling of named patterns. 2020-08-15 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: * config/i386/i386-builtin.def (__builtin_ia32_bextri_u32) (__builtin_ia32_bextri_u64): Use CODE_FOR_nothing. * config/i386/i386.md (@tbm_bextri_<mode>): Implement as parametrized name pattern. (@rdrand<mode>): Ditto. (@rdseed<mode>): Ditto. * config/i386/i386-expand.c (ix86_expand_builtin) [case IX86_BUILTIN_BEXTRI32, case IX86_BUILTIN_BEXTRI64]: Update for parameterized name patterns. [case IX86_BUILTIN_RDRAND16_STEP, case IX86_BUILTIN_RDRAND32_STEP] [case IX86_BUILTIN_RDRAND64_STEP]: Ditto. [case IX86_BUILTIN_RDSEED16_STEP, case IX86_BUILTIN_RDSEED32_STEP] [case IX86_BUILTIN_RDSEED64_STEP]: Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/rdrand-1.c (dg-final): Update scan string. * gcc.target/i386/rdrand-2.c (dg-final): Ditto. * gcc.target/i386/rdrand-3.c (dg-final): Ditto.
This commit is contained in:
Uros Bizjak
parent
26fdc47da7
commit
9e02619154
6 changed files with 52 additions and 68 deletions
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@ -1270,8 +1270,8 @@ BDESC (OPTION_MASK_ISA_BMI, 0, CODE_FOR_tzcnt_si, "__builtin_ia32_tzcnt_u32", IX
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BDESC (OPTION_MASK_ISA_BMI | OPTION_MASK_ISA_64BIT, 0, CODE_FOR_tzcnt_di, "__builtin_ia32_tzcnt_u64", IX86_BUILTIN_TZCNT64, UNKNOWN, (int) UINT64_FTYPE_UINT64)
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/* TBM */
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BDESC (OPTION_MASK_ISA_TBM, 0, CODE_FOR_tbm_bextri_si, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT)
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BDESC (OPTION_MASK_ISA_TBM | OPTION_MASK_ISA_64BIT, 0, CODE_FOR_tbm_bextri_di, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64)
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BDESC (OPTION_MASK_ISA_TBM, 0, CODE_FOR_nothing, "__builtin_ia32_bextri_u32", IX86_BUILTIN_BEXTRI32, UNKNOWN, (int) UINT_FTYPE_UINT_UINT)
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BDESC (OPTION_MASK_ISA_TBM | OPTION_MASK_ISA_64BIT, 0, CODE_FOR_nothing, "__builtin_ia32_bextri_u64", IX86_BUILTIN_BEXTRI64, UNKNOWN, (int) UINT64_FTYPE_UINT64_UINT64)
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/* F16C */
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BDESC (OPTION_MASK_ISA_F16C, 0, CODE_FOR_vcvtph2ps, "__builtin_ia32_vcvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int) V4SF_FTYPE_V8HI)
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@ -11709,24 +11709,26 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
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case IX86_BUILTIN_BEXTRI32:
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case IX86_BUILTIN_BEXTRI64:
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mode = (fcode == IX86_BUILTIN_BEXTRI32 ? SImode : DImode);
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arg0 = CALL_EXPR_ARG (exp, 0);
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arg1 = CALL_EXPR_ARG (exp, 1);
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op0 = expand_normal (arg0);
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op1 = expand_normal (arg1);
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icode = (fcode == IX86_BUILTIN_BEXTRI32
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? CODE_FOR_tbm_bextri_si
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: CODE_FOR_tbm_bextri_di);
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if (!CONST_INT_P (op1))
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{
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error ("last argument must be an immediate");
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return const0_rtx;
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}
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{
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error ("last argument must be an immediate");
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return const0_rtx;
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}
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else
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{
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unsigned char length = (INTVAL (op1) >> 8) & 0xFF;
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unsigned char lsb_index = INTVAL (op1) & 0xFF;
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op1 = GEN_INT (length);
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op2 = GEN_INT (lsb_index);
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{
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unsigned char lsb_index = UINTVAL (op1);
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unsigned char length = UINTVAL (op1) >> 8;
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unsigned char bitsize = GET_MODE_BITSIZE (mode);
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icode = code_for_tbm_bextri (mode);
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mode1 = insn_data[icode].operand[1].mode;
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if (!insn_data[icode].operand[1].predicate (op0, mode1))
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@ -11737,25 +11739,32 @@ ix86_expand_builtin (tree exp, rtx target, rtx subtarget,
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|| !register_operand (target, mode0))
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target = gen_reg_rtx (mode0);
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pat = GEN_FCN (icode) (target, op0, op1, op2);
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if (pat)
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emit_insn (pat);
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return target;
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}
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if (length == 0 || lsb_index >= bitsize)
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{
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emit_move_insn (target, const0_rtx);
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return target;
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}
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if (length + lsb_index > bitsize)
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length = bitsize - lsb_index;
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op1 = GEN_INT (length);
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op2 = GEN_INT (lsb_index);
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emit_insn (GEN_FCN (icode) (target, op0, op1, op2));
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return target;
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}
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case IX86_BUILTIN_RDRAND16_STEP:
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icode = CODE_FOR_rdrandhi_1;
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mode0 = HImode;
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mode = HImode;
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goto rdrand_step;
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case IX86_BUILTIN_RDRAND32_STEP:
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icode = CODE_FOR_rdrandsi_1;
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mode0 = SImode;
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mode = SImode;
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goto rdrand_step;
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case IX86_BUILTIN_RDRAND64_STEP:
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icode = CODE_FOR_rdranddi_1;
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mode0 = DImode;
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mode = DImode;
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rdrand_step:
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arg0 = CALL_EXPR_ARG (exp, 0);
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@ -11766,16 +11775,15 @@ rdrand_step:
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op1 = copy_addr_to_reg (op1);
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}
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op0 = gen_reg_rtx (mode0);
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emit_insn (GEN_FCN (icode) (op0));
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op0 = gen_reg_rtx (mode);
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emit_insn (gen_rdrand (mode, op0));
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emit_move_insn (gen_rtx_MEM (mode0, op1), op0);
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emit_move_insn (gen_rtx_MEM (mode, op1), op0);
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op1 = gen_reg_rtx (SImode);
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emit_move_insn (op1, CONST1_RTX (SImode));
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op1 = force_reg (SImode, const1_rtx);
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/* Emit SImode conditional move. */
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if (mode0 == HImode)
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if (mode == HImode)
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{
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if (TARGET_ZERO_EXTEND_WITH_AND
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&& optimize_function_for_speed_p (cfun))
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@ -11792,7 +11800,7 @@ rdrand_step:
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emit_insn (gen_zero_extendhisi2 (op2, op0));
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}
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}
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else if (mode0 == SImode)
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else if (mode == SImode)
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op2 = op0;
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else
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op2 = gen_rtx_SUBREG (SImode, op0, 0);
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@ -11808,18 +11816,15 @@ rdrand_step:
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return target;
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case IX86_BUILTIN_RDSEED16_STEP:
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icode = CODE_FOR_rdseedhi_1;
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mode0 = HImode;
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mode = HImode;
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goto rdseed_step;
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case IX86_BUILTIN_RDSEED32_STEP:
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icode = CODE_FOR_rdseedsi_1;
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mode0 = SImode;
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mode = SImode;
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goto rdseed_step;
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case IX86_BUILTIN_RDSEED64_STEP:
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icode = CODE_FOR_rdseeddi_1;
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mode0 = DImode;
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mode = DImode;
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rdseed_step:
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arg0 = CALL_EXPR_ARG (exp, 0);
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@ -11830,10 +11835,10 @@ rdseed_step:
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op1 = copy_addr_to_reg (op1);
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}
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op0 = gen_reg_rtx (mode0);
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emit_insn (GEN_FCN (icode) (op0));
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op0 = gen_reg_rtx (mode);
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emit_insn (gen_rdseed (mode, op0));
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emit_move_insn (gen_rtx_MEM (mode0, op1), op0);
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emit_move_insn (gen_rtx_MEM (mode, op1), op0);
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op2 = gen_reg_rtx (QImode);
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@ -14524,28 +14524,7 @@
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(set_attr "mode" "<MODE>")])
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;; TBM instructions.
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(define_expand "tbm_bextri_<mode>"
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[(parallel
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[(set (match_operand:SWI48 0 "register_operand")
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(zero_extract:SWI48
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(match_operand:SWI48 1 "nonimmediate_operand")
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(match_operand 2 "const_0_to_255_operand" "N")
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(match_operand 3 "const_0_to_255_operand" "N")))
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(clobber (reg:CC FLAGS_REG))])]
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"TARGET_TBM"
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{
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if (operands[2] == const0_rtx
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|| INTVAL (operands[3]) >= <MODE_SIZE> * BITS_PER_UNIT)
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{
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emit_move_insn (operands[0], const0_rtx);
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DONE;
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}
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if (INTVAL (operands[2]) + INTVAL (operands[3])
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> <MODE_SIZE> * BITS_PER_UNIT)
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operands[2] = GEN_INT (<MODE_SIZE> * BITS_PER_UNIT - INTVAL (operands[3]));
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})
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(define_insn "*tbm_bextri_<mode>"
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(define_insn "@tbm_bextri_<mode>"
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[(set (match_operand:SWI48 0 "register_operand" "=r")
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(zero_extract:SWI48
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(match_operand:SWI48 1 "nonimmediate_operand" "rm")
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@ -21174,7 +21153,7 @@
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[(set_attr "type" "other")
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(set_attr "prefix_extra" "2")])
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(define_insn "rdrand<mode>_1"
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(define_insn "@rdrand<mode>"
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[(set (match_operand:SWI248 0 "register_operand" "=r")
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(unspec_volatile:SWI248 [(const_int 0)] UNSPECV_RDRAND))
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(set (reg:CCC FLAGS_REG)
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@ -21184,7 +21163,7 @@
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[(set_attr "type" "other")
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(set_attr "prefix_extra" "1")])
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(define_insn "rdseed<mode>_1"
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(define_insn "@rdseed<mode>"
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[(set (match_operand:SWI248 0 "register_operand" "=r")
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(unspec_volatile:SWI248 [(const_int 0)] UNSPECV_RDSEED))
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(set (reg:CCC FLAGS_REG)
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@ -1,6 +1,6 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -mrdrnd -dp" } */
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/* { dg-final { scan-assembler-times "rdrandhi_1" 1 } } */
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/* { dg-final { scan-assembler-times "rdrandhi" 1 } } */
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/* { dg-final { scan-assembler-times "\\*movsicc_noc" 1 } } */
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#include <immintrin.h>
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@ -1,6 +1,6 @@
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/* { dg-do compile } */
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/* { dg-options "-O2 -mrdrnd -dp" } */
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/* { dg-final { scan-assembler-times "rdrandsi_1" 1 } } */
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/* { dg-final { scan-assembler-times "rdrandsi" 1 } } */
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/* { dg-final { scan-assembler-times "\\*movsicc_noc" 1 } } */
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#include <immintrin.h>
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@ -1,6 +1,6 @@
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/* { dg-do compile { target { ! ia32 } } } */
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/* { dg-options "-O2 -mrdrnd -dp" } */
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/* { dg-final { scan-assembler-times "rdranddi_1" 1 } } */
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/* { dg-final { scan-assembler-times "rdranddi" 1 } } */
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/* { dg-final { scan-assembler-times "\\*movsicc_noc" 1 } } */
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#include <immintrin.h>
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