rs6000.md (neg-minus-mult): Set type to dmul.
2005-09-23 David Edelsohn <edelsohn@gnu.org> Pete Steinmetz <steinmtz@us.ibm.com> * config/rs6000/rs6000.md (neg-minus-mult): Set type to dmul. (rldic.): Set type to "compare". (rldicr.): Same. (movsf_hardfloat): Set type to mtjmpr for MTCTR/MTLR. Set type to mfjmpr for MFCTR/MFLR. (movdf_hardfloat64): Same. (movdf_softfloat64): Same. Correct order of store and move types. (movti_string): Set type to store_ux/load_ux. (load_multiple): Set type to load_ux. (store_multiple): Set type to store_ux. (movmemsi): Set type to store_ux. (output_cbranch direct_return): Set type to jmpreg. (stmw): Set type to store_ux. (lmw): Set type to load_ux. * config/rs6000/40x.md (ppc403-store): Increase latency to 2. * config/rs6000/440.md (ppc440-store): Increase latency to 6. * config/rs6000/603.md (ppc603-store): Occupy LSU for 2 cycles. * config/rs6000/6xx.md (ppc604-store): Increase latency to 3. * config/rs6000/mpc.md (mpccore-store): Increase latency to 2. * config/rs6000/rios1.md (rios1-store): Increase latency to 2. (rios1-fpstore): Increase latency to 3. * config/rs6000/rios2.md (rios2-store): Increase latency to 2. * config/rs6000/rs64.md (rs64a-store): Increase latency to 2. Co-Authored-By: Pete Steinmetz <steinmtz@us.ibm.com> From-SVN: r104568
This commit is contained in:
David Edelsohn
David Edelsohn
parent
66684b7e9b
commit
9c6fdb4671
10 changed files with 77 additions and 48 deletions
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@ -1,3 +1,30 @@
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2005-09-23 David Edelsohn <edelsohn@gnu.org>
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Pete Steinmetz <steinmtz@us.ibm.com>
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* config/rs6000/rs6000.md (neg-minus-mult): Set type to dmul.
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(rldic.): Set type to "compare".
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(rldicr.): Same.
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(movsf_hardfloat): Set type to mtjmpr for MTCTR/MTLR. Set type to
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mfjmpr for MFCTR/MFLR.
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(movdf_hardfloat64): Same.
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(movdf_softfloat64): Same. Correct order of store and move types.
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(movti_string): Set type to store_ux/load_ux.
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(load_multiple): Set type to load_ux.
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(store_multiple): Set type to store_ux.
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(movmemsi): Set type to store_ux.
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(output_cbranch direct_return): Set type to jmpreg.
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(stmw): Set type to store_ux.
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(lmw): Set type to load_ux.
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* config/rs6000/40x.md (ppc403-store): Increase latency to 2.
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* config/rs6000/440.md (ppc440-store): Increase latency to 6.
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* config/rs6000/603.md (ppc603-store): Occupy LSU for 2 cycles.
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* config/rs6000/6xx.md (ppc604-store): Increase latency to 3.
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* config/rs6000/mpc.md (mpccore-store): Increase latency to 2.
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* config/rs6000/rios1.md (rios1-store): Increase latency to 2.
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(rios1-fpstore): Increase latency to 3.
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* config/rs6000/rios2.md (rios2-store): Increase latency to 2.
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* config/rs6000/rs64.md (rs64a-store): Increase latency to 2.
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2005-09-23 David Edelsohn <edelsohn@gnu.org>
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Andrew Pinski <pinskia@physics.uc.edu>
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@ -32,7 +32,7 @@
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(eq_attr "cpu" "ppc403,ppc405"))
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"iu_40x")
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(define_insn_reservation "ppc403-store" 1
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(define_insn_reservation "ppc403-store" 2
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(and (eq_attr "type" "store,store_ux,store_u")
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(eq_attr "cpu" "ppc403,ppc405"))
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"iu_40x")
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@ -39,7 +39,7 @@
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(eq_attr "cpu" "ppc440"))
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"ppc440_issue,ppc440_l_pipe")
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(define_insn_reservation "ppc440-store" 1
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(define_insn_reservation "ppc440-store" 3
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(and (eq_attr "type" "store,store_ux,store_u")
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(eq_attr "cpu" "ppc440"))
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"ppc440_issue,ppc440_l_pipe")
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@ -46,7 +46,7 @@
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(define_insn_reservation "ppc603-store" 2
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(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
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(eq_attr "cpu" "ppc603"))
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"lsu_603")
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"lsu_603*2")
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(define_insn_reservation "ppc603-fpload" 2
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(and (eq_attr "type" "fpload,fpload_ux,fpload_u")
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@ -58,7 +58,7 @@
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(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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"lsu_6xx")
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(define_insn_reservation "ppc604-store" 1
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(define_insn_reservation "ppc604-store" 3
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(and (eq_attr "type" "store,fpstore,store_ux,store_u,fpstore_ux,fpstore_u")
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(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
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"lsu_6xx")
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@ -32,7 +32,7 @@
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(eq_attr "cpu" "mpccore"))
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"lsu_mpc")
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(define_insn_reservation "mpccore-store" 1
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(define_insn_reservation "mpccore-store" 2
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(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
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(eq_attr "cpu" "mpccore"))
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"lsu_mpc")
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@ -31,7 +31,7 @@
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(eq_attr "cpu" "rios1,ppc601"))
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"iu_rios1")
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(define_insn_reservation "rios1-store" 1
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(define_insn_reservation "rios1-store" 2
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(and (eq_attr "type" "store,store_ux,store_u")
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(eq_attr "cpu" "rios1,ppc601"))
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"iu_rios1")
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@ -46,7 +46,7 @@
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(eq_attr "cpu" "ppc601"))
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"iu_rios1")
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(define_insn_reservation "rios1-fpstore" 1
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(define_insn_reservation "rios1-fpstore" 3
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(and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u")
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(eq_attr "cpu" "rios1,ppc601"))
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"iu_rios1+fpu_rios1")
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@ -34,7 +34,7 @@
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(eq_attr "cpu" "rios2"))
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"iu1_rios2|iu2_rios2")
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(define_insn_reservation "rios2-store" 1
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(define_insn_reservation "rios2-store" 2
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(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
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(eq_attr "cpu" "rios2"))
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"iu1_rios2|iu2_rios2")
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@ -4669,7 +4669,7 @@
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"! TARGET_POWERPC && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_FUSED_MADD
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&& ! HONOR_SIGNED_ZEROS (SFmode)"
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"{fnms|fnmsub} %0,%1,%2,%3"
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[(set_attr "type" "fp")])
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[(set_attr "type" "dmul")])
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(define_expand "sqrtsf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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@ -6382,7 +6382,7 @@
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"@
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rldic. %4,%1,%H2,%W3
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#"
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[(set_attr "type" "delayed_compare")
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[(set_attr "type" "compare")
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(set_attr "length" "4,8")])
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(define_split
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@ -6416,7 +6416,7 @@
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"@
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rldic. %0,%1,%H2,%W3
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#"
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[(set_attr "type" "delayed_compare")
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[(set_attr "type" "compare")
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(set_attr "length" "4,8")])
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(define_split
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@ -6458,7 +6458,7 @@
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"@
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rldicr. %4,%1,%H2,%S3
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#"
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[(set_attr "type" "delayed_compare")
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[(set_attr "type" "compare")
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(set_attr "length" "4,8")])
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(define_split
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@ -6492,7 +6492,7 @@
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"@
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rldicr. %0,%1,%H2,%S3
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#"
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[(set_attr "type" "delayed_compare")
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[(set_attr "type" "compare")
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(set_attr "length" "4,8")])
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(define_split
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@ -6740,7 +6740,7 @@
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#
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#
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#"
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[(set_attr "type" "compare,delayed_compare,delayed_compare,compare,compare,delayed_compare,delayed_compare,compare,compare,compare,compare,compare")
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[(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
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(set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
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(define_split
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@ -6791,7 +6791,7 @@
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#
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#
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#"
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[(set_attr "type" "compare,delayed_compare,delayed_compare,compare,compare,delayed_compare,delayed_compare,compare,compare,compare,compare,compare")
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[(set_attr "type" "compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare,compare")
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(set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")])
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(define_split
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@ -7418,7 +7418,7 @@
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{cror 0,0,0|nop}
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#
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#"
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[(set_attr "type" "*,load,store,fp,fpload,fpstore,*,mtjmpr,*,*,*,*")
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[(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,mfjmpr,*,*,*")
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(set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,8")])
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(define_insn "*movsf_softfloat"
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@ -7440,7 +7440,7 @@
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#
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#
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{cror 0,0,0|nop}"
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[(set_attr "type" "*,mtjmpr,*,*,load,store,*,*,*,*,*,*")
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[(set_attr "type" "*,mtjmpr,*,mfjmpr,load,store,*,*,*,*,*,*")
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(set_attr "length" "4,4,4,4,4,4,4,4,4,4,8,4")])
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@ -7700,7 +7700,7 @@
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#
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#
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#"
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[(set_attr "type" "*,load,store,fp,fpload,fpstore,mtjmpr,*,*,*,*,*")
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[(set_attr "type" "store,load,*,fp,fpload,fpstore,mtjmpr,mfjmpr,*,*,*,*")
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(set_attr "length" "4,4,4,4,4,4,4,4,4,8,12,16")])
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(define_insn "*movdf_softfloat64"
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@ -7719,7 +7719,7 @@
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#
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#
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{cror 0,0,0|nop}"
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[(set_attr "type" "load,store,*,*,*,*,*,*,*")
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[(set_attr "type" "load,store,*,mtjmpr,mfjmpr,*,*,*,*")
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(set_attr "length" "4,4,4,4,4,8,12,16,4")])
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(define_expand "movtf"
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@ -8153,7 +8153,7 @@
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return \"#\";
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}
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}"
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[(set_attr "type" "store,store,*,load,load,*")])
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[(set_attr "type" "store_ux,store_ux,*,load_ux,load_ux,*")])
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(define_insn "*movti_ppc64"
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[(set (match_operand:TI 0 "nonimmediate_operand" "=r,o<>,r")
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@ -8254,7 +8254,7 @@
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"TARGET_STRING && XVECLEN (operands[0], 0) == 8"
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"*
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{ return rs6000_output_load_multiple (operands); }"
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[(set_attr "type" "load")
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[(set_attr "type" "load_ux")
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(set_attr "length" "32")])
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(define_insn "*ldmsi7"
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@ -8276,7 +8276,7 @@
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"TARGET_STRING && XVECLEN (operands[0], 0) == 7"
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"*
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{ return rs6000_output_load_multiple (operands); }"
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[(set_attr "type" "load")
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[(set_attr "type" "load_ux")
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(set_attr "length" "32")])
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(define_insn "*ldmsi6"
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@ -8296,7 +8296,7 @@
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"TARGET_STRING && XVECLEN (operands[0], 0) == 6"
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"*
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{ return rs6000_output_load_multiple (operands); }"
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[(set_attr "type" "load")
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[(set_attr "type" "load_ux")
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(set_attr "length" "32")])
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(define_insn "*ldmsi5"
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@ -8314,7 +8314,7 @@
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"TARGET_STRING && XVECLEN (operands[0], 0) == 5"
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"*
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{ return rs6000_output_load_multiple (operands); }"
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[(set_attr "type" "load")
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[(set_attr "type" "load_ux")
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(set_attr "length" "32")])
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(define_insn "*ldmsi4"
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@ -8330,7 +8330,7 @@
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"TARGET_STRING && XVECLEN (operands[0], 0) == 4"
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"*
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{ return rs6000_output_load_multiple (operands); }"
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[(set_attr "type" "load")
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[(set_attr "type" "load_ux")
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(set_attr "length" "32")])
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(define_insn "*ldmsi3"
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@ -8344,7 +8344,7 @@
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"TARGET_STRING && XVECLEN (operands[0], 0) == 3"
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"*
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{ return rs6000_output_load_multiple (operands); }"
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[(set_attr "type" "load")
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[(set_attr "type" "load_ux")
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(set_attr "length" "32")])
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(define_expand "store_multiple"
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@ -8421,7 +8421,7 @@
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(match_operand:SI 10 "gpc_reg_operand" "r"))])]
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"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 9"
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"{stsi|stswi} %2,%1,%O0"
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[(set_attr "type" "store")])
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[(set_attr "type" "store_ux")])
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(define_insn "*stmsi7"
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[(match_parallel 0 "store_multiple_operation"
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@ -8442,7 +8442,7 @@
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(match_operand:SI 9 "gpc_reg_operand" "r"))])]
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"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 8"
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"{stsi|stswi} %2,%1,%O0"
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[(set_attr "type" "store")])
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[(set_attr "type" "store_ux")])
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(define_insn "*stmsi6"
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[(match_parallel 0 "store_multiple_operation"
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@ -8461,7 +8461,7 @@
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(match_operand:SI 8 "gpc_reg_operand" "r"))])]
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"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 7"
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"{stsi|stswi} %2,%1,%O0"
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[(set_attr "type" "store")])
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[(set_attr "type" "store_ux")])
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(define_insn "*stmsi5"
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[(match_parallel 0 "store_multiple_operation"
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@ -8478,7 +8478,7 @@
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(match_operand:SI 7 "gpc_reg_operand" "r"))])]
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"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 6"
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"{stsi|stswi} %2,%1,%O0"
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[(set_attr "type" "store")])
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[(set_attr "type" "store_ux")])
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(define_insn "*stmsi4"
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[(match_parallel 0 "store_multiple_operation"
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@ -8493,7 +8493,7 @@
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(match_operand:SI 6 "gpc_reg_operand" "r"))])]
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"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 5"
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"{stsi|stswi} %2,%1,%O0"
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[(set_attr "type" "store")])
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[(set_attr "type" "store_ux")])
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(define_insn "*stmsi3"
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[(match_parallel 0 "store_multiple_operation"
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@ -8506,7 +8506,7 @@
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(match_operand:SI 5 "gpc_reg_operand" "r"))])]
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"TARGET_STRING && !TARGET_POWER && XVECLEN (operands[0], 0) == 4"
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"{stsi|stswi} %2,%1,%O0"
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[(set_attr "type" "store")])
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[(set_attr "type" "store_ux")])
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(define_expand "setmemsi"
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[(parallel [(set (match_operand:BLK 0 "" "")
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@ -8587,7 +8587,7 @@
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&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
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&& REGNO (operands[4]) == 5"
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"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
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[(set_attr "type" "load")
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[(set_attr "type" "store_ux")
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(set_attr "length" "8")])
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(define_insn ""
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@ -8611,7 +8611,7 @@
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&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12)
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&& REGNO (operands[4]) == 5"
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"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
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[(set_attr "type" "load")
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[(set_attr "type" "store_ux")
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(set_attr "length" "8")])
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;; Move up to 24 bytes at a time. The fixed registers are needed because the
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@ -8650,7 +8650,7 @@
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&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
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&& REGNO (operands[4]) == 5"
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"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
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[(set_attr "type" "load")
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[(set_attr "type" "store_ux")
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(set_attr "length" "8")])
|
||||
|
||||
(define_insn ""
|
||||
|
|
@ -8671,7 +8671,7 @@
|
|||
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10)
|
||||
&& REGNO (operands[4]) == 5"
|
||||
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
|
||||
[(set_attr "type" "load")
|
||||
[(set_attr "type" "store_ux")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill
|
||||
|
|
@ -8706,7 +8706,7 @@
|
|||
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
|
||||
&& REGNO (operands[4]) == 5"
|
||||
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
|
||||
[(set_attr "type" "load")
|
||||
[(set_attr "type" "store_ux")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_insn ""
|
||||
|
|
@ -8725,7 +8725,7 @@
|
|||
&& (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8)
|
||||
&& REGNO (operands[4]) == 5"
|
||||
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
|
||||
[(set_attr "type" "load")
|
||||
[(set_attr "type" "store_ux")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
;; Move up to 8 bytes at a time.
|
||||
|
|
@ -8749,7 +8749,7 @@
|
|||
"TARGET_STRING && TARGET_POWER && ! TARGET_POWERPC64
|
||||
&& INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
|
||||
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
|
||||
[(set_attr "type" "load")
|
||||
[(set_attr "type" "store_ux")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_insn ""
|
||||
|
|
@ -8762,7 +8762,7 @@
|
|||
"TARGET_STRING && ! TARGET_POWER && ! TARGET_POWERPC64
|
||||
&& INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8"
|
||||
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
|
||||
[(set_attr "type" "load")
|
||||
[(set_attr "type" "store_ux")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
;; Move up to 4 bytes at a time.
|
||||
|
|
@ -8786,7 +8786,7 @@
|
|||
"TARGET_STRING && TARGET_POWER
|
||||
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
|
||||
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
|
||||
[(set_attr "type" "load")
|
||||
[(set_attr "type" "store_ux")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
(define_insn ""
|
||||
|
|
@ -8799,7 +8799,7 @@
|
|||
"TARGET_STRING && ! TARGET_POWER
|
||||
&& INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4"
|
||||
"{lsi|lswi} %4,%1,%2\;{stsi|stswi} %4,%0,%2"
|
||||
[(set_attr "type" "load")
|
||||
[(set_attr "type" "store_ux")
|
||||
(set_attr "length" "8")])
|
||||
|
||||
;; Define insns that do load or store with update. Some of these we can
|
||||
|
|
@ -12825,7 +12825,7 @@
|
|||
{
|
||||
return output_cbranch (operands[0], NULL, 0, insn);
|
||||
}"
|
||||
[(set_attr "type" "branch")
|
||||
[(set_attr "type" "jmpreg")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
(define_insn ""
|
||||
|
|
@ -12856,7 +12856,7 @@
|
|||
{
|
||||
return output_cbranch (operands[0], NULL, 1, insn);
|
||||
}"
|
||||
[(set_attr "type" "branch")
|
||||
[(set_attr "type" "jmpreg")
|
||||
(set_attr "length" "4")])
|
||||
|
||||
;; Logic on condition register values.
|
||||
|
|
@ -13327,7 +13327,8 @@
|
|||
[(set (match_operand:SI 1 "memory_operand" "=m")
|
||||
(match_operand:SI 2 "gpc_reg_operand" "r"))])]
|
||||
"TARGET_MULTIPLE"
|
||||
"{stm|stmw} %2,%1")
|
||||
"{stm|stmw} %2,%1"
|
||||
[(set_attr "type" "store_ux")])
|
||||
|
||||
(define_insn "*save_fpregs_<mode>"
|
||||
[(match_parallel 0 "any_parallel_operand"
|
||||
|
|
@ -13402,14 +13403,15 @@
|
|||
|
||||
; The load-multiple instructions have similar properties.
|
||||
; Note that "load_multiple" is a name known to the machine-independent
|
||||
; code that actually corresponds to the powerpc load-string.
|
||||
; code that actually corresponds to the PowerPC load-string.
|
||||
|
||||
(define_insn "*lmw"
|
||||
[(match_parallel 0 "lmw_operation"
|
||||
[(set (match_operand:SI 1 "gpc_reg_operand" "=r")
|
||||
(match_operand:SI 2 "memory_operand" "m"))])]
|
||||
"TARGET_MULTIPLE"
|
||||
"{lm|lmw} %1,%2")
|
||||
"{lm|lmw} %1,%2"
|
||||
[(set_attr "type" "load_ux")])
|
||||
|
||||
(define_insn "*return_internal_<mode>"
|
||||
[(return)
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
(eq_attr "cpu" "rs64a"))
|
||||
"lsu_rs64")
|
||||
|
||||
(define_insn_reservation "rs64a-store" 1
|
||||
(define_insn_reservation "rs64a-store" 2
|
||||
(and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u")
|
||||
(eq_attr "cpu" "rs64a"))
|
||||
"lsu_rs64")
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue