[Patch AArch64] Add initial tuning support for Cortex-A55 and Cortex-A75
This patch adds support for the ARM Cortex-A75 and Cortex-A55 processors through the -mcpu/-mtune values cortex-a55 and cortex-a75, and an ARM DynamIQ big.LITTLE configuration of these two processors through the -mcpu/-mtune value cortex-a75.cortex-a55 The ARM Cortex-A75 is ARM's latest and highest performance applications processor. For the initial tuning provided in this patch, I have chosen to share the tuning structure with its predecessor, the Cortex-A73. The ARM Cortex-A55 delivers the best combination of power efficiency and performance in its class. For the initial tuning provided in this patch, I have chosen to share the tuning structure with its predecessor, the Cortex-A53. Both Cortex-A55 and Cortex-A75 support ARMv8-A with the ARM8.1-A and ARMv8.2-A extensions, along with the cryptography extension, and the RCPC extensions from ARMv8.3-A. This is reflected in the patch, -mcpu=cortex-a75 is treated as equivalent to passing -mtune=cortex-a75 -march=armv8.2-a+rcpc . 2017-06-21 James Greenhalgh <james.greenhalgh@arm.com> * config/aarch64/aarch64-cores.def (cortex-a55): New. (cortex-a75): Likewise. (cortex-a75.cortex-a55): Likewise. * config/aarch64/aarch64-tune.md: Regenerate. * doc/invoke.texi (-mtune): Document new values for -mtune. From-SVN: r249441
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James Greenhalgh
James Greenhalgh
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4 changed files with 27 additions and 7 deletions
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@ -1,3 +1,11 @@
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2017-06-21 James Greenhalgh <james.greenhalgh@arm.com>
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* config/aarch64/aarch64-cores.def (cortex-a55): New.
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(cortex-a75): Likewise.
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(cortex-a75.cortex-a55): Likewise.
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* config/aarch64/aarch64-tune.md: Regenerate.
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* doc/invoke.texi (-mtune): Document new values for -mtune.
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2017-06-21 Tom de Vries <tom@codesourcery.com>
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* doc/sourcebuild.texi (Add Options, Features for dg-add-options): Add
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@ -80,6 +80,12 @@ AARCH64_CORE("vulcan", vulcan, thunderx2t99, 8_1A, AARCH64_FL_FOR_ARCH8_1 | AA
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/* Cavium ('C') cores. */
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AARCH64_CORE("thunderx2t99", thunderx2t99, thunderx2t99, 8_1A, AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_CRYPTO, thunderx2t99, 0x43, 0x0af, -1)
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/* ARMv8.2-A Architecture Processors. */
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/* ARM ('A') cores. */
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AARCH64_CORE("cortex-a55", cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC, cortexa53, 0x41, 0xd05, -1)
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AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC, cortexa73, 0x41, 0xd0a, -1)
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/* ARMv8-A big.LITTLE implementations. */
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AARCH64_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, 0x41, AARCH64_BIG_LITTLE (0xd07, 0xd03), -1)
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@ -87,4 +93,8 @@ AARCH64_CORE("cortex-a72.cortex-a53", cortexa72cortexa53, cortexa53, 8A, AARCH
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AARCH64_CORE("cortex-a73.cortex-a35", cortexa73cortexa35, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd09, 0xd04), -1)
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AARCH64_CORE("cortex-a73.cortex-a53", cortexa73cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd09, 0xd03), -1)
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/* ARM DynamIQ big.LITTLE configurations. */
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AARCH64_CORE("cortex-a75.cortex-a55", cortexa75cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC, cortexa73, 0x41, AARCH64_BIG_LITTLE (0xd0a, 0xd05), -1)
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#undef AARCH64_CORE
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@ -1,5 +1,5 @@
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;; -*- buffer-read-only: t -*-
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;; Generated automatically by gentune.sh from aarch64-cores.def
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(define_attr "tune"
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"cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53"
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"cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55"
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(const (symbol_ref "((enum attr_tune) aarch64_tune)")))
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@ -14077,17 +14077,19 @@ processors implementing the target architecture.
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@opindex mtune
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Specify the name of the target processor for which GCC should tune the
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performance of the code. Permissible values for this option are:
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@samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57},
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@samp{cortex-a72}, @samp{cortex-a73}, @samp{exynos-m1},
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@samp{xgene1}, @samp{vulcan}, @samp{thunderx},
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@samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55},
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@samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75},
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@samp{exynos-m1}, @samp{xgene1}, @samp{vulcan}, @samp{thunderx},
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@samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81},
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@samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53},
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@samp{cortex-a72.cortex-a53}, @samp{cortex-a73.cortex-a35},
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@samp{cortex-a73.cortex-a53}, @samp{native}.
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@samp{cortex-a73.cortex-a53}, @samp{cortex-a75.cortex-a55},
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@samp{native}.
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The values @samp{cortex-a57.cortex-a53}, @samp{cortex-a72.cortex-a53},
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@samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53}
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specify that GCC should tune for a big.LITTLE system.
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@samp{cortex-a73.cortex-a35}, @samp{cortex-a73.cortex-a53},
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@samp{cortex-a75.cortex-a55} specify that GCC should tune for a
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big.LITTLE system.
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Additionally on native AArch64 GNU/Linux systems the value
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@samp{native} tunes performance to the host system. This option has no effect
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