RISC-V: Add instruction fusion (for ventana-vt1)
The Ventana VT1 core supports quad-issue and instruction fusion. This implemented TARGET_SCHED_MACRO_FUSION_P to keep fusible sequences together and adds idiom matcheing for the supported fusion cases. gcc/ChangeLog: * config/riscv/riscv.cc (enum riscv_fusion_pairs): Add symbolic constants to identify supported fusion patterns. (struct riscv_tune_param): Add fusible_op field. (riscv_macro_fusion_p): Implement. (riscv_fusion_enabled_p): Implement. (riscv_macro_fusion_pair_p): Implement and recognize fusible idioms for Ventana VT1. (TARGET_SCHED_MACRO_FUSION_P): Point to riscv_macro_fusion_p. (TARGET_SCHED_MACRO_FUSION_PAIR_P): Point to riscv_macro_fusion_pair_p.
This commit is contained in:
Philipp Tomsich
parent
b4fca4fc70
commit
991cfe5b30
1 changed files with 220 additions and 0 deletions
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@ -215,6 +215,19 @@ struct riscv_integer_op {
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The worst case is LUI, ADDI, SLLI, ADDI, SLLI, ADDI, SLLI, ADDI. */
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#define RISCV_MAX_INTEGER_OPS 8
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enum riscv_fusion_pairs
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{
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RISCV_FUSE_NOTHING = 0,
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RISCV_FUSE_ZEXTW = (1 << 0),
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RISCV_FUSE_ZEXTH = (1 << 1),
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RISCV_FUSE_ZEXTWS = (1 << 2),
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RISCV_FUSE_LDINDEXED = (1 << 3),
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RISCV_FUSE_LUI_ADDI = (1 << 4),
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RISCV_FUSE_AUIPC_ADDI = (1 << 5),
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RISCV_FUSE_LUI_LD = (1 << 6),
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RISCV_FUSE_AUIPC_LD = (1 << 7),
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};
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/* Costs of various operations on the different architectures. */
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struct riscv_tune_param
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@ -229,6 +242,7 @@ struct riscv_tune_param
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unsigned short memory_cost;
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unsigned short fmv_cost;
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bool slow_unaligned_access;
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unsigned int fusible_ops;
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};
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/* Information about one micro-arch we know about. */
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@ -316,6 +330,7 @@ static const struct riscv_tune_param rocket_tune_info = {
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5, /* memory_cost */
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8, /* fmv_cost */
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true, /* slow_unaligned_access */
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RISCV_FUSE_NOTHING, /* fusible_ops */
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};
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/* Costs to use when optimizing for Sifive 7 Series. */
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@ -330,6 +345,7 @@ static const struct riscv_tune_param sifive_7_tune_info = {
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3, /* memory_cost */
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8, /* fmv_cost */
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true, /* slow_unaligned_access */
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RISCV_FUSE_NOTHING, /* fusible_ops */
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};
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/* Costs to use when optimizing for T-HEAD c906. */
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@ -344,6 +360,7 @@ static const struct riscv_tune_param thead_c906_tune_info = {
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5, /* memory_cost */
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8, /* fmv_cost */
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false, /* slow_unaligned_access */
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RISCV_FUSE_NOTHING, /* fusible_ops */
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};
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/* Costs to use when optimizing for size. */
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@ -358,6 +375,7 @@ static const struct riscv_tune_param optimize_size_tune_info = {
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2, /* memory_cost */
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8, /* fmv_cost */
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false, /* slow_unaligned_access */
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RISCV_FUSE_NOTHING, /* fusible_ops */
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};
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/* Costs to use when optimizing for Ventana Micro VT1. */
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@ -372,6 +390,10 @@ static const struct riscv_tune_param ventana_vt1_tune_info = {
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5, /* memory_cost */
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8, /* fmv_cost */
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false, /* slow_unaligned_access */
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( RISCV_FUSE_ZEXTW | RISCV_FUSE_ZEXTH | /* fusible_ops */
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RISCV_FUSE_ZEXTWS | RISCV_FUSE_LDINDEXED |
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RISCV_FUSE_LUI_ADDI | RISCV_FUSE_AUIPC_ADDI |
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RISCV_FUSE_LUI_LD | RISCV_FUSE_AUIPC_LD )
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};
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static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *);
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@ -5611,6 +5633,200 @@ riscv_issue_rate (void)
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return tune_param->issue_rate;
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}
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/* Implement TARGET_SCHED_MACRO_FUSION_P. Return true if target supports
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instruction fusion of some sort. */
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static bool
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riscv_macro_fusion_p (void)
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{
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return tune_param->fusible_ops != RISCV_FUSE_NOTHING;
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}
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/* Return true iff the instruction fusion described by OP is enabled. */
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static bool
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riscv_fusion_enabled_p(enum riscv_fusion_pairs op)
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{
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return tune_param->fusible_ops & op;
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}
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/* Implement TARGET_SCHED_MACRO_FUSION_PAIR_P. Return true if PREV and CURR
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should be kept together during scheduling. */
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static bool
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riscv_macro_fusion_pair_p (rtx_insn *prev, rtx_insn *curr)
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{
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rtx prev_set = single_set (prev);
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rtx curr_set = single_set (curr);
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/* prev and curr are simple SET insns i.e. no flag setting or branching. */
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bool simple_sets_p = prev_set && curr_set && !any_condjump_p (curr);
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if (!riscv_macro_fusion_p ())
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return false;
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if (simple_sets_p
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&& (riscv_fusion_enabled_p (RISCV_FUSE_ZEXTW)
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|| riscv_fusion_enabled_p (RISCV_FUSE_ZEXTH)))
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{
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/* We are trying to match the following:
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prev (slli) == (set (reg:DI rD)
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(ashift:DI (reg:DI rS) (const_int 32)))
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curr (slri) == (set (reg:DI rD)
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(lshiftrt:DI (reg:DI rD) (const_int <shift>)))
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with <shift> being either 32 for FUSE_ZEXTW, or
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less than 32 for FUSE_ZEXTWS. */
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if (GET_CODE (SET_SRC (prev_set)) == ASHIFT
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&& GET_CODE (SET_SRC (curr_set)) == LSHIFTRT
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&& REG_P (SET_DEST (prev_set))
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&& REG_P (SET_DEST (curr_set))
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&& REGNO (SET_DEST (prev_set)) == REGNO (SET_DEST (curr_set))
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&& REGNO (XEXP (SET_SRC (curr_set), 0)) == REGNO (SET_DEST (curr_set))
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&& CONST_INT_P (XEXP (SET_SRC (prev_set), 1))
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&& CONST_INT_P (XEXP (SET_SRC (curr_set), 1))
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&& INTVAL (XEXP (SET_SRC (prev_set), 1)) == 32
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&& ((INTVAL (XEXP (SET_SRC (curr_set), 1)) == 32
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&& riscv_fusion_enabled_p (RISCV_FUSE_ZEXTW))
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|| (INTVAL (XEXP (SET_SRC (curr_set), 1)) < 32
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&& riscv_fusion_enabled_p (RISCV_FUSE_ZEXTWS))))
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return true;
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}
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if (simple_sets_p && riscv_fusion_enabled_p (RISCV_FUSE_ZEXTH))
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{
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/* We are trying to match the following:
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prev (slli) == (set (reg:DI rD)
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(ashift:DI (reg:DI rS) (const_int 48)))
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curr (slri) == (set (reg:DI rD)
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(lshiftrt:DI (reg:DI rD) (const_int 48))) */
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if (GET_CODE (SET_SRC (prev_set)) == ASHIFT
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&& GET_CODE (SET_SRC (curr_set)) == LSHIFTRT
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&& REG_P (SET_DEST (prev_set))
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&& REG_P (SET_DEST (curr_set))
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&& REGNO (SET_DEST (prev_set)) == REGNO (SET_DEST (curr_set))
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&& REGNO (XEXP (SET_SRC (curr_set), 0)) == REGNO (SET_DEST (curr_set))
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&& CONST_INT_P (XEXP (SET_SRC (prev_set), 1))
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&& CONST_INT_P (XEXP (SET_SRC (curr_set), 1))
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&& INTVAL (XEXP (SET_SRC (prev_set), 1)) == 48
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&& INTVAL (XEXP (SET_SRC (curr_set), 1)) == 48)
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return true;
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}
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if (simple_sets_p && riscv_fusion_enabled_p (RISCV_FUSE_LDINDEXED))
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{
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/* We are trying to match the following:
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prev (add) == (set (reg:DI rD)
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(plus:DI (reg:DI rS1) (reg:DI rS2))
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curr (ld) == (set (reg:DI rD)
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(mem:DI (reg:DI rD))) */
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if (MEM_P (SET_SRC (curr_set))
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&& REG_P (XEXP (SET_SRC (curr_set), 0))
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&& REGNO (XEXP (SET_SRC (curr_set), 0)) == REGNO (SET_DEST (prev_set))
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&& GET_CODE (SET_SRC (prev_set)) == PLUS
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&& REG_P (XEXP (SET_SRC (prev_set), 0))
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&& REG_P (XEXP (SET_SRC (prev_set), 1)))
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return true;
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/* We are trying to match the following:
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prev (add) == (set (reg:DI rD)
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(plus:DI (reg:DI rS1) (reg:DI rS2)))
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curr (lw) == (set (any_extend:DI (mem:SUBX (reg:DI rD)))) */
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if ((GET_CODE (SET_SRC (curr_set)) == SIGN_EXTEND
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|| (GET_CODE (SET_SRC (curr_set)) == ZERO_EXTEND))
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&& MEM_P (XEXP (SET_SRC (curr_set), 0))
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&& REG_P (XEXP (XEXP (SET_SRC (curr_set), 0), 0))
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&& REGNO (XEXP (XEXP (SET_SRC (curr_set), 0), 0)) == REGNO (SET_DEST (prev_set))
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&& GET_CODE (SET_SRC (prev_set)) == PLUS
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&& REG_P (XEXP (SET_SRC (prev_set), 0))
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&& REG_P (XEXP (SET_SRC (prev_set), 1)))
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return true;
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}
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if (simple_sets_p && riscv_fusion_enabled_p (RISCV_FUSE_LUI_ADDI))
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{
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/* We are trying to match the following:
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prev (lui) == (set (reg:DI rD) (const_int UPPER_IMM_20))
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curr (addi) == (set (reg:DI rD)
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(plus:DI (reg:DI rD) (const_int IMM12))) */
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if ((GET_CODE (SET_SRC (curr_set)) == LO_SUM
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|| (GET_CODE (SET_SRC (curr_set)) == PLUS
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&& CONST_INT_P (XEXP (SET_SRC (curr_set), 1))
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&& SMALL_OPERAND (INTVAL (XEXP (SET_SRC (curr_set), 1)))))
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&& (GET_CODE (SET_SRC (prev_set)) == HIGH
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|| (CONST_INT_P (SET_SRC (prev_set))
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&& LUI_OPERAND (INTVAL (SET_SRC (prev_set))))))
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return true;
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}
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if (simple_sets_p && riscv_fusion_enabled_p (RISCV_FUSE_AUIPC_ADDI))
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{
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/* We are trying to match the following:
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prev (auipc) == (set (reg:DI rD) (unspec:DI [...] UNSPEC_AUIPC))
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curr (addi) == (set (reg:DI rD)
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(plus:DI (reg:DI rD) (const_int IMM12)))
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and
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prev (auipc) == (set (reg:DI rD) (unspec:DI [...] UNSPEC_AUIPC))
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curr (addi) == (set (reg:DI rD)
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(lo_sum:DI (reg:DI rD) (const_int IMM12))) */
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if (GET_CODE (SET_SRC (prev_set)) == UNSPEC
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&& XINT (prev_set, 1) == UNSPEC_AUIPC
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&& (GET_CODE (SET_SRC (curr_set)) == LO_SUM
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|| (GET_CODE (SET_SRC (curr_set)) == PLUS
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&& SMALL_OPERAND (INTVAL (XEXP (SET_SRC (curr_set), 1))))))
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return true;
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}
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if (simple_sets_p && riscv_fusion_enabled_p (RISCV_FUSE_LUI_LD))
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{
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/* We are trying to match the following:
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prev (lui) == (set (reg:DI rD) (const_int UPPER_IMM_20))
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curr (ld) == (set (reg:DI rD)
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(mem:DI (plus:DI (reg:DI rD) (const_int IMM12)))) */
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if (CONST_INT_P (SET_SRC (prev_set))
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&& LUI_OPERAND (INTVAL (SET_SRC (prev_set)))
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&& MEM_P (SET_SRC (curr_set))
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&& GET_CODE (XEXP (SET_SRC (curr_set), 0)) == PLUS)
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return true;
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if (GET_CODE (SET_SRC (prev_set)) == HIGH
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&& MEM_P (SET_SRC (curr_set))
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&& GET_CODE (XEXP (SET_SRC (curr_set), 0)) == LO_SUM
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&& REGNO (SET_DEST (prev_set)) == REGNO (XEXP (XEXP (SET_SRC (curr_set), 0), 0)))
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return true;
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if (GET_CODE (SET_SRC (prev_set)) == HIGH
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&& (GET_CODE (SET_SRC (curr_set)) == SIGN_EXTEND
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|| GET_CODE (SET_SRC (curr_set)) == ZERO_EXTEND)
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&& MEM_P (XEXP (SET_SRC (curr_set), 0))
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&& (GET_CODE (XEXP (XEXP (SET_SRC (curr_set), 0), 0)) == LO_SUM
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&& REGNO (SET_DEST (prev_set)) == REGNO (XEXP (XEXP (XEXP (SET_SRC (curr_set), 0), 0), 0))))
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return true;
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}
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if (simple_sets_p && riscv_fusion_enabled_p (RISCV_FUSE_AUIPC_LD))
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{
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/* We are trying to match the following:
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prev (auipc) == (set (reg:DI rD) (unspec:DI [...] UNSPEC_AUIPC))
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curr (ld) == (set (reg:DI rD)
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(mem:DI (plus:DI (reg:DI rD) (const_int IMM12)))) */
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if (GET_CODE (SET_SRC (prev_set)) == UNSPEC
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&& XINT (prev_set, 1) == UNSPEC_AUIPC
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&& MEM_P (SET_SRC (curr_set))
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&& GET_CODE (XEXP (SET_SRC (curr_set), 0)) == PLUS)
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return true;
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}
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return false;
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}
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/* Auxiliary function to emit RISC-V ELF attribute. */
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static void
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riscv_emit_attribute ()
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@ -6633,6 +6849,10 @@ riscv_dwarf_poly_indeterminate_value (unsigned int i, unsigned int *factor,
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#undef TARGET_SCHED_ISSUE_RATE
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#define TARGET_SCHED_ISSUE_RATE riscv_issue_rate
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#undef TARGET_SCHED_MACRO_FUSION_P
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#define TARGET_SCHED_MACRO_FUSION_P riscv_macro_fusion_p
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#undef TARGET_SCHED_MACRO_FUSION_PAIR_P
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#define TARGET_SCHED_MACRO_FUSION_PAIR_P riscv_macro_fusion_pair_p
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#undef TARGET_FUNCTION_OK_FOR_SIBCALL
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#define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall
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