RISC-V: Add TAREGT_VECTOR check into VLS modes

This patch fixes bug: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110994

This is caused VLS modes incorrect codes int register allocation.

The original case trigger the ICE is fortran code but I can reproduce
with a C code.

gcc/ChangeLog:

	PR target/110994
	* config/riscv/riscv-opts.h (TARGET_VECTOR_VLS): Add TARGET_VETOR.

gcc/testsuite/ChangeLog:

	PR target/110994
	* gcc.target/riscv/rvv/autovec/vls/pr110994.c: New test.

gcc/config/riscv/riscv-opts.h

@@ -300,6 +300,7 @@ enum riscv_entity
 
 /* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode
    is the highest priority choice and should not conflict with VLS modes.  */
-#define TARGET_VECTOR_VLS (riscv_autovec_preference == RVV_SCALABLE)
+#define TARGET_VECTOR_VLS                                                      \
+  (TARGET_VECTOR && riscv_autovec_preference == RVV_SCALABLE)
 
 #endif /* ! GCC_RISCV_OPTS_H */

gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/pr110994.c

@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc -mabi=lp64d --param=riscv-autovec-preference=scalable -O2" } */
+
+#include "def.h"
+
+void foo (int8_t *in, int8_t *out)
+{
+  v4qi v = *(v4qi*)in;
+  *(v4qi*)out = v;
+}