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RISC-V: Do not allow v0 as dest when merging [PR115068].

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This patch splits the vfw...wf pattern so we do not emit e.g. vfwadd.wf
v0,v8,fa5,v0.t anymore.

gcc/ChangeLog:

	PR target/115068

	* config/riscv/vector.md:  Split vfw<insn>.wf pattern.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/pr115068-run.c: New test.
	* gcc.target/riscv/rvv/base/pr115068.c: New test.

(cherry picked from commit a2fd0812a54cf51520f15e900df4cfb5874b75ed)
This commit is contained in:
Robin Dapp 2024-05-13 13:49:57 +02:00 • committed by Kito Cheng
parent 3a7e796b48
commit 937713a523
3 changed files with 67 additions and 10 deletions
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20
gcc/config/riscv/vector.md
View file

@ -7197,24 +7197,24 @@
(symbol_ref "riscv_vector::get_frm_mode (operands[9])"))])
(define_insn "@pred_single_widen_<plus_minus:optab><mode>_scalar"
[(set (match_operand:VWEXTF 0 "register_operand" "=vr, vr")
[(set (match_operand:VWEXTF 0 "register_operand" "=vd, vd, vr, vr")
(if_then_else:VWEXTF
(unspec:<VM>
[(match_operand:<VM> 1 "vector_mask_operand" "vmWc1,vmWc1")
(match_operand 5 "vector_length_operand" " rK, rK")
(match_operand 6 "const_int_operand" " i, i")
(match_operand 7 "const_int_operand" " i, i")
(match_operand 8 "const_int_operand" " i, i")
(match_operand 9 "const_int_operand" " i, i")
[(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1")
(match_operand 5 "vector_length_operand" " rK, rK, rK, rK")
(match_operand 6 "const_int_operand" " i, i, i, i")
(match_operand 7 "const_int_operand" " i, i, i, i")
(match_operand 8 "const_int_operand" " i, i, i, i")
(match_operand 9 "const_int_operand" " i, i, i, i")
(reg:SI VL_REGNUM)
(reg:SI VTYPE_REGNUM)
(reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE)
(plus_minus:VWEXTF
(match_operand:VWEXTF 3 "register_operand" " vr, vr")
(match_operand:VWEXTF 3 "register_operand" " vr, vr, vr, vr")
(float_extend:VWEXTF
(vec_duplicate:<V_DOUBLE_TRUNC>
(match_operand:<VSUBEL> 4 "register_operand" " f, f"))))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0")))]
(match_operand:<VSUBEL> 4 "register_operand" " f, f, f, f"))))
(match_operand:VWEXTF 2 "vector_merge_operand" " vu, 0, vu, 0")))]
"TARGET_VECTOR"
"vfw<insn>.wf\t%0,%3,%4%p1"
[(set_attr "type" "vf<widen_binop_insn_type>")

28
gcc/testsuite/gcc.target/riscv/rvv/base/pr115068-run.c Normal file
View file

@ -0,0 +1,28 @@
/* { dg-do run } */
/* { dg-require-effective-target riscv_v_ok } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-std=gnu99" } */
#include <stdint.h>
#include <riscv_vector.h>
vfloat64m8_t
test_vfwadd_wf_f64m8_m (vbool8_t vm, vfloat64m8_t vs2, float rs1, size_t vl)
{
return __riscv_vfwadd_wf_f64m8_m (vm, vs2, rs1, vl);
}
char global_memory[1024];
void *fake_memory = (void *) global_memory;
int
main ()
{
asm volatile ("fence" ::: "memory");
vfloat64m8_t vfwadd_wf_f64m8_m_vd = test_vfwadd_wf_f64m8_m (
__riscv_vreinterpret_v_i8m1_b8 (__riscv_vundefined_i8m1 ()),
__riscv_vundefined_f64m8 (), 1.0, __riscv_vsetvlmax_e64m8 ());
asm volatile ("" ::"vr"(vfwadd_wf_f64m8_m_vd) : "memory");
return 0;
}

29
gcc/testsuite/gcc.target/riscv/rvv/base/pr115068.c Normal file
View file

@ -0,0 +1,29 @@
/* { dg-do compile } */
/* { dg-add-options riscv_v } */
/* { dg-additional-options "-std=gnu99" } */
#include <stdint.h>
#include <riscv_vector.h>
vfloat64m8_t
test_vfwadd_wf_f64m8_m (vbool8_t vm, vfloat64m8_t vs2, float rs1, size_t vl)
{
return __riscv_vfwadd_wf_f64m8_m (vm, vs2, rs1, vl);
}
char global_memory[1024];
void *fake_memory = (void *) global_memory;
int
main ()
{
asm volatile ("fence" ::: "memory");
vfloat64m8_t vfwadd_wf_f64m8_m_vd = test_vfwadd_wf_f64m8_m (
__riscv_vreinterpret_v_i8m1_b8 (__riscv_vundefined_i8m1 ()),
__riscv_vundefined_f64m8 (), 1.0, __riscv_vsetvlmax_e64m8 ());
asm volatile ("" ::"vr"(vfwadd_wf_f64m8_m_vd) : "memory");
return 0;
}
/* { dg-final { scan-assembler-not "vfwadd.wf\tv0.*v0" } } */