Add rudimentary support for atomics on RX.
Add rudimentary support for atomics on RX. It is implemented by flipping interrupts off/on around the atomic sequences. gcc/ * config/rx/rx-protos.h (is_interrupt_func, is_fast_interrupt_func): Forward declare. (rx_atomic_sequence): New class. * config/rx/rx.c (rx_print_operand): Use symbolic names for PSW bits. (is_interrupt_func, is_fast_interrupt_func): Make non-static and non-inline. (rx_atomic_sequence::rx_atomic_sequence, rx_atomic_sequence::~rx_atomic_sequence): New functions. * config/rx/rx.md (CTRLREG_PSW, CTRLREG_USP, CTRLREG_FPSW, CTRLREG_CPEN, CTRLREG_BPSW, CTRLREG_BPC, CTRLREG_ISP, CTRLREG_FINTV, CTRLREG_INTB): New constants. (FETCHOP): New code iterator. (fethcop_name, fetchop_name2): New iterator code attributes. (QIHI): New mode iterator. (atomic_exchange<mode>, atomic_exchangesi, xchg_mem<mode>, atomic_fetch_<fetchop_name>si, atomic_fetch_nandsi, atomic_<fetchop_name>_fetchsi, atomic_nand_fetchsi): New patterns. From-SVN: r236075
This commit is contained in:
Oleg Endo
parent
6f0800d418
commit
927d22fa01
4 changed files with 217 additions and 12 deletions
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@ -1,3 +1,23 @@
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2016-05-10 Oleg Endo <olegendo@gcc.gnu.org>
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* config/rx/rx-protos.h (is_interrupt_func, is_fast_interrupt_func):
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Forward declare.
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(rx_atomic_sequence): New class.
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* config/rx/rx.c (rx_print_operand): Use symbolic names for PSW bits.
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(is_interrupt_func, is_fast_interrupt_func): Make non-static and
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non-inline.
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(rx_atomic_sequence::rx_atomic_sequence,
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rx_atomic_sequence::~rx_atomic_sequence): New functions.
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* config/rx/rx.md (CTRLREG_PSW, CTRLREG_USP, CTRLREG_FPSW, CTRLREG_CPEN,
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CTRLREG_BPSW, CTRLREG_BPC, CTRLREG_ISP, CTRLREG_FINTV,
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CTRLREG_INTB): New constants.
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(FETCHOP): New code iterator.
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(fethcop_name, fetchop_name2): New iterator code attributes.
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(QIHI): New mode iterator.
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(atomic_exchange<mode>, atomic_exchangesi, xchg_mem<mode>,
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atomic_fetch_<fetchop_name>si, atomic_fetch_nandsi,
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atomic_<fetchop_name>_fetchsi, atomic_nand_fetchsi): New patterns.
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2016-05-10 Martin Liska <mliska@suse.cz>
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* tree-inline.c (remap_dependence_clique): Do not remap
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@ -26,6 +26,28 @@ extern void rx_expand_epilogue (bool);
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extern void rx_expand_prologue (void);
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extern int rx_initial_elimination_offset (int, int);
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bool is_interrupt_func (const_tree decl);
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bool is_fast_interrupt_func (const_tree decl);
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/* rx_atomic_sequence is used to emit the header and footer
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of an atomic sequence. It's supposed to be used in a scope.
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When constructed, it will emit the atomic sequence header insns.
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When destructred (goes out of scope), it will emit the
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corresponding atomic sequence footer insns. */
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class rx_atomic_sequence
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{
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public:
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rx_atomic_sequence (const_tree fun_decl);
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~rx_atomic_sequence (void);
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private:
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rx_atomic_sequence (void);
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rx_atomic_sequence (const rx_atomic_sequence&);
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rx_atomic_sequence& operator = (const rx_atomic_sequence&);
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rtx m_prev_psw_reg;
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};
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#ifdef RTX_CODE
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extern int rx_adjust_insn_length (rtx_insn *, int);
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extern int rx_align_for_label (rtx, int);
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@ -630,15 +630,15 @@ rx_print_operand (FILE * file, rtx op, int letter)
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gcc_assert (CONST_INT_P (op));
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switch (INTVAL (op))
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{
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case 0: fprintf (file, "psw"); break;
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case 2: fprintf (file, "usp"); break;
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case 3: fprintf (file, "fpsw"); break;
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case 4: fprintf (file, "cpen"); break;
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case 8: fprintf (file, "bpsw"); break;
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case 9: fprintf (file, "bpc"); break;
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case 0xa: fprintf (file, "isp"); break;
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case 0xb: fprintf (file, "fintv"); break;
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case 0xc: fprintf (file, "intb"); break;
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case CTRLREG_PSW: fprintf (file, "psw"); break;
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case CTRLREG_USP: fprintf (file, "usp"); break;
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case CTRLREG_FPSW: fprintf (file, "fpsw"); break;
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case CTRLREG_CPEN: fprintf (file, "cpen"); break;
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case CTRLREG_BPSW: fprintf (file, "bpsw"); break;
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case CTRLREG_BPC: fprintf (file, "bpc"); break;
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case CTRLREG_ISP: fprintf (file, "isp"); break;
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case CTRLREG_FINTV: fprintf (file, "fintv"); break;
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case CTRLREG_INTB: fprintf (file, "intb"); break;
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default:
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warning (0, "unrecognized control register number: %d - using 'psw'",
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(int) INTVAL (op));
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@ -1216,7 +1216,7 @@ has_func_attr (const_tree decl, const char * func_attr)
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/* Returns true if the provided function has the "fast_interrupt" attribute. */
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static inline bool
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bool
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is_fast_interrupt_func (const_tree decl)
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{
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return has_func_attr (decl, "fast_interrupt");
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@ -1224,7 +1224,7 @@ is_fast_interrupt_func (const_tree decl)
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/* Returns true if the provided function has the "interrupt" attribute. */
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static inline bool
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bool
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is_interrupt_func (const_tree decl)
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{
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return has_func_attr (decl, "interrupt");
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@ -3409,6 +3409,29 @@ rx_enable_lra (void)
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return TARGET_ENABLE_LRA;
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}
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rx_atomic_sequence::rx_atomic_sequence (const_tree fun_decl)
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{
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if (is_fast_interrupt_func (fun_decl) || is_interrupt_func (fun_decl))
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{
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/* If we are inside an interrupt handler, assume that interrupts are
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off -- which is the default hardware behavior. In this case, there
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is no need to disable the interrupts. */
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m_prev_psw_reg = NULL;
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}
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else
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{
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m_prev_psw_reg = gen_reg_rtx (SImode);
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emit_insn (gen_mvfc (m_prev_psw_reg, GEN_INT (CTRLREG_PSW)));
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emit_insn (gen_clrpsw (GEN_INT ('I')));
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}
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}
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rx_atomic_sequence::~rx_atomic_sequence (void)
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{
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if (m_prev_psw_reg != NULL)
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emit_insn (gen_mvtc (GEN_INT (CTRLREG_PSW), m_prev_psw_reg));
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}
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#undef TARGET_NARROW_VOLATILE_BITFIELD
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#define TARGET_NARROW_VOLATILE_BITFIELD rx_narrow_volatile_bitfield
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@ -75,6 +75,16 @@
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(UNSPEC_BUILTIN_WAIT 51)
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(UNSPEC_PID_ADDR 52)
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(CTRLREG_PSW 0)
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(CTRLREG_USP 2)
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(CTRLREG_FPSW 3)
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(CTRLREG_CPEN 4)
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(CTRLREG_BPSW 8)
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(CTRLREG_BPC 9)
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(CTRLREG_ISP 10)
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(CTRLREG_FINTV 11)
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(CTRLREG_INTB 12)
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]
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)
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@ -2145,7 +2155,17 @@
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FAIL;
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})
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;; Atomic exchange operation.
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;; Atomic operations.
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(define_code_iterator FETCHOP [plus minus ior xor and])
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(define_code_attr fetchop_name
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[(plus "add") (minus "sub") (ior "or") (xor "xor") (and "and")])
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(define_code_attr fetchop_name2
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[(plus "add") (minus "sub") (ior "ior") (xor "xor") (and "and")])
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(define_mode_iterator QIHI [QI HI])
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(define_insn "sync_lock_test_and_setsi"
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[(set (match_operand:SI 0 "register_operand" "=r,r")
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@ -2157,6 +2177,126 @@
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[(set_attr "length" "3,6")
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(set_attr "timings" "22")]
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)
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(define_expand "atomic_exchange<mode>"
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[(match_operand:QIHI 0 "register_operand") ;; oldval output
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(match_operand:QIHI 1 "rx_restricted_mem_operand") ;; memory
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(match_operand:QIHI 2 "register_operand") ;; newval input
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(match_operand:QIHI 3 "const_int_operand")] ;; memory model
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""
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{
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emit_insn (gen_xchg_mem<mode> (operands[0], operands[1], operands[2]));
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DONE;
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})
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(define_expand "atomic_exchangesi"
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[(match_operand:SI 0 "register_operand") ;; oldval output
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(match_operand:SI 1 "rx_restricted_mem_operand") ;; memory
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(match_operand:SI 2 "register_operand") ;; newval input
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(match_operand:SI 3 "const_int_operand")] ;; memory model
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""
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{
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emit_insn (gen_sync_lock_test_and_setsi (operands[0], operands[1],
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operands[2]));
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DONE;
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})
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(define_insn "xchg_mem<mode>"
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[(set (match_operand:QIHI 0 "register_operand" "=r")
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(match_operand:QIHI 1 "rx_compare_operand" "=Q"))
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(set (match_dup 1)
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(match_operand:QIHI 2 "register_operand" "0"))]
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""
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"xchg\t%1, %0"
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[(set_attr "length" "6")
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(set_attr "timings" "22")]
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)
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;; read - modify - write - return old value
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(define_expand "atomic_fetch_<fetchop_name>si"
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[(set (match_operand:SI 0 "register_operand")
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(match_operand:SI 1 "memory_operand"))
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(set (match_dup 1)
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(FETCHOP:SI (match_dup 1) (match_operand:SI 2 "rx_source_operand")))
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(match_operand:SI 3 "const_int_operand")] ;; memory model
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""
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{
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{
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rx_atomic_sequence seq (current_function_decl);
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emit_move_insn (operands[0], operands[1]);
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rtx tmp = gen_reg_rtx (SImode);
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emit_insn (gen_<fetchop_name2>si3 (tmp, operands[0], operands[2]));
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emit_move_insn (operands[1], tmp);
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}
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DONE;
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})
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(define_expand "atomic_fetch_nandsi"
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[(set (match_operand:SI 0 "register_operand")
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(match_operand:SI 1 "memory_operand"))
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(set (match_dup 1)
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(not:SI (and:SI (match_dup 1)
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(match_operand:SI 2 "rx_source_operand"))))
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(match_operand:SI 3 "const_int_operand")] ;; memory model
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""
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{
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{
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rx_atomic_sequence seq (current_function_decl);
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emit_move_insn (operands[0], operands[1]);
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rtx tmp = gen_reg_rtx (SImode);
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emit_insn (gen_andsi3 (tmp, operands[0], operands[2]));
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emit_insn (gen_one_cmplsi2 (tmp, tmp));
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emit_move_insn (operands[1], tmp);
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}
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DONE;
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})
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;; read - modify - write - return new value
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(define_expand "atomic_<fetchop_name>_fetchsi"
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[(set (match_operand:SI 0 "register_operand")
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(FETCHOP:SI (match_operand:SI 1 "rx_restricted_mem_operand")
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(match_operand:SI 2 "register_operand")))
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(set (match_dup 1)
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(FETCHOP:SI (match_dup 1) (match_dup 2)))
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(match_operand:SI 3 "const_int_operand")] ;; memory model
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""
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{
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{
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rx_atomic_sequence seq (current_function_decl);
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emit_move_insn (operands[0], operands[2]);
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emit_insn (gen_<fetchop_name2>si3 (operands[0], operands[0], operands[1]));
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emit_move_insn (operands[1], operands[0]);
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}
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DONE;
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})
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(define_expand "atomic_nand_fetchsi"
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[(set (match_operand:SI 0 "register_operand")
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(not:SI (and:SI (match_operand:SI 1 "rx_restricted_mem_operand")
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(match_operand:SI 2 "register_operand"))))
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(set (match_dup 1)
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(not:SI (and:SI (match_dup 1) (match_dup 2))))
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(match_operand:SI 3 "const_int_operand")] ;; memory model
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""
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{
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{
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rx_atomic_sequence seq (current_function_decl);
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emit_move_insn (operands[0], operands[2]);
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emit_insn (gen_andsi3 (operands[0], operands[0], operands[1]));
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emit_insn (gen_one_cmplsi2 (operands[0], operands[0]));
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emit_move_insn (operands[1], operands[0]);
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}
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DONE;
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});
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;; Block move functions.
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