re PR target/65614 (PowerPC VSX systems should use XSCPSGNDP to copy scalar fp data to/from Altivec registers)
[gcc] 2015-04-06 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/65614 * config/rs6000/rs6000.c (struct processor_costs): Add cost field for SF->DF conversions to make FLOAT_EXTEND more expensive, so that LFD is used to load double constants instead of LFS. Add defaults for all costs structures. Add comments for missing initialization fields. (size32_cost): Likewise. (size64_cost): Likewise. (rs64a_cost): Likewise. (mpccore_cost): Likewise. (ppc403_cost): Likewise. (ppc405_cost): Likewise. (ppc440_cost): Likewise. (ppc476_cost): Likewise. (ppc601_cost): Likewise. (ppc603_cost): Likewise. (ppc604_cost): Likewise. (ppc604e_cost): Likewise. (ppc620_cost): Likewise. (ppc630_cost): Likewise. (ppccell_cost): Likewise. (ppc750_cost): Likewise. (ppc7450_cost): Likewise. (ppc8540_cost): Likewise. (ppce300c2c3_cost): Likewise. (ppce500mc_cost): Likewise. (ppce500mc64_cost): Likewise. (ppce5500_cost): Likewise. (ppce6500_cost): Likewise. (titan_cost): Likewise. (power4_cost): Likewise. (power6_cost): Likewise. (power7_cost): Likewise. (power8_cost): Likewise. (ppca2_cost): Likewise. (rs6000_rtx_costs): Make FLOAT_EXTEND use SFDF_convert field. * config/rs6000/rs6000.md (extendsfdf2_fpr): Generate XSCPSGNDP instead of XXLOR to copy SFmode to clear out dirty bits created when SFmode denormals are generated. (mov<mode>_hardfloat, FMOVE32 case): Likewise. (truncdfsf2_fpr): Add support for ISA 2.07 XSRSP instruction. [gcc/testsuite] 2015-04-06 Michael Meissner <meissner@linux.vnet.ibm.com> PR target/65614 * gcc.target/powerpc/compress-float-ppc-pic.c: Run test on power5 to get floating point compression. * gcc.target/powerpc/compress-foat-ppc.c: Likewise. From-SVN: r221888
This commit is contained in:
Michael Meissner
Michael Meissner
parent
68b3d8c987
commit
90e0a7020e
6 changed files with 106 additions and 18 deletions
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@ -1,3 +1,48 @@
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2015-04-06 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/65614
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* config/rs6000/rs6000.c (struct processor_costs): Add cost field
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for SF->DF conversions to make FLOAT_EXTEND more expensive, so
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that LFD is used to load double constants instead of LFS. Add
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defaults for all costs structures. Add comments for missing
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initialization fields.
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(size32_cost): Likewise.
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(size64_cost): Likewise.
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(rs64a_cost): Likewise.
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(mpccore_cost): Likewise.
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(ppc403_cost): Likewise.
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(ppc405_cost): Likewise.
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(ppc440_cost): Likewise.
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(ppc476_cost): Likewise.
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(ppc601_cost): Likewise.
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(ppc603_cost): Likewise.
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(ppc604_cost): Likewise.
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(ppc604e_cost): Likewise.
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(ppc620_cost): Likewise.
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(ppc630_cost): Likewise.
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(ppccell_cost): Likewise.
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(ppc750_cost): Likewise.
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(ppc7450_cost): Likewise.
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(ppc8540_cost): Likewise.
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(ppce300c2c3_cost): Likewise.
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(ppce500mc_cost): Likewise.
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(ppce500mc64_cost): Likewise.
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(ppce5500_cost): Likewise.
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(ppce6500_cost): Likewise.
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(titan_cost): Likewise.
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(power4_cost): Likewise.
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(power6_cost): Likewise.
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(power7_cost): Likewise.
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(power8_cost): Likewise.
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(ppca2_cost): Likewise.
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(rs6000_rtx_costs): Make FLOAT_EXTEND use SFDF_convert field.
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* config/rs6000/rs6000.md (extendsfdf2_fpr): Generate XSCPSGNDP
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instead of XXLOR to copy SFmode to clear out dirty bits created
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when SFmode denormals are generated.
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(mov<mode>_hardfloat, FMOVE32 case): Likewise.
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(truncdfsf2_fpr): Add support for ISA 2.07 XSRSP instruction.
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2015-04-06 Evandro Menezes <e.menezes@samsung.com>
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* doc/invoke.texi (AARCH64/mtune): Add exynos-m1 as an option.
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@ -457,6 +457,7 @@ struct processor_costs {
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const int l2_cache_size; /* size of l2 cache, in kilobytes. */
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const int simultaneous_prefetches; /* number of parallel prefetch
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operations. */
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const int sfdf_convert; /* cost of SF->DF conversion. */
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};
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const struct processor_costs *rs6000_cost;
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@ -476,10 +477,11 @@ struct processor_costs size32_cost = {
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COSTS_N_INSNS (1), /* dmul */
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COSTS_N_INSNS (1), /* sdiv */
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COSTS_N_INSNS (1), /* ddiv */
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32,
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0,
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0,
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0,
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32, /* cache line size */
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0, /* l1 cache */
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0, /* l2 cache */
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0, /* streams */
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0, /* SF->DF convert */
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};
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/* Instruction size costs on 64bit processors. */
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@ -495,10 +497,11 @@ struct processor_costs size64_cost = {
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COSTS_N_INSNS (1), /* dmul */
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COSTS_N_INSNS (1), /* sdiv */
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COSTS_N_INSNS (1), /* ddiv */
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128,
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0,
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0,
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0,
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128, /* cache line size */
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0, /* l1 cache */
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0, /* l2 cache */
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0, /* streams */
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0, /* SF->DF convert */
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};
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/* Instruction costs on RS64A processors. */
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@ -518,6 +521,7 @@ struct processor_costs rs64a_cost = {
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128, /* l1 cache */
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2048, /* l2 cache */
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1, /* streams */
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0, /* SF->DF convert */
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};
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/* Instruction costs on MPCCORE processors. */
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@ -537,6 +541,7 @@ struct processor_costs mpccore_cost = {
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4, /* l1 cache */
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16, /* l2 cache */
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1, /* streams */
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0, /* SF->DF convert */
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};
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/* Instruction costs on PPC403 processors. */
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@ -556,6 +561,7 @@ struct processor_costs ppc403_cost = {
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4, /* l1 cache */
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16, /* l2 cache */
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1, /* streams */
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0, /* SF->DF convert */
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};
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/* Instruction costs on PPC405 processors. */
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@ -575,6 +581,7 @@ struct processor_costs ppc405_cost = {
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16, /* l1 cache */
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128, /* l2 cache */
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1, /* streams */
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0, /* SF->DF convert */
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};
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/* Instruction costs on PPC440 processors. */
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@ -594,6 +601,7 @@ struct processor_costs ppc440_cost = {
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32, /* l1 cache */
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256, /* l2 cache */
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1, /* streams */
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0, /* SF->DF convert */
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};
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/* Instruction costs on PPC476 processors. */
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@ -613,6 +621,7 @@ struct processor_costs ppc476_cost = {
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32, /* l1 cache */
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512, /* l2 cache */
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1, /* streams */
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0, /* SF->DF convert */
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};
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/* Instruction costs on PPC601 processors. */
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@ -632,6 +641,7 @@ struct processor_costs ppc601_cost = {
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32, /* l1 cache */
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256, /* l2 cache */
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1, /* streams */
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0, /* SF->DF convert */
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};
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/* Instruction costs on PPC603 processors. */
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@ -651,6 +661,7 @@ struct processor_costs ppc603_cost = {
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8, /* l1 cache */
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64, /* l2 cache */
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1, /* streams */
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0, /* SF->DF convert */
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};
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/* Instruction costs on PPC604 processors. */
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@ -670,6 +681,7 @@ struct processor_costs ppc604_cost = {
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16, /* l1 cache */
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512, /* l2 cache */
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1, /* streams */
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0, /* SF->DF convert */
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};
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/* Instruction costs on PPC604e processors. */
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@ -689,6 +701,7 @@ struct processor_costs ppc604e_cost = {
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32, /* l1 cache */
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1024, /* l2 cache */
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1, /* streams */
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0, /* SF->DF convert */
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};
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/* Instruction costs on PPC620 processors. */
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@ -708,6 +721,7 @@ struct processor_costs ppc620_cost = {
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32, /* l1 cache */
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1024, /* l2 cache */
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1, /* streams */
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0, /* SF->DF convert */
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};
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/* Instruction costs on PPC630 processors. */
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@ -727,6 +741,7 @@ struct processor_costs ppc630_cost = {
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64, /* l1 cache */
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1024, /* l2 cache */
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1, /* streams */
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0, /* SF->DF convert */
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};
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/* Instruction costs on Cell processor. */
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@ -747,6 +762,7 @@ struct processor_costs ppccell_cost = {
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32, /* l1 cache */
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512, /* l2 cache */
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6, /* streams */
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0, /* SF->DF convert */
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};
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/* Instruction costs on PPC750 and PPC7400 processors. */
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@ -766,6 +782,7 @@ struct processor_costs ppc750_cost = {
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32, /* l1 cache */
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512, /* l2 cache */
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1, /* streams */
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0, /* SF->DF convert */
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};
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/* Instruction costs on PPC7450 processors. */
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@ -785,6 +802,7 @@ struct processor_costs ppc7450_cost = {
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32, /* l1 cache */
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1024, /* l2 cache */
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1, /* streams */
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0, /* SF->DF convert */
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};
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/* Instruction costs on PPC8540 processors. */
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@ -804,6 +822,7 @@ struct processor_costs ppc8540_cost = {
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32, /* l1 cache */
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256, /* l2 cache */
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1, /* prefetch streams /*/
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0, /* SF->DF convert */
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};
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/* Instruction costs on E300C2 and E300C3 cores. */
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@ -823,6 +842,7 @@ struct processor_costs ppce300c2c3_cost = {
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16, /* l1 cache */
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16, /* l2 cache */
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1, /* prefetch streams /*/
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0, /* SF->DF convert */
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};
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/* Instruction costs on PPCE500MC processors. */
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@ -842,6 +862,7 @@ struct processor_costs ppce500mc_cost = {
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32, /* l1 cache */
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128, /* l2 cache */
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1, /* prefetch streams /*/
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0, /* SF->DF convert */
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};
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/* Instruction costs on PPCE500MC64 processors. */
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@ -861,6 +882,7 @@ struct processor_costs ppce500mc64_cost = {
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32, /* l1 cache */
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128, /* l2 cache */
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1, /* prefetch streams /*/
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0, /* SF->DF convert */
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};
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/* Instruction costs on PPCE5500 processors. */
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@ -880,6 +902,7 @@ struct processor_costs ppce5500_cost = {
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32, /* l1 cache */
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128, /* l2 cache */
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1, /* prefetch streams /*/
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0, /* SF->DF convert */
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};
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/* Instruction costs on PPCE6500 processors. */
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@ -899,6 +922,7 @@ struct processor_costs ppce6500_cost = {
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32, /* l1 cache */
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128, /* l2 cache */
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1, /* prefetch streams /*/
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0, /* SF->DF convert */
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};
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/* Instruction costs on AppliedMicro Titan processors. */
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@ -918,6 +942,7 @@ struct processor_costs titan_cost = {
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32, /* l1 cache */
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512, /* l2 cache */
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1, /* prefetch streams /*/
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0, /* SF->DF convert */
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};
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/* Instruction costs on POWER4 and POWER5 processors. */
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@ -937,6 +962,7 @@ struct processor_costs power4_cost = {
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32, /* l1 cache */
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1024, /* l2 cache */
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8, /* prefetch streams /*/
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0, /* SF->DF convert */
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};
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/* Instruction costs on POWER6 processors. */
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@ -956,6 +982,7 @@ struct processor_costs power6_cost = {
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64, /* l1 cache */
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2048, /* l2 cache */
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16, /* prefetch streams */
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0, /* SF->DF convert */
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};
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/* Instruction costs on POWER7 processors. */
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@ -975,6 +1002,7 @@ struct processor_costs power7_cost = {
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32, /* l1 cache */
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256, /* l2 cache */
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12, /* prefetch streams */
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COSTS_N_INSNS (3), /* SF->DF convert */
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};
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/* Instruction costs on POWER8 processors. */
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@ -994,6 +1022,7 @@ struct processor_costs power8_cost = {
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32, /* l1 cache */
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256, /* l2 cache */
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12, /* prefetch streams */
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COSTS_N_INSNS (3), /* SF->DF convert */
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};
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/* Instruction costs on POWER A2 processors. */
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@ -1013,6 +1042,7 @@ struct processor_costs ppca2_cost = {
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16, /* l1 cache */
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2048, /* l2 cache */
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16, /* prefetch streams */
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0, /* SF->DF convert */
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};
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@ -30480,7 +30510,7 @@ rs6000_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED,
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case FLOAT_EXTEND:
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if (mode == DFmode)
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*total = 0;
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*total = rs6000_cost->sfdf_convert;
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else
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*total = rs6000_cost->fp;
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return false;
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@ -5222,7 +5222,7 @@
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fmr %0,%1
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lfs%U1%X1 %0,%1
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#
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xxlor %x0,%x1,%x1
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xscpsgndp %x0,%x1,%x1
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lxsspx %x0,%y1"
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"&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])"
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[(const_int 0)]
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@ -5230,7 +5230,7 @@
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emit_note (NOTE_INSN_DELETED);
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DONE;
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}
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[(set_attr "type" "fp,fp,fpload,fp,vecsimple,fpload")])
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[(set_attr "type" "fp,fp,fpload,fp,fp,fpload")])
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(define_expand "truncdfsf2"
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[(set (match_operand:SF 0 "gpc_reg_operand" "")
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@ -5239,10 +5239,12 @@
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"")
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(define_insn "*truncdfsf2_fpr"
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f")
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(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))]
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[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wy")
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(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d,ws")))]
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"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
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"frsp %0,%1"
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"@
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frsp %0,%1
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xsrsp %x0,%x1"
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[(set_attr "type" "fp")])
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;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in
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@ -8058,7 +8060,7 @@
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lwz%U1%X1 %0,%1
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stw%U0%X0 %1,%0
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fmr %0,%1
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xxlor %x0,%x1,%x1
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xscpsgndp %x0,%x1,%x1
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xxlxor %x0,%x0,%x0
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li %0,0
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<f32_li>
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@ -8070,7 +8072,7 @@
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mt%0 %1
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mf%1 %0
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nop"
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[(set_attr "type" "*,load,store,fp,vecsimple,vecsimple,integer,fpload,fpstore,fpload,fpstore,mftgpr,mffgpr,mtjmpr,mfjmpr,*")
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[(set_attr "type" "*,load,store,fp,fp,vecsimple,integer,fpload,fpstore,fpload,fpstore,mftgpr,mffgpr,mtjmpr,mfjmpr,*")
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(set_attr "length" "4")])
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(define_insn "*mov<mode>_softfloat"
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@ -1,3 +1,10 @@
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2015-04-06 Michael Meissner <meissner@linux.vnet.ibm.com>
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PR target/65614
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* gcc.target/powerpc/compress-float-ppc-pic.c: Run test on power5
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to get floating point compression.
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* gcc.target/powerpc/compress-foat-ppc.c: Likewise.
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2015-04-06 Jakub Jelinek <jakub@redhat.com>
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PR preprocessor/61977
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@ -1,5 +1,7 @@
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/* { dg-do compile { target powerpc_fprs } } */
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/* { dg-options "-O2 -fpic" } */
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/* { dg-options "-O2 -fpic -mcpu=power5" } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power5" } } */
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double foo (double x) {
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return x + 1.75;
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}
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@ -1,5 +1,7 @@
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/* { dg-do compile { target powerpc_fprs } } */
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/* { dg-options "-O2" } */
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/* { dg-options "-O2 -mcpu=power5" } */
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/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power5" } } */
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double foo (double x) {
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return x + 1.75;
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}
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