From 902692c1cbdb5c0ce7ea865fa5677aaeb78802f4 Mon Sep 17 00:00:00 2001 From: Christophe Lyon Date: Mon, 10 May 2021 12:52:11 +0000 Subject: [PATCH] arm: MVE: Factorize vcmp_*f* Like in the previous, we factorize the vcmp_*f* patterns to make maintenance easier. 2021-05-10 Christophe Lyon gcc/ * config/arm/iterators.md (MVE_FP_COMPARISONS): New. * config/arm/mve.md (mve_vcmpq_f) (mve_vcmpq_n_f): New, merge all vcmp_*f* patterns. (mve_vcmpeqq_f, mve_vcmpeqq_n_f, mve_vcmpgeq_f) (mve_vcmpgeq_n_f, mve_vcmpgtq_f) (mve_vcmpgtq_n_f, mve_vcmpleq_f) (mve_vcmpleq_n_f, mve_vcmpltq_f) (mve_vcmpltq_n_f, mve_vcmpneq_f) (mve_vcmpneq_n_f): Remove. * config/arm/unspecs.md (VCMPEQQ_F, VCMPEQQ_N_F, VCMPGEQ_F) (VCMPGEQ_N_F, VCMPGTQ_F, VCMPGTQ_N_F, VCMPLEQ_F, VCMPLEQ_N_F) (VCMPLTQ_F, VCMPLTQ_N_F, VCMPNEQ_F, VCMPNEQ_N_F): Remove. --- gcc/config/arm/iterators.md | 1 + gcc/config/arm/mve.md | 172 +++--------------------------------- gcc/config/arm/unspecs.md | 12 --- 3 files changed, 11 insertions(+), 174 deletions(-) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 29347f70bcd..95df8bdf77d 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -287,6 +287,7 @@ (define_code_iterator COMPARISONS [eq gt ge le lt]) ;; Comparisons for MVE (define_code_iterator MVE_COMPARISONS [eq ge geu gt gtu le lt ne]) +(define_code_iterator MVE_FP_COMPARISONS [eq ge gt le lt ne]) ;; A list of ... (define_code_iterator IOR_XOR [ior xor]) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 85c108cd269..45df2110ae9 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -1901,182 +1901,30 @@ ]) ;; -;; [vcmpeqq_f]) +;; [vcmpeqq_f, vcmpgeq_f, vcmpgtq_f, vcmpleq_f, vcmpltq_f, vcmpneq_f]) ;; -(define_insn "mve_vcmpeqq_f" +(define_insn "mve_vcmpq_f" [ (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VCMPEQQ_F)) + (MVE_FP_COMPARISONS:HI (match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand:MVE_0 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmp.f%# eq, %q1, %q2" + "vcmp.f%# , %q1, %q2" [(set_attr "type" "mve_move") ]) ;; -;; [vcmpeqq_n_f]) +;; [vcmpeqq_n_f, vcmpgeq_n_f, vcmpgtq_n_f, vcmpleq_n_f, vcmpltq_n_f, vcmpneq_n_f]) ;; -(define_insn "mve_vcmpeqq_n_f" +(define_insn "mve_vcmpq_n_f" [ (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r")] - VCMPEQQ_N_F)) + (MVE_FP_COMPARISONS:HI (match_operand:MVE_0 1 "s_register_operand" "w") + (match_operand: 2 "s_register_operand" "r"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmp.f%# eq, %q1, %2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpgeq_f]) -;; -(define_insn "mve_vcmpgeq_f" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VCMPGEQ_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmp.f%# ge, %q1, %q2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpgeq_n_f]) -;; -(define_insn "mve_vcmpgeq_n_f" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r")] - VCMPGEQ_N_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmp.f%# ge, %q1, %2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpgtq_f]) -;; -(define_insn "mve_vcmpgtq_f" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VCMPGTQ_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmp.f%# gt, %q1, %q2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpgtq_n_f]) -;; -(define_insn "mve_vcmpgtq_n_f" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r")] - VCMPGTQ_N_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmp.f%# gt, %q1, %2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpleq_f]) -;; -(define_insn "mve_vcmpleq_f" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VCMPLEQ_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmp.f%# le, %q1, %q2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpleq_n_f]) -;; -(define_insn "mve_vcmpleq_n_f" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r")] - VCMPLEQ_N_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmp.f%# le, %q1, %2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpltq_f]) -;; -(define_insn "mve_vcmpltq_f" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VCMPLTQ_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmp.f%# lt, %q1, %q2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpltq_n_f]) -;; -(define_insn "mve_vcmpltq_n_f" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r")] - VCMPLTQ_N_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmp.f%# lt, %q1, %2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpneq_f]) -;; -(define_insn "mve_vcmpneq_f" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand:MVE_0 2 "s_register_operand" "w")] - VCMPNEQ_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmp.f%# ne, %q1, %q2" - [(set_attr "type" "mve_move") -]) - -;; -;; [vcmpneq_n_f]) -;; -(define_insn "mve_vcmpneq_n_f" - [ - (set (match_operand:HI 0 "vpr_register_operand" "=Up") - (unspec:HI [(match_operand:MVE_0 1 "s_register_operand" "w") - (match_operand: 2 "s_register_operand" "r")] - VCMPNEQ_N_F)) - ] - "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" - "vcmp.f%# ne, %q1, %2" + "vcmp.f%# , %q1, %2" [(set_attr "type" "mve_move") ]) diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index 4d47ab734e3..07ca53b8b0b 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -710,18 +710,6 @@ VABDQ_M_U VABDQ_F VADDQ_N_F - VCMPEQQ_F - VCMPEQQ_N_F - VCMPGEQ_F - VCMPGEQ_N_F - VCMPGTQ_F - VCMPGTQ_N_F - VCMPLEQ_F - VCMPLEQ_N_F - VCMPLTQ_F - VCMPLTQ_N_F - VCMPNEQ_F - VCMPNEQ_N_F VMAXNMAQ_F VMAXNMAVQ_F VMAXNMQ_F