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RISC-V: Enable vect test for RV32

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gcc/testsuite/ChangeLog:

	* lib/target-supports.exp: Add RV32.
This commit is contained in:
Juzhe-Zhong 2023-12-18 17:49:08 +08:00 • committed by Pan Li
parent 000155e8ee
commit 8c5d1d1388
1 changed files with 4 additions and 3 deletions
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7
gcc/testsuite/lib/target-supports.exp
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@ -11569,13 +11569,14 @@ proc check_vect_support_and_set_flags { } {
}
} elseif [istarget amdgcn-*-*] {
set dg-do-what-default run
} elseif [istarget riscv64-*-*] {
} elseif [istarget riscv*-*-*] {
if [check_effective_target_riscv_v] {
lappend DEFAULT_VECTCFLAGS "--param" "riscv-vector-abi"
set dg-do-what-default run
} else {
lappend DEFAULT_VECTCFLAGS "-march=rv64gcv_zvfh" "-mabi=lp64d"
lappend DEFAULT_VECTCFLAGS "--param" "riscv-autovec-preference=scalable"
foreach item [add_options_for_riscv_v ""] {
lappend DEFAULT_VECTCFLAGS $item
}
lappend DEFAULT_VECTCFLAGS "--param" "riscv-vector-abi"
set dg-do-what-default compile
}