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re PR target/63187 (Unrecognizable insn ICE due to revision 214080)

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2014-09-05  Segher Boessenkool  <segher@kernel.crashing.org>

	PR target/63187
	* config/rs6000/rs6000.md (*and<mode>3_imm_dot, *and<mode>3_imm_dot2):
	Do not allow any_mask_operand for operands[2].
	(*and<mode>3_imm_mask_dot, *and<mode>3_imm_mask_dot2): New.

From-SVN: r214976
This commit is contained in:
Segher Boessenkool 2014-09-05 21:17:08 +02:00 • committed by Segher Boessenkool
parent ed23bf8bd6
commit 8a03df77b1
2 changed files with 61 additions and 2 deletions
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7
gcc/ChangeLog
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@ -1,3 +1,10 @@
2014-09-05 Segher Boessenkool <segher@kernel.crashing.org>
PR target/63187
* config/rs6000/rs6000.md (*and<mode>3_imm_dot, *and<mode>3_imm_dot2):
Do not allow any_mask_operand for operands[2].
(*and<mode>3_imm_mask_dot, *and<mode>3_imm_mask_dot2): New.
2014-09-05 David Malcolm <dmalcolm@redhat.com>
* config/arc/arc.c (arc_print_operand): Use insn method of

56
gcc/config/rs6000/rs6000.md
View file

@ -2736,7 +2736,8 @@
(clobber (match_scratch:GPR 0 "=r,r"))
(clobber (match_scratch:CC 4 "=X,x"))]
"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
&& rs6000_gen_cell_microcode"
&& rs6000_gen_cell_microcode
&& !any_mask_operand (operands[2], <MODE>mode)"
"@
andi%e2. %0,%1,%u2
#"
@ -2763,7 +2764,8 @@
(match_dup 2)))
(clobber (match_scratch:CC 4 "=X,x"))]
"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
&& rs6000_gen_cell_microcode"
&& rs6000_gen_cell_microcode
&& !any_mask_operand (operands[2], <MODE>mode)"
"@
andi%e2. %0,%1,%u2
#"
@ -2780,6 +2782,56 @@
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_insn_and_split "*and<mode>3_imm_mask_dot"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
(compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
(match_operand:GPR 2 "logical_const_operand" "n,n"))
(const_int 0)))
(clobber (match_scratch:GPR 0 "=r,r"))]
"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
&& rs6000_gen_cell_microcode
&& any_mask_operand (operands[2], <MODE>mode)"
"@
andi%e2. %0,%1,%u2
#"
"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
[(set (match_dup 0)
(and:GPR (match_dup 1)
(match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
""
[(set_attr "type" "logical")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_insn_and_split "*and<mode>3_imm_mask_dot2"
[(set (match_operand:CC 3 "cc_reg_operand" "=x,??y")
(compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,r")
(match_operand:GPR 2 "logical_const_operand" "n,n"))
(const_int 0)))
(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")
(and:GPR (match_dup 1)
(match_dup 2)))]
"(<MODE>mode == Pmode || UINTVAL (operands[2]) <= 0x7fffffff)
&& rs6000_gen_cell_microcode
&& any_mask_operand (operands[2], <MODE>mode)"
"@
andi%e2. %0,%1,%u2
#"
"&& reload_completed && cc_reg_not_cr0_operand (operands[3], CCmode)"
[(set (match_dup 0)
(and:GPR (match_dup 1)
(match_dup 2)))
(set (match_dup 3)
(compare:CC (match_dup 0)
(const_int 0)))]
""
[(set_attr "type" "logical")
(set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_insn "*and<mode>3_mask"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r")