[GCC, AArch64] Enable Transactional Memory Extension
This patch enables the new Transactional Memory Extension announced recently as part of Arm's new architecture technologies. We introduce a new optional extension "tme" to enable this. The following instructions are part of the extension: * tstart <Xt> * ttest <Xt> * tcommit * tcancel #<imm> We have also added ACLE intrinsics for the instructions. *** gcc/ChangeLog *** 2019-07-31 Sudakshina Das <sudi.das@arm.com> * config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add AARCH64_TME_BUILTIN_TSTART, AARCH64_TME_BUILTIN_TCOMMIT, AARCH64_TME_BUILTIN_TTEST and AARCH64_TME_BUILTIN_TCANCEL. (aarch64_init_tme_builtins): New. (aarch64_init_builtins): Call aarch64_init_tme_builtins. (aarch64_expand_builtin_tme): New. (aarch64_expand_builtin): Handle TME builtins. * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define __ARM_FEATURE_TME when enabled. * config/aarch64/aarch64-option-extensions.def: Add "tme". * config/aarch64/aarch64.h (AARCH64_FL_TME, AARCH64_ISA_TME): New. (TARGET_TME): New. * config/aarch64/aarch64.md (define_c_enum "unspec"): Add UNSPEC_TTEST. (define_c_enum "unspecv"): Add UNSPECV_TSTART, UNSPECV_TCOMMIT and UNSPECV_TCANCEL. (tstart, ttest, tcommit, tcancel): New instructions. * config/aarch64/arm_acle.h (__tstart, __tcommit): New. (__tcancel, __ttest): New. (_TMFAILURE_REASON, _TMFAILURE_RTRY, _TMFAILURE_CNCL): New macro. (_TMFAILURE_MEM, _TMFAILURE_IMP, _TMFAILURE_ERR): Likewise. (_TMFAILURE_SIZE, _TMFAILURE_NEST, _TMFAILURE_DBG): Likewise. (_TMFAILURE_INT, _TMFAILURE_TRIVIAL): Likewise. * config/arm/types.md: Add new tme type attr. * doc/invoke.texi: Document "tme". *** gcc/testsuite/ChangeLog *** 2019-07-31 Sudakshina Das <sudi.das@arm.com> * gcc.target/aarch64/acle/tme.c: New test. * gcc.target/aarch64/pragma_cpp_predefs_2.c: New test. From-SVN: r273926
This commit is contained in:
Sudakshina Das
Sudakshina Das
parent
f0efd92502
commit
89626179b6
12 changed files with 280 additions and 7 deletions
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@ -1,3 +1,30 @@
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2019-07-31 Sudakshina Das <sudi.das@arm.com>
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* config/aarch64/aarch64-builtins.c (enum aarch64_builtins): Add
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AARCH64_TME_BUILTIN_TSTART, AARCH64_TME_BUILTIN_TCOMMIT,
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AARCH64_TME_BUILTIN_TTEST and AARCH64_TME_BUILTIN_TCANCEL.
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(aarch64_init_tme_builtins): New.
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(aarch64_init_builtins): Call aarch64_init_tme_builtins.
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(aarch64_expand_builtin_tme): New.
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(aarch64_expand_builtin): Handle TME builtins.
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* config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define
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__ARM_FEATURE_TME when enabled.
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* config/aarch64/aarch64-option-extensions.def: Add "tme".
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* config/aarch64/aarch64.h (AARCH64_FL_TME, AARCH64_ISA_TME): New.
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(TARGET_TME): New.
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* config/aarch64/aarch64.md (define_c_enum "unspec"): Add UNSPEC_TTEST.
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(define_c_enum "unspecv"): Add UNSPECV_TSTART, UNSPECV_TCOMMIT and
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UNSPECV_TCANCEL.
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(tstart, ttest, tcommit, tcancel): New instructions.
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* config/aarch64/arm_acle.h (__tstart, __tcommit): New.
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(__tcancel, __ttest): New.
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(_TMFAILURE_REASON, _TMFAILURE_RTRY, _TMFAILURE_CNCL): New macro.
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(_TMFAILURE_MEM, _TMFAILURE_IMP, _TMFAILURE_ERR): Likewise.
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(_TMFAILURE_SIZE, _TMFAILURE_NEST, _TMFAILURE_DBG): Likewise.
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(_TMFAILURE_INT, _TMFAILURE_TRIVIAL): Likewise.
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* config/arm/types.md: Add new tme type attr.
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* doc/invoke.texi: Document "tme".
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2019-07-31 Joel Hutton <Joel.Hutton@arm.com>
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* config/arm/arm_cmse.h (cmse_nonsecure_caller): Add
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@ -438,6 +438,11 @@ enum aarch64_builtins
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/* Special cased Armv8.3-A Complex FMA by Lane quad Builtins. */
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AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE,
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AARCH64_SIMD_FCMLA_LANEQ_BUILTINS
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/* TME builtins. */
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AARCH64_TME_BUILTIN_TSTART,
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AARCH64_TME_BUILTIN_TCOMMIT,
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AARCH64_TME_BUILTIN_TTEST,
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AARCH64_TME_BUILTIN_TCANCEL,
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AARCH64_BUILTIN_MAX
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};
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@ -1067,6 +1072,35 @@ aarch64_init_pauth_hint_builtins (void)
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NULL_TREE);
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}
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/* Initialize the transactional memory extension (TME) builtins. */
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static void
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aarch64_init_tme_builtins (void)
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{
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tree ftype_uint64_void
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= build_function_type_list (uint64_type_node, NULL);
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tree ftype_void_void
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= build_function_type_list (void_type_node, NULL);
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tree ftype_void_uint64
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= build_function_type_list (void_type_node, uint64_type_node, NULL);
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aarch64_builtin_decls[AARCH64_TME_BUILTIN_TSTART]
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= add_builtin_function ("__builtin_aarch64_tstart", ftype_uint64_void,
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AARCH64_TME_BUILTIN_TSTART, BUILT_IN_MD,
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NULL, NULL_TREE);
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aarch64_builtin_decls[AARCH64_TME_BUILTIN_TTEST]
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= add_builtin_function ("__builtin_aarch64_ttest", ftype_uint64_void,
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AARCH64_TME_BUILTIN_TTEST, BUILT_IN_MD,
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NULL, NULL_TREE);
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aarch64_builtin_decls[AARCH64_TME_BUILTIN_TCOMMIT]
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= add_builtin_function ("__builtin_aarch64_tcommit", ftype_void_void,
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AARCH64_TME_BUILTIN_TCOMMIT, BUILT_IN_MD,
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NULL, NULL_TREE);
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aarch64_builtin_decls[AARCH64_TME_BUILTIN_TCANCEL]
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= add_builtin_function ("__builtin_aarch64_tcancel", ftype_void_uint64,
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AARCH64_TME_BUILTIN_TCANCEL, BUILT_IN_MD,
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NULL, NULL_TREE);
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}
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void
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aarch64_init_builtins (void)
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{
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@ -1104,6 +1138,9 @@ aarch64_init_builtins (void)
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register them. */
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if (!TARGET_ILP32)
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aarch64_init_pauth_hint_builtins ();
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if (TARGET_TME)
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aarch64_init_tme_builtins ();
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}
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tree
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@ -1507,6 +1544,47 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode)
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return target;
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}
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/* Function to expand an expression EXP which calls one of the Transactional
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Memory Extension (TME) builtins FCODE with the result going to TARGET. */
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static rtx
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aarch64_expand_builtin_tme (int fcode, tree exp, rtx target)
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{
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switch (fcode)
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{
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case AARCH64_TME_BUILTIN_TSTART:
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target = gen_reg_rtx (DImode);
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emit_insn (GEN_FCN (CODE_FOR_tstart) (target));
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break;
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case AARCH64_TME_BUILTIN_TTEST:
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target = gen_reg_rtx (DImode);
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emit_insn (GEN_FCN (CODE_FOR_ttest) (target));
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break;
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case AARCH64_TME_BUILTIN_TCOMMIT:
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emit_insn (GEN_FCN (CODE_FOR_tcommit) ());
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break;
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case AARCH64_TME_BUILTIN_TCANCEL:
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{
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tree arg0 = CALL_EXPR_ARG (exp, 0);
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rtx op0 = expand_normal (arg0);
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if (CONST_INT_P (op0) && UINTVAL (op0) <= 65536)
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emit_insn (GEN_FCN (CODE_FOR_tcancel) (op0));
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else
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{
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error ("%Kargument must be a 16-bit constant immediate", exp);
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return const0_rtx;
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}
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}
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break;
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default :
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gcc_unreachable ();
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}
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return target;
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}
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/* Expand an expression EXP that calls a built-in function,
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with result going to TARGET if that's convenient. */
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rtx
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@ -1627,6 +1705,12 @@ aarch64_expand_builtin (tree exp,
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|| fcode == AARCH64_BUILTIN_RSQRT_V4SF)
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return aarch64_expand_builtin_rsqrt (fcode, exp, target);
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if (fcode == AARCH64_TME_BUILTIN_TSTART
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|| fcode == AARCH64_TME_BUILTIN_TCOMMIT
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|| fcode == AARCH64_TME_BUILTIN_TTEST
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|| fcode == AARCH64_TME_BUILTIN_TCANCEL)
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return aarch64_expand_builtin_tme (fcode, exp, target);
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gcc_unreachable ();
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}
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@ -157,6 +157,8 @@ aarch64_update_cpp_builtins (cpp_reader *pfile)
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aarch64_def_or_undef (TARGET_SM4, "__ARM_FEATURE_SM4", pfile);
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aarch64_def_or_undef (TARGET_F16FML, "__ARM_FEATURE_FP16_FML", pfile);
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aarch64_def_or_undef (TARGET_TME, "__ARM_FEATURE_TME", pfile);
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/* Not for ACLE, but required to keep "float.h" correct if we switch
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target between implementations that do or do not support ARMv8.2-A
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16-bit floating-point extensions. */
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@ -195,4 +195,7 @@ AARCH64_OPT_EXTENSION("sve2-bitperm", AARCH64_FL_SVE2_BITPERM, AARCH64_FL_SIMD |
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AARCH64_FL_F16 | AARCH64_FL_FP | AARCH64_FL_SVE | \
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AARCH64_FL_SVE2, 0, false, "")
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/* Enabling or disabling "tme" only changes "tme". */
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AARCH64_OPT_EXTENSION("tme", AARCH64_FL_TME, 0, 0, false, "")
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#undef AARCH64_OPT_EXTENSION
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@ -199,6 +199,9 @@ extern unsigned aarch64_architecture_version;
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#define AARCH64_FL_SVE2_SHA3 (1ULL << 31)
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#define AARCH64_FL_SVE2_BITPERM (1ULL << 32)
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/* Transactional Memory Extension. */
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#define AARCH64_FL_TME (1ULL << 33) /* Has TME instructions. */
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/* Has FP and SIMD. */
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#define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD)
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@ -243,6 +246,7 @@ extern unsigned aarch64_architecture_version;
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#define AARCH64_ISA_F16FML (aarch64_isa_flags & AARCH64_FL_F16FML)
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#define AARCH64_ISA_RCPC8_4 (aarch64_isa_flags & AARCH64_FL_RCPC8_4)
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#define AARCH64_ISA_V8_5 (aarch64_isa_flags & AARCH64_FL_V8_5)
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#define AARCH64_ISA_TME (aarch64_isa_flags & AARCH64_FL_TME)
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/* Crypto is an optional extension to AdvSIMD. */
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#define TARGET_CRYPTO (TARGET_SIMD && AARCH64_ISA_CRYPTO)
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@ -287,6 +291,9 @@ extern unsigned aarch64_architecture_version;
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/* Armv8.3-a Complex number extension to AdvSIMD extensions. */
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#define TARGET_COMPLEX (TARGET_SIMD && TARGET_ARMV8_3)
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/* TME instructions are enabled. */
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#define TARGET_TME (AARCH64_ISA_TME)
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/* Make sure this is always defined so we don't have to check for ifdefs
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but rather use normal ifs. */
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#ifndef TARGET_FIX_ERR_A53_835769_DEFAULT
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@ -236,6 +236,7 @@
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UNSPEC_REV_SUBREG
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UNSPEC_SPECULATION_TRACKER
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UNSPEC_COPYSIGN
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UNSPEC_TTEST ; Represent transaction test.
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])
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(define_c_enum "unspecv" [
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@ -251,6 +252,9 @@
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UNSPECV_BTI_C ; Represent BTI c.
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UNSPECV_BTI_J ; Represent BTI j.
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UNSPECV_BTI_JC ; Represent BTI jc.
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UNSPECV_TSTART ; Represent transaction start.
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UNSPECV_TCOMMIT ; Represent transaction commit.
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UNSPECV_TCANCEL ; Represent transaction cancel.
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]
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)
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@ -7242,6 +7246,43 @@
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(set_attr "speculation_barrier" "true")]
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)
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;; Transactional Memory Extension (TME) instructions.
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(define_insn "tstart"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec_volatile:DI [(const_int 0)] UNSPECV_TSTART))
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(clobber (mem:BLK (scratch)))]
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"TARGET_TME"
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"tstart\\t%0"
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[(set_attr "type" "tme")]
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)
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(define_insn "ttest"
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[(set (match_operand:DI 0 "register_operand" "=r")
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(unspec_volatile:DI [(const_int 0)] UNSPEC_TTEST))
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(clobber (mem:BLK (scratch)))]
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"TARGET_TME"
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"ttest\\t%0"
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[(set_attr "type" "tme")]
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)
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(define_insn "tcommit"
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[(unspec_volatile:BLK [(const_int 0)] UNSPECV_TCOMMIT)
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(clobber (mem:BLK (scratch)))]
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"TARGET_TME"
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"tcommit"
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[(set_attr "type" "tme")]
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)
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(define_insn "tcancel"
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[(unspec_volatile:BLK
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[(match_operand 0 "const_int_operand" "n")] UNSPECV_TCANCEL)
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(clobber (mem:BLK (scratch)))]
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"TARGET_TME && (UINTVAL (operands[0]) <= 65535)"
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"tcancel\\t#%0"
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[(set_attr "type" "tme")]
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)
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;; AdvSIMD Stuff
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(include "aarch64-simd.md")
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@ -29,14 +29,14 @@
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#include <stdint.h>
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#pragma GCC push_options
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#pragma GCC target ("+nothing+crc")
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#ifdef __cplusplus
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extern "C" {
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#endif
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#pragma GCC push_options
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#pragma GCC target ("+nothing+crc")
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__extension__ static __inline uint32_t __attribute__ ((__always_inline__))
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__crc32b (uint32_t __a, uint8_t __b)
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{
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@ -85,10 +85,53 @@ __crc32d (uint32_t __a, uint64_t __b)
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return __builtin_aarch64_crc32x (__a, __b);
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}
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#pragma GCC pop_options
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#ifdef __ARM_FEATURE_TME
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#pragma GCC push_options
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#pragma GCC target ("+nothing+tme")
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#define _TMFAILURE_REASON 0x00007fffu
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#define _TMFAILURE_RTRY 0x00008000u
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#define _TMFAILURE_CNCL 0x00010000u
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#define _TMFAILURE_MEM 0x00020000u
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#define _TMFAILURE_IMP 0x00040000u
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#define _TMFAILURE_ERR 0x00080000u
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#define _TMFAILURE_SIZE 0x00100000u
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#define _TMFAILURE_NEST 0x00200000u
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#define _TMFAILURE_DBG 0x00400000u
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#define _TMFAILURE_INT 0x00800000u
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#define _TMFAILURE_TRIVIAL 0x01000000u
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__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
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__tstart (void)
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{
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return __builtin_aarch64_tstart ();
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}
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__extension__ static __inline void __attribute__ ((__always_inline__))
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__tcommit (void)
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{
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__builtin_aarch64_tcommit ();
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}
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__extension__ static __inline void __attribute__ ((__always_inline__))
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__tcancel (const uint64_t __reason)
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{
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__builtin_aarch64_tcancel (__reason);
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}
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__extension__ static __inline uint64_t __attribute__ ((__always_inline__))
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__ttest (void)
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{
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return __builtin_aarch64_ttest ();
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}
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#pragma GCC pop_options
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#endif
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#ifdef __cplusplus
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}
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#endif
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#pragma GCC pop_options
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#endif
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@ -546,6 +546,10 @@
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; The classification below is for coprocessor instructions
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;
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; coproc
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;
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; The classification below is for TME instructions
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;
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; tme
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(define_attr "type"
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"adc_imm,\
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@ -1091,7 +1095,8 @@
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crypto_sha3,\
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crypto_sm3,\
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crypto_sm4,\
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coproc"
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coproc,\
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tme"
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(const_string "untyped"))
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; Is this an (integer side) multiply with a 32-bit (or smaller) result?
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@ -16095,6 +16095,8 @@ Enable SVE2 aes instructions. This also enables SVE2 instructions.
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@item sve2-sha3
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Enable SVE2 sha3 instructions. This also enables SVE2 instructions.
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@option{-march=armv8.5-a}.
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@item tme
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Enable the Transactional Memory Extension.
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@end table
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@ -1,3 +1,8 @@
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2019-07-31 Sudakshina Das <sudi.das@arm.com>
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* gcc.target/aarch64/acle/tme.c: New test.
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* gcc.target/aarch64/pragma_cpp_predefs_2.c: New test.
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2019-07-31 Joel Hutton <Joel.Hutton@arm.com>
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|
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* gcc.target/arm/cmse/cmse-17.c: New test.
|
||||
|
|
|
|||
34
gcc/testsuite/gcc.target/aarch64/acle/tme.c
Normal file
34
gcc/testsuite/gcc.target/aarch64/acle/tme.c
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
/* Test the TME intrinsics. */
|
||||
|
||||
/* { dg-do compile } */
|
||||
/* { dg-options "-save-temps -O2 -march=armv8-a+tme" } */
|
||||
|
||||
#include "arm_acle.h"
|
||||
|
||||
#define tcancel_reason 0x234
|
||||
|
||||
unsigned
|
||||
check_tme (void)
|
||||
{
|
||||
unsigned status = __tstart ();
|
||||
if (status == 0)
|
||||
{
|
||||
if (__ttest () == 2)
|
||||
{
|
||||
__tcancel (tcancel_reason & _TMFAILURE_REASON);
|
||||
return tcancel_reason;
|
||||
}
|
||||
|
||||
__tcommit ();
|
||||
return 0;
|
||||
}
|
||||
else if (status & _TMFAILURE_NEST)
|
||||
return _TMFAILURE_NEST;
|
||||
else if (status & _TMFAILURE_TRIVIAL)
|
||||
return _TMFAILURE_TRIVIAL;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler "tstart\tx..?\n" } } */
|
||||
/* { dg-final { scan-assembler "tcancel\t#564\n" } } */
|
||||
/* { dg-final { scan-assembler "ttest\tx..?\n" } } */
|
||||
/* { dg-final { scan-assembler "tcommit\n" } } */
|
||||
20
gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c
Normal file
20
gcc/testsuite/gcc.target/aarch64/pragma_cpp_predefs_2.c
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2" } */
|
||||
|
||||
#pragma GCC push_options
|
||||
#pragma GCC target ("arch=armv8-a+tme")
|
||||
#ifndef __ARM_FEATURE_TME
|
||||
#error "__ARM_FEATURE_TME is not defined but should be!"
|
||||
#endif
|
||||
|
||||
#pragma GCC pop_options
|
||||
|
||||
#ifdef __ARM_FEATURE_TME
|
||||
#error "__ARM_FEATURE_TME is defined but should not be!"
|
||||
#endif
|
||||
|
||||
int
|
||||
foo (int a)
|
||||
{
|
||||
return a;
|
||||
}
|
||||
Loading…
Add table
Reference in a new issue