RISC-V: Add vwsubu.w C++ api TETS
gcc/testsuite/ChangeLog: * g++.target/riscv/rvv/base/vwsubu_wv-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_mu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_mu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_mu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_tu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_tu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_tu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_tum-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_tum-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_tum-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wv_tumu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_mu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_mu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_mu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_tu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_tu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_tu-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_tum-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_tum-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_tum-3.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_tumu-1.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_tumu-2.C: New test. * g++.target/riscv/rvv/base/vwsubu_wx_tumu-3.C: New test.
This commit is contained in:
Ju-Zhe Zhong
Kito Cheng
parent
345b2aa4eb
commit
8532ae57f3
30 changed files with 3960 additions and 0 deletions
216
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-1.C
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216
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-1.C
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/* { dg-do compile } */
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/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
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#include "riscv_vector.h"
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vuint16mf4_t test___riscv_vwsubu_wv(vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(op1,op2,vl);
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}
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vuint16mf2_t test___riscv_vwsubu_wv(vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(op1,op2,vl);
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}
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vuint16m1_t test___riscv_vwsubu_wv(vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(op1,op2,vl);
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}
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vuint16m2_t test___riscv_vwsubu_wv(vuint16m2_t op1,vuint8m1_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(op1,op2,vl);
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}
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vuint16m4_t test___riscv_vwsubu_wv(vuint16m4_t op1,vuint8m2_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(op1,op2,vl);
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}
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vuint16m8_t test___riscv_vwsubu_wv(vuint16m8_t op1,vuint8m4_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(op1,op2,vl);
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}
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vuint32mf2_t test___riscv_vwsubu_wv(vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(op1,op2,vl);
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}
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vuint32m1_t test___riscv_vwsubu_wv(vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(op1,op2,vl);
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}
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vuint32m2_t test___riscv_vwsubu_wv(vuint32m2_t op1,vuint16m1_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(op1,op2,vl);
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}
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vuint32m4_t test___riscv_vwsubu_wv(vuint32m4_t op1,vuint16m2_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(op1,op2,vl);
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}
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vuint32m8_t test___riscv_vwsubu_wv(vuint32m8_t op1,vuint16m4_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(op1,op2,vl);
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}
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vuint64m1_t test___riscv_vwsubu_wv(vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(op1,op2,vl);
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}
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vuint64m2_t test___riscv_vwsubu_wv(vuint64m2_t op1,vuint32m1_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(op1,op2,vl);
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}
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vuint64m4_t test___riscv_vwsubu_wv(vuint64m4_t op1,vuint32m2_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(op1,op2,vl);
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}
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vuint64m8_t test___riscv_vwsubu_wv(vuint64m8_t op1,vuint32m4_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(op1,op2,vl);
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}
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vuint16mf4_t test___riscv_vwsubu_wv(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(mask,op1,op2,vl);
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}
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vuint16mf2_t test___riscv_vwsubu_wv(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(mask,op1,op2,vl);
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}
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vuint16m1_t test___riscv_vwsubu_wv(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(mask,op1,op2,vl);
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}
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vuint16m2_t test___riscv_vwsubu_wv(vbool8_t mask,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(mask,op1,op2,vl);
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}
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vuint16m4_t test___riscv_vwsubu_wv(vbool4_t mask,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(mask,op1,op2,vl);
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}
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vuint16m8_t test___riscv_vwsubu_wv(vbool2_t mask,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(mask,op1,op2,vl);
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}
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vuint32mf2_t test___riscv_vwsubu_wv(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(mask,op1,op2,vl);
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}
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vuint32m1_t test___riscv_vwsubu_wv(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(mask,op1,op2,vl);
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}
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vuint32m2_t test___riscv_vwsubu_wv(vbool16_t mask,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(mask,op1,op2,vl);
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}
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vuint32m4_t test___riscv_vwsubu_wv(vbool8_t mask,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(mask,op1,op2,vl);
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}
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vuint32m8_t test___riscv_vwsubu_wv(vbool4_t mask,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(mask,op1,op2,vl);
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}
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vuint64m1_t test___riscv_vwsubu_wv(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(mask,op1,op2,vl);
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}
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vuint64m2_t test___riscv_vwsubu_wv(vbool32_t mask,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(mask,op1,op2,vl);
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}
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vuint64m4_t test___riscv_vwsubu_wv(vbool16_t mask,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(mask,op1,op2,vl);
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}
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vuint64m8_t test___riscv_vwsubu_wv(vbool8_t mask,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
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{
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return __riscv_vwsubu_wv(mask,op1,op2,vl);
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}
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
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/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
216
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-2.C
Normal file
216
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-2.C
Normal file
|
|
@ -0,0 +1,216 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wv(vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wv(vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wv(vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wv(vuint16m2_t op1,vuint8m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wv(vuint16m4_t op1,vuint8m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wv(vuint16m8_t op1,vuint8m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wv(vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wv(vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wv(vuint32m2_t op1,vuint16m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wv(vuint32m4_t op1,vuint16m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wv(vuint32m8_t op1,vuint16m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wv(vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wv(vuint64m2_t op1,vuint32m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wv(vuint64m4_t op1,vuint32m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wv(vuint64m8_t op1,vuint32m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wv(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wv(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wv(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wv(vbool8_t mask,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wv(vbool4_t mask,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wv(vbool2_t mask,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wv(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wv(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wv(vbool16_t mask,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wv(vbool8_t mask,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wv(vbool4_t mask,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wv(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wv(vbool32_t mask,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wv(vbool16_t mask,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wv(vbool8_t mask,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
216
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-3.C
Normal file
216
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv-3.C
Normal file
|
|
@ -0,0 +1,216 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wv(vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wv(vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wv(vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wv(vuint16m2_t op1,vuint8m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wv(vuint16m4_t op1,vuint8m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wv(vuint16m8_t op1,vuint8m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wv(vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wv(vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wv(vuint32m2_t op1,vuint16m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wv(vuint32m4_t op1,vuint16m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wv(vuint32m8_t op1,vuint16m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wv(vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wv(vuint64m2_t op1,vuint32m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wv(vuint64m4_t op1,vuint32m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wv(vuint64m8_t op1,vuint32m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wv(vbool64_t mask,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wv(vbool32_t mask,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wv(vbool16_t mask,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wv(vbool8_t mask,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wv(vbool4_t mask,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wv(vbool2_t mask,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wv(vbool64_t mask,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wv(vbool32_t mask,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wv(vbool16_t mask,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wv(vbool8_t mask,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wv(vbool4_t mask,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wv(vbool64_t mask,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wv(vbool32_t mask,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wv(vbool16_t mask,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wv(vbool8_t mask,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv(mask,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-1.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-1.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wv_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wv_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wv_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wv_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wv_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wv_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wv_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wv_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wv_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wv_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wv_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wv_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wv_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wv_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wv_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-2.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-2.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wv_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wv_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wv_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wv_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wv_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wv_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wv_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wv_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wv_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wv_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wv_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wv_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wv_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wv_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wv_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-3.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_mu-3.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wv_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wv_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wv_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wv_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wv_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wv_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wv_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wv_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wv_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wv_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wv_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wv_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wv_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wv_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wv_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_mu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-1.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-1.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wv_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wv_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wv_tu(vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wv_tu(vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wv_tu(vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wv_tu(vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wv_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wv_tu(vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wv_tu(vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wv_tu(vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wv_tu(vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wv_tu(vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wv_tu(vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wv_tu(vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wv_tu(vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-2.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-2.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wv_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wv_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wv_tu(vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wv_tu(vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wv_tu(vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wv_tu(vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wv_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wv_tu(vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wv_tu(vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wv_tu(vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wv_tu(vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wv_tu(vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wv_tu(vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wv_tu(vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wv_tu(vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-3.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tu-3.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wv_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wv_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wv_tu(vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wv_tu(vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wv_tu(vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wv_tu(vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wv_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wv_tu(vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wv_tu(vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wv_tu(vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wv_tu(vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wv_tu(vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wv_tu(vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wv_tu(vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wv_tu(vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tu(merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-1.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-1.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wv_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wv_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wv_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wv_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wv_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wv_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wv_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wv_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wv_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wv_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wv_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wv_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wv_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wv_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wv_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-2.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-2.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wv_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wv_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wv_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wv_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wv_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wv_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wv_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wv_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wv_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wv_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wv_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wv_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wv_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wv_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wv_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-3.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tum-3.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wv_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wv_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wv_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wv_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wv_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wv_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wv_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wv_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wv_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wv_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wv_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wv_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wv_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wv_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wv_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tum(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-1.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-1.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wv_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wv_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wv_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wv_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wv_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wv_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wv_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wv_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wv_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wv_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wv_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wv_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wv_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wv_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wv_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-2.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-2.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wv_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wv_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wv_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wv_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wv_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wv_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wv_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wv_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wv_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wv_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wv_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wv_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wv_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wv_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wv_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-3.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wv_tumu-3.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wv_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,vuint8mf8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wv_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,vuint8mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wv_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,vuint8mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wv_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,vuint8m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wv_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,vuint8m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wv_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,vuint8m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wv_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,vuint16mf4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wv_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,vuint16mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wv_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,vuint16m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wv_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,vuint16m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wv_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,vuint16m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wv_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,vuint32mf2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wv_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,vuint32m1_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wv_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,vuint32m2_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wv_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,vuint32m4_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wv_tumu(mask,merge,op1,op2,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} 1 } } */
|
||||
216
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-1.C
Normal file
216
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-1.C
Normal file
|
|
@ -0,0 +1,216 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wx(vuint16mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wx(vuint16mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wx(vuint16m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wx(vuint16m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wx(vuint16m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wx(vuint16m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wx(vuint32mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wx(vuint32m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wx(vuint32m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wx(vuint32m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wx(vuint32m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wx(vuint64m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wx(vuint64m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wx(vuint64m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wx(vuint64m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wx(vbool64_t mask,vuint16mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wx(vbool32_t mask,vuint16mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wx(vbool16_t mask,vuint16m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wx(vbool8_t mask,vuint16m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wx(vbool4_t mask,vuint16m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wx(vbool2_t mask,vuint16m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wx(vbool64_t mask,vuint32mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wx(vbool32_t mask,vuint32m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wx(vbool16_t mask,vuint32m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wx(vbool8_t mask,vuint32m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wx(vbool4_t mask,vuint32m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wx(vbool64_t mask,vuint64m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wx(vbool32_t mask,vuint64m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wx(vbool16_t mask,vuint64m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wx(vbool8_t mask,vuint64m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
216
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-2.C
Normal file
216
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-2.C
Normal file
|
|
@ -0,0 +1,216 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wx(vuint16mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wx(vuint16mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wx(vuint16m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wx(vuint16m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wx(vuint16m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wx(vuint16m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wx(vuint32mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wx(vuint32m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wx(vuint32m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wx(vuint32m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wx(vuint32m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wx(vuint64m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wx(vuint64m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wx(vuint64m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wx(vuint64m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wx(vbool64_t mask,vuint16mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wx(vbool32_t mask,vuint16mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wx(vbool16_t mask,vuint16m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wx(vbool8_t mask,vuint16m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wx(vbool4_t mask,vuint16m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wx(vbool2_t mask,vuint16m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wx(vbool64_t mask,vuint32mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wx(vbool32_t mask,vuint32m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wx(vbool16_t mask,vuint32m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wx(vbool8_t mask,vuint32m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wx(vbool4_t mask,vuint32m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wx(vbool64_t mask,vuint64m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wx(vbool32_t mask,vuint64m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wx(vbool16_t mask,vuint64m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wx(vbool8_t mask,vuint64m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
216
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-3.C
Normal file
216
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx-3.C
Normal file
|
|
@ -0,0 +1,216 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wx(vuint16mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wx(vuint16mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wx(vuint16m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wx(vuint16m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wx(vuint16m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wx(vuint16m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wx(vuint32mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wx(vuint32m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wx(vuint32m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wx(vuint32m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wx(vuint32m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wx(vuint64m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wx(vuint64m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wx(vuint64m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wx(vuint64m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wx(vbool64_t mask,vuint16mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wx(vbool32_t mask,vuint16mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wx(vbool16_t mask,vuint16m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wx(vbool8_t mask,vuint16m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wx(vbool4_t mask,vuint16m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wx(vbool2_t mask,vuint16m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wx(vbool64_t mask,vuint32mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wx(vbool32_t mask,vuint32m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wx(vbool16_t mask,vuint32m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wx(vbool8_t mask,vuint32m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wx(vbool4_t mask,vuint32m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wx(vbool64_t mask,vuint64m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wx(vbool32_t mask,vuint64m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wx(vbool16_t mask,vuint64m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wx(vbool8_t mask,vuint64m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx(mask,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-1.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-1.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wx_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wx_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wx_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wx_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wx_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wx_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wx_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wx_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wx_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wx_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wx_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wx_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wx_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wx_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wx_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-2.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-2.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wx_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wx_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wx_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wx_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wx_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wx_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wx_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wx_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wx_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wx_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wx_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wx_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wx_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wx_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wx_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-3.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_mu-3.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wx_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wx_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wx_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wx_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wx_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wx_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wx_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wx_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wx_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wx_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wx_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wx_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wx_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wx_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wx_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_mu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-1.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-1.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wx_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wx_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wx_tu(vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wx_tu(vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wx_tu(vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wx_tu(vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wx_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wx_tu(vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wx_tu(vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wx_tu(vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wx_tu(vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wx_tu(vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wx_tu(vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wx_tu(vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wx_tu(vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-2.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-2.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wx_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wx_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wx_tu(vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wx_tu(vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wx_tu(vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wx_tu(vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wx_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wx_tu(vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wx_tu(vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wx_tu(vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wx_tu(vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wx_tu(vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wx_tu(vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wx_tu(vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wx_tu(vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-3.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tu-3.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wx_tu(vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wx_tu(vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wx_tu(vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wx_tu(vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wx_tu(vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wx_tu(vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wx_tu(vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wx_tu(vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wx_tu(vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wx_tu(vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wx_tu(vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wx_tu(vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wx_tu(vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wx_tu(vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wx_tu(vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tu(merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-1.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-1.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wx_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wx_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wx_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wx_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wx_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wx_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wx_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wx_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wx_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wx_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wx_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wx_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wx_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wx_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wx_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-2.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-2.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wx_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wx_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wx_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wx_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wx_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wx_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wx_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wx_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wx_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wx_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wx_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wx_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wx_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wx_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wx_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-3.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tum-3.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wx_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wx_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wx_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wx_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wx_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wx_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wx_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wx_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wx_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wx_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wx_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wx_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wx_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wx_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wx_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tum(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-1.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-1.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wx_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wx_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wx_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wx_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wx_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wx_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wx_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wx_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wx_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wx_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wx_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wx_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wx_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wx_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wx_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,vl);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-2.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-2.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wx_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wx_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wx_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wx_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wx_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wx_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wx_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wx_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wx_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wx_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wx_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wx_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wx_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wx_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wx_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,31);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-3.C
Normal file
111
gcc/testsuite/g++.target/riscv/rvv/base/vwsubu_wx_tumu-3.C
Normal file
|
|
@ -0,0 +1,111 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-march=rv32gcv -mabi=ilp32 -O3 -fno-schedule-insns -fno-schedule-insns2" } */
|
||||
|
||||
#include "riscv_vector.h"
|
||||
|
||||
vuint16mf4_t test___riscv_vwsubu_wx_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16mf2_t test___riscv_vwsubu_wx_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m1_t test___riscv_vwsubu_wx_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m2_t test___riscv_vwsubu_wx_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m4_t test___riscv_vwsubu_wx_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint16m8_t test___riscv_vwsubu_wx_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t op1,uint8_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32mf2_t test___riscv_vwsubu_wx_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m1_t test___riscv_vwsubu_wx_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m2_t test___riscv_vwsubu_wx_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m4_t test___riscv_vwsubu_wx_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint32m8_t test___riscv_vwsubu_wx_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t op1,uint16_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m1_t test___riscv_vwsubu_wx_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m2_t test___riscv_vwsubu_wx_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m4_t test___riscv_vwsubu_wx_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
vuint64m8_t test___riscv_vwsubu_wx_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t op1,uint32_t op2,size_t vl)
|
||||
{
|
||||
return __riscv_vwsubu_wx_tumu(mask,merge,op1,0xAA,32);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vwsubu\.wx\s+v[0-9]+,\s*v[0-9]+,\s*[a-x0-9]+,\s*v0.t\s+} 1 } } */
|
||||
Loading…
Add table
Reference in a new issue