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re PR tree-optimization/71625 (missing strlen optimization on different array initialization style)

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2018-10-05  Steve Ellcey  <sellcey@cavium.com>

	PR tree-optimization/71625
	* /gcc.target/aarch64/vclz.c (test_vclz_s8): Add noinline attribute.
	(test_vclz_s16): Ditto.
	(test_vclz_s32): Ditto.
	(test_vclzq_s8): Ditto.
	(test_vclzq_s16): Ditto.
	(test_vclzq_s32): Ditto.
	(test_vclz_u8): Ditto.
	(test_vclz_u16): Ditto.
	(test_vclz_u32): Ditto.
	(test_vclzq_u8): Ditto.
	(test_vclzq_u16): Ditto.
	(test_vclzq_u32): Ditto.
	* gcc.target/aarch64/vneg_s.c (test_vneg_s8): Ditto.
	(test_vneg_s16): Ditto.
	(test_vneg_s32): Ditto.
	(test_vneg_s64): Ditto.
	(test_vnegd_s64): Ditto.
	(test_vnegq_s8): Ditto.
	(test_vnegq_s16): Ditto.
	(test_vnegq_s32): Ditto.
	(test_vnegq_s64): Ditto.

From-SVN: r264874
This commit is contained in:
Steve Ellcey 2018-10-05 15:26:40 +00:00 • committed by Steve Ellcey
parent cbba2e1e47
commit 825e64583e
3 changed files with 46 additions and 21 deletions
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25
gcc/testsuite/ChangeLog
View file

@ -1,3 +1,28 @@
2018-10-05 Steve Ellcey <sellcey@cavium.com>
PR tree-optimization/71625
* /gcc.target/aarch64/vclz.c (test_vclz_s8): Add noinline attribute.
(test_vclz_s16): Ditto.
(test_vclz_s32): Ditto.
(test_vclzq_s8): Ditto.
(test_vclzq_s16): Ditto.
(test_vclzq_s32): Ditto.
(test_vclz_u8): Ditto.
(test_vclz_u16): Ditto.
(test_vclz_u32): Ditto.
(test_vclzq_u8): Ditto.
(test_vclzq_u16): Ditto.
(test_vclzq_u32): Ditto.
* gcc.target/aarch64/vneg_s.c (test_vneg_s8): Ditto.
(test_vneg_s16): Ditto.
(test_vneg_s32): Ditto.
(test_vneg_s64): Ditto.
(test_vnegd_s64): Ditto.
(test_vnegq_s8): Ditto.
(test_vnegq_s16): Ditto.
(test_vnegq_s32): Ditto.
(test_vnegq_s64): Ditto.
2018-10-05 Segher Boessenkool <segher@kernel.crashing.org>
PR target/87509

24
gcc/testsuite/gcc.target/aarch64/vclz.c
View file

@ -75,7 +75,7 @@ extern void abort (void);
if (a [i] != b [i]) \
return 1;
int
int __attribute__ ((noinline))
test_vclz_s8 ()
{
int i;
@ -107,7 +107,7 @@ test_vclz_s8 ()
/* Double scan-assembler-times to take account of unsigned functions. */
/* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b" 4 } } */
int
int __attribute__ ((noinline))
test_vclz_s16 ()
{
int i;
@ -138,7 +138,7 @@ test_vclz_s16 ()
/* Double scan-assembler-times to take account of unsigned functions. */
/* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.4h, v\[0-9\]+\.4h" 10} } */
int
int __attribute__ ((noinline))
test_vclz_s32 ()
{
int i;
@ -205,7 +205,7 @@ test_vclz_s32 ()
/* Double scan-assembler-times to take account of unsigned functions. */
/* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" 34 } } */
int
int __attribute__ ((noinline))
test_vclzq_s8 ()
{
int i;
@ -226,7 +226,7 @@ test_vclzq_s8 ()
/* Double scan-assembler-times to take account of unsigned functions. */
/* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 2 } } */
int
int __attribute__ ((noinline))
test_vclzq_s16 ()
{
int i;
@ -262,7 +262,7 @@ test_vclzq_s16 ()
/* Double scan-assembler-times to take account of unsigned functions. */
/* { dg-final { scan-assembler-times "clz\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h" 6 } } */
int
int __attribute__ ((noinline))
test_vclzq_s32 ()
{
int i;
@ -303,7 +303,7 @@ test_vclzq_s32 ()
/* Unsigned versions. */
int
int __attribute__ ((noinline))
test_vclz_u8 ()
{
int i;
@ -331,7 +331,7 @@ test_vclz_u8 ()
/* ASM scan near test for signed version. */
int
int __attribute__ ((noinline))
test_vclz_u16 ()
{
int i;
@ -361,7 +361,7 @@ test_vclz_u16 ()
/* ASM scan near test for signed version. */
int
int __attribute__ ((noinline))
test_vclz_u32 ()
{
int i;
@ -427,7 +427,7 @@ test_vclz_u32 ()
/* ASM scan near test for signed version. */
int
int __attribute__ ((noinline))
test_vclzq_u8 ()
{
int i;
@ -448,7 +448,7 @@ test_vclzq_u8 ()
/* ASM scan near test for signed version. */
int
int __attribute__ ((noinline))
test_vclzq_u16 ()
{
int i;
@ -485,7 +485,7 @@ test_vclzq_u16 ()
/* ASM scan near test for signed version. */
int
int __attribute__ ((noinline))
test_vclzq_u32 ()
{
int i;

18
gcc/testsuite/gcc.target/aarch64/vneg_s.c
View file

@ -87,7 +87,7 @@ extern void abort (void);
force_simd (res); \
}
int
int __attribute__ ((noinline))
test_vneg_s8 ()
{
int8x8_t a;
@ -107,7 +107,7 @@ test_vneg_s8 ()
/* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.8b, v\[0-9\]+\.8b" 1 } } */
int
int __attribute__ ((noinline))
test_vneg_s16 ()
{
int16x4_t a;
@ -127,7 +127,7 @@ test_vneg_s16 ()
/* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.4h, v\[0-9\]+\.4h" 2 } } */
int
int __attribute__ ((noinline))
test_vneg_s32 ()
{
int32x2_t a;
@ -153,7 +153,7 @@ test_vneg_s32 ()
/* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.2s, v\[0-9\]+\.2s" 4 } } */
int
int __attribute__ ((noinline))
test_vneg_s64 ()
{
int64x1_t a;
@ -189,7 +189,7 @@ test_vneg_s64 ()
return 0;
}
int
int __attribute__ ((noinline))
test_vnegd_s64 ()
{
int64_t a, b;
@ -208,7 +208,7 @@ test_vnegd_s64 ()
/* { dg-final { scan-assembler-times "neg\\td\[0-9\]+, d\[0-9\]+" 16 } } */
int
int __attribute__ ((noinline))
test_vnegq_s8 ()
{
int8x16_t a;
@ -231,7 +231,7 @@ test_vnegq_s8 ()
/* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.16b, v\[0-9\]+\.16b" 1 } } */
int
int __attribute__ ((noinline))
test_vnegq_s16 ()
{
int16x8_t a;
@ -251,7 +251,7 @@ test_vnegq_s16 ()
/* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.8h, v\[0-9\]+\.8h" 1 } } */
int
int __attribute__ ((noinline))
test_vnegq_s32 ()
{
int32x4_t a;
@ -271,7 +271,7 @@ test_vnegq_s32 ()
/* { dg-final { scan-assembler-times "neg\\tv\[0-9\]+\.4s, v\[0-9\]+\.4s" 2 } } */
int
int __attribute__ ((noinline))
test_vnegq_s64 ()
{
int64x2_t a;