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amdgcn: Fix assembler version incompatibility

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This is another case of the global_load instruction format changing in LLVM
(because they fixed a bug).  The configure test is already in place to detect
what is needed.

gcc/ChangeLog:

	* config/gcn/gcn-valu.md (gather<mode>_insn_2offsets<exec>): Apply
	HAVE_GCN_ASM_GLOBAL_LOAD_FIXED.
	(scatter<mode>_insn_2offsets<exec_scatter>): Likewise.
This commit is contained in:
Andrew Stubbs 2021-09-30 17:50:33 +01:00
parent 205dafb6ed
commit 81c362c7c2
1 changed files with 12 additions and 4 deletions
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8
gcc/config/gcn/gcn-valu.md
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@ -827,6 +827,10 @@
/* Work around assembler bug in which a 64-bit register is expected, /* Work around assembler bug in which a 64-bit register is expected,
but a 32-bit value would be correct. */ but a 32-bit value would be correct. */
int reg = REGNO (operands[2]) - FIRST_VGPR_REG; int reg = REGNO (operands[2]) - FIRST_VGPR_REG;
if (HAVE_GCN_ASM_GLOBAL_LOAD_FIXED)
sprintf (buf, "global_load%%o0\t%%0, v%d, %%1 offset:%%3%s\;"
"s_waitcnt\tvmcnt(0)", reg, glc);
else
sprintf (buf, "global_load%%o0\t%%0, v[%d:%d], %%1 offset:%%3%s\;" sprintf (buf, "global_load%%o0\t%%0, v[%d:%d], %%1 offset:%%3%s\;"
"s_waitcnt\tvmcnt(0)", reg, reg + 1, glc); "s_waitcnt\tvmcnt(0)", reg, reg + 1, glc);
} }
@ -958,6 +962,10 @@
/* Work around assembler bug in which a 64-bit register is expected, /* Work around assembler bug in which a 64-bit register is expected,
but a 32-bit value would be correct. */ but a 32-bit value would be correct. */
int reg = REGNO (operands[1]) - FIRST_VGPR_REG; int reg = REGNO (operands[1]) - FIRST_VGPR_REG;
if (HAVE_GCN_ASM_GLOBAL_LOAD_FIXED)
sprintf (buf, "global_store%%s3\tv%d, %%3, %%0 offset:%%2%s",
reg, glc);
else
sprintf (buf, "global_store%%s3\tv[%d:%d], %%3, %%0 offset:%%2%s", sprintf (buf, "global_store%%s3\tv[%d:%d], %%3, %%0 offset:%%2%s",
reg, reg + 1, glc); reg, reg + 1, glc);
} }