FreeChainXenon/gcc
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

re PR target/26255 (internal compiler error: in reload_cse_simplify_operands, at postreload.c:391)

Browse source 
PR target/26255
	* pa.md: Create separate HI and QI move patterns for 32-bit and 64-bit
	with hardware float support, and software float support.  Add fcpy
	alternative to hardware patterns.  Add alternatives to copy between
	general and floating-point registers to the 32-bit pattern.
	* pa.c (pa_secondary_reload): Don't abort if reload tries to find a
	secondary reload to load a QI or HI mode constant into a floating
	point register. 
	* pa32-regs.h (VALID_FP_MODE_P): Allow QImode and HImode.
	* pa64-regs.h (VALID_FP_MODE_P): Likewise.

From-SVN: r111214
This commit is contained in:
John David Anglin 2006-02-17 22:19:05 +00:00 • committed by John David Anglin
parent 1435ba17b5
commit 7e646101de
5 changed files with 123 additions and 11 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

13
gcc/ChangeLog
View file

@ -1,3 +1,16 @@
2006-02-17 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
PR target/26255
* pa.md: Create separate HI and QI move patterns for 32-bit and 64-bit
with hardware float support, and software float support. Add fcpy
alternative to hardware patterns. Add alternatives to copy between
general and floating-point registers to the 32-bit pattern.
* pa.c (pa_secondary_reload): Don't abort if reload tries to find a
secondary reload to load a QI or HI mode constant into a floating
point register.
* pa32-regs.h (VALID_FP_MODE_P): Allow QImode and HImode.
* pa64-regs.h (VALID_FP_MODE_P): Likewise.
2006-02-17 Andrew Pinski <pinskia@physics.uc.edu>
PR target/26272

3
gcc/config/pa/pa.c
View file

@ -5630,11 +5630,10 @@ pa_secondary_reload (bool in_p, rtx x, enum reg_class class,
/* Trying to load a constant into a FP register during PIC code
generation requires %r1 as a scratch register. */
if (flag_pic
&& GET_MODE_CLASS (mode) == MODE_INT
&& (mode == SImode || mode == DImode)
&& FP_REG_CLASS_P (class)
&& (GET_CODE (x) == CONST_INT || GET_CODE (x) == CONST_DOUBLE))
{
gcc_assert (mode == SImode || mode == DImode);
sri->icode = (mode == SImode ? CODE_FOR_reload_insi_r1
: CODE_FOR_reload_indi_r1);
return NO_REGS;

106
gcc/config/pa/pa.md
View file

@ -2947,13 +2947,62 @@
DONE;
}")
(define_insn ""
[(set (match_operand:HI 0 "move_dest_operand"
"=r,r,r,r,r,Q,!*q,!r,!*f,!r,!f")
(match_operand:HI 1 "move_src_operand"
"r,J,N,K,RQ,rM,!rM,!*q,!*fM,!f,!r"))]
"(register_operand (operands[0], HImode)
|| reg_or_0_operand (operands[1], HImode))
&& !TARGET_SOFT_FLOAT
&& !TARGET_64BIT"
"@
copy %1,%0
ldi %1,%0
ldil L'%1,%0
{zdepi|depwi,z} %Z1,%0
ldh%M1 %1,%0
sth%M0 %r1,%0
mtsar %r1
{mfctl|mfctl,w} %sar,%0
fcpy,sgl %f1,%0
{fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
{stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
[(set_attr "type" "move,move,move,shift,load,store,move,move,move,move,move")
(set_attr "pa_combine_type" "addmove")
(set_attr "length" "4,4,4,4,4,4,4,4,4,8,8")])
(define_insn ""
[(set (match_operand:HI 0 "move_dest_operand"
"=r,r,r,r,r,Q,!*q,!r,!*f")
(match_operand:HI 1 "move_src_operand"
"r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
"(register_operand (operands[0], HImode)
|| reg_or_0_operand (operands[1], HImode))
&& !TARGET_SOFT_FLOAT
&& TARGET_64BIT"
"@
copy %1,%0
ldi %1,%0
ldil L'%1,%0
{zdepi|depwi,z} %Z1,%0
ldh%M1 %1,%0
sth%M0 %r1,%0
mtsar %r1
{mfctl|mfctl,w} %sar,%0
fcpy,sgl %f1,%0"
[(set_attr "type" "move,move,move,shift,load,store,move,move,move")
(set_attr "pa_combine_type" "addmove")
(set_attr "length" "4,4,4,4,4,4,4,4,4")])
(define_insn ""
[(set (match_operand:HI 0 "move_dest_operand"
"=r,r,r,r,r,Q,!*q,!r")
(match_operand:HI 1 "move_src_operand"
"r,J,N,K,RQ,rM,!rM,!*q"))]
"register_operand (operands[0], HImode)
|| reg_or_0_operand (operands[1], HImode)"
"(register_operand (operands[0], HImode)
|| reg_or_0_operand (operands[1], HImode))
&& TARGET_SOFT_FLOAT"
"@
copy %1,%0
ldi %1,%0
@ -3071,13 +3120,62 @@
DONE;
}")
(define_insn ""
[(set (match_operand:QI 0 "move_dest_operand"
"=r,r,r,r,r,Q,!*q,!r,!*f,!r,!f")
(match_operand:QI 1 "move_src_operand"
"r,J,N,K,RQ,rM,!rM,!*q,!*fM,!f,!r"))]
"(register_operand (operands[0], QImode)
|| reg_or_0_operand (operands[1], QImode))
&& !TARGET_SOFT_FLOAT
&& !TARGET_64BIT"
"@
copy %1,%0
ldi %1,%0
ldil L'%1,%0
{zdepi|depwi,z} %Z1,%0
ldb%M1 %1,%0
stb%M0 %r1,%0
mtsar %r1
{mfctl|mfctl,w} %%sar,%0
fcpy,sgl %f1,%0
{fstws|fstw} %1,-16(%%sp)\n\t{ldws|ldw} -16(%%sp),%0
{stws|stw} %1,-16(%%sp)\n\t{fldws|fldw} -16(%%sp),%0"
[(set_attr "type" "move,move,move,shift,load,store,move,move,move,move,move")
(set_attr "pa_combine_type" "addmove")
(set_attr "length" "4,4,4,4,4,4,4,4,4,8,8")])
(define_insn ""
[(set (match_operand:QI 0 "move_dest_operand"
"=r,r,r,r,r,Q,!*q,!r,!*f")
(match_operand:QI 1 "move_src_operand"
"r,J,N,K,RQ,rM,!rM,!*q,!*fM"))]
"(register_operand (operands[0], QImode)
|| reg_or_0_operand (operands[1], QImode))
&& !TARGET_SOFT_FLOAT
&& TARGET_64BIT"
"@
copy %1,%0
ldi %1,%0
ldil L'%1,%0
{zdepi|depwi,z} %Z1,%0
ldb%M1 %1,%0
stb%M0 %r1,%0
mtsar %r1
{mfctl|mfctl,w} %%sar,%0
fcpy,sgl %f1,%0"
[(set_attr "type" "move,move,move,shift,load,store,move,move,move")
(set_attr "pa_combine_type" "addmove")
(set_attr "length" "4,4,4,4,4,4,4,4,4")])
(define_insn ""
[(set (match_operand:QI 0 "move_dest_operand"
"=r,r,r,r,r,Q,!*q,!r")
(match_operand:QI 1 "move_src_operand"
"r,J,N,K,RQ,rM,!rM,!*q"))]
"register_operand (operands[0], QImode)
|| reg_or_0_operand (operands[1], QImode)"
"(register_operand (operands[0], QImode)
|| reg_or_0_operand (operands[1], QImode))
&& TARGET_SOFT_FLOAT"
"@
copy %1,%0
ldi %1,%0

3
gcc/config/pa/pa32-regs.h
View file

@ -172,7 +172,8 @@
#define VALID_FP_MODE_P(MODE) \
((MODE) == SFmode || (MODE) == DFmode \
|| (MODE) == SCmode || (MODE) == DCmode \
|| (MODE) == SImode || (TARGET_PA_11 && (MODE) == DImode))
|| (MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
|| (TARGET_PA_11 && (MODE) == DImode))
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.

9
gcc/config/pa/pa64-regs.h
View file

@ -154,10 +154,11 @@ Boston, MA 02110-1301, USA. */
((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
/* These are the valid FP modes. */
#define VALID_FP_MODE_P(MODE) \
((MODE) == SFmode || (MODE) == DFmode \
|| (MODE) == SCmode || (MODE) == DCmode \
|| (MODE) == SImode || (MODE) == DImode)
#define VALID_FP_MODE_P(MODE) \
((MODE) == SFmode || (MODE) == DFmode \
|| (MODE) == SCmode || (MODE) == DCmode \
|| (MODE) == QImode || (MODE) == HImode || (MODE) == SImode \
|| (MODE) == DImode)
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
On the HP-PA, the cpu registers can hold any mode. We