Enable _Float16 type for TARGET_SSE2 and above.
gcc/ChangeLog: * config/i386/i386-modes.def (FLOAT_MODE): Define ieee HFmode. * config/i386/i386.c (enum x86_64_reg_class): Add X86_64_SSEHF_CLASS. (merge_classes): Handle X86_64_SSEHF_CLASS. (examine_argument): Ditto. (construct_container): Ditto. (classify_argument): Ditto, and set HFmode/HCmode to X86_64_SSEHF_CLASS. (function_value_32): Return _FLoat16/Complex Float16 by %xmm0. (function_value_64): Return _Float16/Complex Float16 by SSE register. (ix86_print_operand): Handle CONST_DOUBLE HFmode. (ix86_secondary_reload): Require gpr as intermediate register to store _Float16 from sse register when sse4 is not available. (ix86_libgcc_floating_mode_supported_p): Enable _FLoat16 under sse2. (ix86_scalar_mode_supported_p): Ditto. (TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P): Defined. * config/i386/i386.h (VALID_SSE2_REG_MODE): Add HFmode. (VALID_INT_MODE_P): Add HFmode and HCmode. * config/i386/i386.md (*pushhf_rex64): New define_insn. (*pushhf): Ditto. (*movhf_internal): Ditto. * doc/extend.texi (Half-Precision Floating Point): Documemt _Float16 for x86. gcc/lto/ChangeLog: * lto-lang.c (lto_type_for_mode): Return float16_type_node when mode == TYPE_MODE (float16_type_node). gcc/testsuite/ChangeLog * gcc.target/i386/sse2-float16-1.c: New test. * gcc.target/i386/sse2-float16-2.c: Ditto. * gcc.target/i386/sse2-float16-3.c: Ditto. * gcc.target/i386/float16-5.c: New test.
This commit is contained in:
liuhongt
parent
e42d2d2a20
commit
7cbc870c49
10 changed files with 269 additions and 8 deletions
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@ -23,6 +23,7 @@ along with GCC; see the file COPYING3. If not see
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FRACTIONAL_FLOAT_MODE (XF, 80, 12, ieee_extended_intel_96_format);
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FLOAT_MODE (TF, 16, ieee_quad_format);
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FLOAT_MODE (HF, 2, ieee_half_format);
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/* In ILP32 mode, XFmode has size 12 and alignment 4.
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In LP64 mode, XFmode has size and alignment 16. */
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@ -387,6 +387,7 @@ enum x86_64_reg_class
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X86_64_INTEGER_CLASS,
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X86_64_INTEGERSI_CLASS,
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X86_64_SSE_CLASS,
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X86_64_SSEHF_CLASS,
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X86_64_SSESF_CLASS,
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X86_64_SSEDF_CLASS,
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X86_64_SSEUP_CLASS,
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@ -2027,8 +2028,10 @@ merge_classes (enum x86_64_reg_class class1, enum x86_64_reg_class class2)
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return X86_64_MEMORY_CLASS;
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/* Rule #4: If one of the classes is INTEGER, the result is INTEGER. */
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if ((class1 == X86_64_INTEGERSI_CLASS && class2 == X86_64_SSESF_CLASS)
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|| (class2 == X86_64_INTEGERSI_CLASS && class1 == X86_64_SSESF_CLASS))
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if ((class1 == X86_64_INTEGERSI_CLASS
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&& (class2 == X86_64_SSESF_CLASS || class2 == X86_64_SSEHF_CLASS))
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|| (class2 == X86_64_INTEGERSI_CLASS
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&& (class1 == X86_64_SSESF_CLASS || class1 == X86_64_SSEHF_CLASS)))
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return X86_64_INTEGERSI_CLASS;
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if (class1 == X86_64_INTEGER_CLASS || class1 == X86_64_INTEGERSI_CLASS
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|| class2 == X86_64_INTEGER_CLASS || class2 == X86_64_INTEGERSI_CLASS)
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@ -2182,6 +2185,8 @@ classify_argument (machine_mode mode, const_tree type,
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/* The partial classes are now full classes. */
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if (subclasses[0] == X86_64_SSESF_CLASS && bytes != 4)
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subclasses[0] = X86_64_SSE_CLASS;
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if (subclasses[0] == X86_64_SSEHF_CLASS && bytes != 2)
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subclasses[0] = X86_64_SSE_CLASS;
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if (subclasses[0] == X86_64_INTEGERSI_CLASS
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&& !((bit_offset % 64) == 0 && bytes == 4))
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subclasses[0] = X86_64_INTEGER_CLASS;
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@ -2354,6 +2359,12 @@ classify_argument (machine_mode mode, const_tree type,
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gcc_unreachable ();
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case E_CTImode:
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return 0;
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case E_HFmode:
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if (!(bit_offset % 64))
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classes[0] = X86_64_SSEHF_CLASS;
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else
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classes[0] = X86_64_SSE_CLASS;
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return 1;
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case E_SFmode:
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if (!(bit_offset % 64))
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classes[0] = X86_64_SSESF_CLASS;
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@ -2371,6 +2382,15 @@ classify_argument (machine_mode mode, const_tree type,
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classes[0] = X86_64_SSE_CLASS;
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classes[1] = X86_64_SSEUP_CLASS;
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return 2;
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case E_HCmode:
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classes[0] = X86_64_SSE_CLASS;
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if (!(bit_offset % 64))
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return 1;
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else
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{
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classes[1] = X86_64_SSEHF_CLASS;
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return 2;
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}
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case E_SCmode:
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classes[0] = X86_64_SSE_CLASS;
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if (!(bit_offset % 64))
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@ -2485,6 +2505,7 @@ examine_argument (machine_mode mode, const_tree type, int in_return,
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(*int_nregs)++;
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break;
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case X86_64_SSE_CLASS:
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case X86_64_SSEHF_CLASS:
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case X86_64_SSESF_CLASS:
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case X86_64_SSEDF_CLASS:
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(*sse_nregs)++;
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@ -2584,13 +2605,14 @@ construct_container (machine_mode mode, machine_mode orig_mode,
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/* First construct simple cases. Avoid SCmode, since we want to use
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single register to pass this type. */
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if (n == 1 && mode != SCmode)
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if (n == 1 && mode != SCmode && mode != HCmode)
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switch (regclass[0])
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{
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case X86_64_INTEGER_CLASS:
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case X86_64_INTEGERSI_CLASS:
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return gen_rtx_REG (mode, intreg[0]);
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case X86_64_SSE_CLASS:
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case X86_64_SSEHF_CLASS:
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case X86_64_SSESF_CLASS:
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case X86_64_SSEDF_CLASS:
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if (mode != BLKmode)
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@ -2687,6 +2709,14 @@ construct_container (machine_mode mode, machine_mode orig_mode,
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GEN_INT (i*8));
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intreg++;
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break;
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case X86_64_SSEHF_CLASS:
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exp [nexps++]
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= gen_rtx_EXPR_LIST (VOIDmode,
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gen_rtx_REG (HFmode,
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GET_SSE_REGNO (sse_regno)),
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GEN_INT (i*8));
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sse_regno++;
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break;
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case X86_64_SSESF_CLASS:
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exp [nexps++]
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= gen_rtx_EXPR_LIST (VOIDmode,
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@ -3907,6 +3937,19 @@ function_value_32 (machine_mode orig_mode, machine_mode mode,
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/* Most things go in %eax. */
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regno = AX_REG;
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/* Return _Float16/_Complex _Foat16 by sse register. */
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if (mode == HFmode)
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regno = FIRST_SSE_REG;
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if (mode == HCmode)
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{
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rtx ret = gen_rtx_PARALLEL (mode, rtvec_alloc(1));
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XVECEXP (ret, 0, 0)
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= gen_rtx_EXPR_LIST (VOIDmode,
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gen_rtx_REG (SImode, FIRST_SSE_REG),
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GEN_INT (0));
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return ret;
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}
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/* Override FP return register with %xmm0 for local functions when
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SSE math is enabled or for functions with sseregparm attribute. */
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if ((fn || fntype) && (mode == SFmode || mode == DFmode))
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@ -3943,6 +3986,8 @@ function_value_64 (machine_mode orig_mode, machine_mode mode,
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switch (mode)
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{
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case E_HFmode:
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case E_HCmode:
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case E_SFmode:
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case E_SCmode:
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case E_DFmode:
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@ -13455,6 +13500,15 @@ ix86_print_operand (FILE *file, rtx x, int code)
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(file, addr, MEM_ADDR_SPACE (x), code == 'p' || code == 'P');
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}
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else if (CONST_DOUBLE_P (x) && GET_MODE (x) == HFmode)
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{
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long l = real_to_target (NULL, CONST_DOUBLE_REAL_VALUE (x),
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REAL_MODE_FORMAT (HFmode));
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if (ASSEMBLER_DIALECT == ASM_ATT)
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putc ('$', file);
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fprintf (file, "0x%04x", (unsigned int) l);
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}
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else if (CONST_DOUBLE_P (x) && GET_MODE (x) == SFmode)
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{
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long l;
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@ -19107,6 +19161,16 @@ ix86_secondary_reload (bool in_p, rtx x, reg_class_t rclass,
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return NO_REGS;
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}
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/* Require movement to gpr, and then store to memory. */
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if (mode == HFmode
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&& !TARGET_SSE4_1
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&& SSE_CLASS_P (rclass)
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&& !in_p && MEM_P (x))
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{
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sri->extra_cost = 1;
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return GENERAL_REGS;
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}
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/* This condition handles corner case where an expression involving
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pointers gets vectorized. We're trying to use the address of a
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stack slot as a vector initializer.
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@ -21781,10 +21845,27 @@ ix86_scalar_mode_supported_p (scalar_mode mode)
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return default_decimal_float_supported_p ();
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else if (mode == TFmode)
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return true;
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else if (mode == HFmode && TARGET_SSE2)
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return true;
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else
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return default_scalar_mode_supported_p (mode);
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}
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/* Implement TARGET_LIBGCC_FLOATING_POINT_MODE_SUPPORTED_P - return TRUE
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if MODE is HFmode, and punt to the generic implementation otherwise. */
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static bool
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ix86_libgcc_floating_mode_supported_p (scalar_float_mode mode)
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{
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/* NB: Always return TRUE for HFmode so that the _Float16 type will
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be defined by the C front-end for AVX512FP16 intrinsics. We will
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issue an error in ix86_expand_move for HFmode if AVX512FP16 isn't
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enabled. */
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return ((mode == HFmode && TARGET_SSE2)
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? true
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: default_libgcc_floating_mode_supported_p (mode));
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}
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/* Implements target hook vector_mode_supported_p. */
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static bool
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ix86_vector_mode_supported_p (machine_mode mode)
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@ -24067,6 +24148,10 @@ ix86_run_selftests (void)
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#undef TARGET_SCALAR_MODE_SUPPORTED_P
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#define TARGET_SCALAR_MODE_SUPPORTED_P ix86_scalar_mode_supported_p
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#undef TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P
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#define TARGET_LIBGCC_FLOATING_MODE_SUPPORTED_P \
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ix86_libgcc_floating_mode_supported_p
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#undef TARGET_VECTOR_MODE_SUPPORTED_P
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#define TARGET_VECTOR_MODE_SUPPORTED_P ix86_vector_mode_supported_p
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@ -1025,7 +1025,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
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#define VALID_SSE2_REG_MODE(MODE) \
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((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \
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|| (MODE) == V4QImode || (MODE) == V2HImode || (MODE) == V1SImode \
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|| (MODE) == V2DImode || (MODE) == DFmode)
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|| (MODE) == V2DImode || (MODE) == DFmode || (MODE) == HFmode)
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#define VALID_SSE_REG_MODE(MODE) \
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((MODE) == V1TImode || (MODE) == TImode \
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@ -1054,6 +1054,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
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|| (MODE) == CQImode || (MODE) == CHImode \
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|| (MODE) == CSImode || (MODE) == CDImode \
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|| (MODE) == SDmode || (MODE) == DDmode \
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|| (MODE) == HFmode || (MODE) == HCmode \
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|| (MODE) == V4QImode || (MODE) == V2HImode || (MODE) == V1SImode \
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|| (TARGET_64BIT \
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&& ((MODE) == TImode || (MODE) == CTImode \
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@ -1226,6 +1226,9 @@
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;; All x87 floating point modes
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(define_mode_iterator X87MODEF [SF DF XF])
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;; All x87 floating point modes plus HF
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(define_mode_iterator X87MODEFH [SF DF XF HF])
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;; All SSE floating point modes
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(define_mode_iterator SSEMODEF [SF DF TF])
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(define_mode_attr ssevecmodef [(SF "V4SF") (DF "V2DF") (TF "TF")])
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@ -3134,6 +3137,32 @@
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operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);
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})
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(define_insn "*pushhf_rex64"
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[(set (match_operand:HF 0 "push_operand" "=X,X")
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(match_operand:HF 1 "nonmemory_no_elim_operand" "r,x"))]
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"TARGET_64BIT"
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{
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/* Anything else should be already split before reg-stack. */
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gcc_assert (which_alternative == 0);
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return "push{q}\t%q1";
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}
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[(set_attr "isa" "*,sse4")
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(set_attr "type" "push,multi")
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(set_attr "mode" "DI,TI")])
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(define_insn "*pushhf"
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[(set (match_operand:HF 0 "push_operand" "=X,X")
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(match_operand:HF 1 "general_no_elim_operand" "rmF,x"))]
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"!TARGET_64BIT"
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{
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/* Anything else should be already split before reg-stack. */
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gcc_assert (which_alternative == 0);
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return "push{l}\t%k1";
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}
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[(set_attr "isa" "*,sse4")
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(set_attr "type" "push,multi")
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(set_attr "mode" "SI,TI")])
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(define_insn "*pushsf_rex64"
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[(set (match_operand:SF 0 "push_operand" "=X,X,X")
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(match_operand:SF 1 "nonmemory_no_elim_operand" "f,rF,v"))]
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@ -3162,10 +3191,11 @@
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(set_attr "unit" "i387,*,*")
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(set_attr "mode" "SF,SI,SF")])
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(define_mode_iterator MODESH [SF HF])
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;; %%% Kill this when call knows how to work this out.
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(define_split
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[(set (match_operand:SF 0 "push_operand")
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(match_operand:SF 1 "any_fp_register_operand"))]
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[(set (match_operand:MODESH 0 "push_operand")
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(match_operand:MODESH 1 "any_fp_register_operand"))]
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"reload_completed"
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[(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
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(set (match_dup 0) (match_dup 1))]
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@ -3213,8 +3243,8 @@
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"ix86_expand_move (TFmode, operands); DONE;")
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(define_expand "mov<mode>"
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[(set (match_operand:X87MODEF 0 "nonimmediate_operand")
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(match_operand:X87MODEF 1 "general_operand"))]
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[(set (match_operand:X87MODEFH 0 "nonimmediate_operand")
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(match_operand:X87MODEFH 1 "general_operand"))]
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""
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"ix86_expand_move (<MODE>mode, operands); DONE;")
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@ -3650,6 +3680,86 @@
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]
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(const_string "*")))])
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(define_insn "*movhf_internal"
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[(set (match_operand:HF 0 "nonimmediate_operand"
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"=?r,?m,v,v,?r,m,?v,v")
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(match_operand:HF 1 "general_operand"
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"rmF,rF,C,v, v,v, r,m"))]
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"!(MEM_P (operands[0]) && MEM_P (operands[1]))
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&& (lra_in_progress
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|| reload_completed
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|| !CONST_DOUBLE_P (operands[1])
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|| (TARGET_SSE && TARGET_SSE_MATH
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&& standard_sse_constant_p (operands[1], HFmode) == 1)
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|| memory_operand (operands[0], HFmode))"
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{
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switch (get_attr_type (insn))
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{
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case TYPE_IMOV:
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return "mov{w}\t{%1, %0|%0, %1}";
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case TYPE_SSELOG1:
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return standard_sse_constant_opcode (insn, operands);
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case TYPE_SSEMOV:
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return ix86_output_ssemov (insn, operands);
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case TYPE_SSELOG:
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if (SSE_REG_P (operands[0]))
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return MEM_P (operands[1])
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? "pinsrw\t{$0, %1, %0|%0, %1, 0}"
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: "pinsrw\t{$0, %k1, %0|%0, %k1, 0}";
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else
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return MEM_P (operands[1])
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? "pextrw\t{$0, %1, %0|%0, %1, 0}"
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: "pextrw\t{$0, %1, %k0|%k0, %k1, 0}";
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default:
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gcc_unreachable ();
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}
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}
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[(set (attr "isa")
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(cond [(eq_attr "alternative" "2,3,4,6,7")
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(const_string "sse2")
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(eq_attr "alternative" "5")
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(const_string "sse4")
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]
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(const_string "*")))
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(set (attr "type")
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(cond [(eq_attr "alternative" "0,1")
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(const_string "imov")
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(eq_attr "alternative" "2")
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(const_string "sselog1")
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(eq_attr "alternative" "4,5,6,7")
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(const_string "sselog")
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]
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(const_string "ssemov")))
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(set (attr "memory")
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(cond [(eq_attr "alternative" "4,6")
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(const_string "none")
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(eq_attr "alternative" "5")
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(const_string "store")
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(eq_attr "alternative" "7")
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(const_string "load")
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]
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(const_string "*")))
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(set (attr "prefix")
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(cond [(eq_attr "alternative" "0,1")
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(const_string "orig")
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||||
]
|
||||
(const_string "maybe_vex")))
|
||||
(set (attr "mode")
|
||||
(cond [(eq_attr "alternative" "0,1")
|
||||
(const_string "HI")
|
||||
(eq_attr "alternative" "2")
|
||||
(const_string "V4SF")
|
||||
(eq_attr "alternative" "4,5,6,7")
|
||||
(const_string "TI")
|
||||
(eq_attr "alternative" "3")
|
||||
(const_string "SF")
|
||||
]
|
||||
(const_string "*")))])
|
||||
|
||||
(define_split
|
||||
[(set (match_operand 0 "any_fp_register_operand")
|
||||
(match_operand 1 "memory_operand"))]
|
||||
|
|
|
|||
|
|
@ -1102,6 +1102,7 @@ typedef _Complex float __attribute__((mode(IC))) _Complex_ibm128;
|
|||
@section Half-Precision Floating Point
|
||||
@cindex half-precision floating point
|
||||
@cindex @code{__fp16} data type
|
||||
@cindex @code{__Float16} data type
|
||||
|
||||
On ARM and AArch64 targets, GCC supports half-precision (16-bit) floating
|
||||
point via the @code{__fp16} type defined in the ARM C Language Extensions.
|
||||
|
|
@ -1150,6 +1151,18 @@ calls.
|
|||
It is recommended that portable code use the @code{_Float16} type defined
|
||||
by ISO/IEC TS 18661-3:2015. @xref{Floating Types}.
|
||||
|
||||
On x86 targets with @code{target("sse2")} and above, GCC supports half-precision
|
||||
(16-bit) floating point via the @code{_Float16} type which is defined by
|
||||
18661-3:2015. For C++, x86 provide a builtin type named @code{_Float16}
|
||||
which contains same data format as C.
|
||||
|
||||
Without @option{-mavx512fp16}, @code{_Float16} type is storage only, all
|
||||
operations will be emulated by software emulation and the @code{float}
|
||||
instructions. The default behavior for @code{FLT_EVAL_METHOD} is to keep
|
||||
the intermediate result of the operation as 32-bit precision. This may lead
|
||||
to inconsistent behavior between software emulation and AVX512-FP16
|
||||
instructions.
|
||||
|
||||
@node Decimal Float
|
||||
@section Decimal Floating Types
|
||||
@cindex decimal floating types
|
||||
|
|
|
|||
|
|
@ -992,6 +992,9 @@ lto_type_for_mode (machine_mode mode, int unsigned_p)
|
|||
return unsigned_p ? unsigned_intTI_type_node : intTI_type_node;
|
||||
#endif
|
||||
|
||||
if (float16_type_node && mode == TYPE_MODE (float16_type_node))
|
||||
return float16_type_node;
|
||||
|
||||
if (mode == TYPE_MODE (float_type_node))
|
||||
return float_type_node;
|
||||
|
||||
|
|
|
|||
12
gcc/testsuite/gcc.target/i386/float16-5.c
Normal file
12
gcc/testsuite/gcc.target/i386/float16-5.c
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-msse2 -O2" } */
|
||||
_Float16
|
||||
foo (int a)
|
||||
{
|
||||
union {
|
||||
int a;
|
||||
_Float16 b;
|
||||
}c;
|
||||
c.a = a;
|
||||
return c.b;
|
||||
}
|
||||
8
gcc/testsuite/gcc.target/i386/sse2-float16-1.c
Normal file
8
gcc/testsuite/gcc.target/i386/sse2-float16-1.c
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -mno-sse2" } */
|
||||
|
||||
_Float16/* { dg-error "is not supported on this target" } */
|
||||
foo (_Float16 x) /* { dg-error "is not supported on this target" } */
|
||||
{
|
||||
return x;
|
||||
}
|
||||
16
gcc/testsuite/gcc.target/i386/sse2-float16-2.c
Normal file
16
gcc/testsuite/gcc.target/i386/sse2-float16-2.c
Normal file
|
|
@ -0,0 +1,16 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -msse2 -mno-avx512f" } */
|
||||
|
||||
union flt
|
||||
{
|
||||
_Float16 flt;
|
||||
short s;
|
||||
};
|
||||
|
||||
_Float16
|
||||
foo (union flt x)
|
||||
{
|
||||
return x.flt;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler {(?n)pinsrw[\t ].*%xmm0} } } */
|
||||
12
gcc/testsuite/gcc.target/i386/sse2-float16-3.c
Normal file
12
gcc/testsuite/gcc.target/i386/sse2-float16-3.c
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
/* { dg-do compile } */
|
||||
/* { dg-options "-O2 -msse2 -mno-avx512f" } */
|
||||
|
||||
#include<complex.h>
|
||||
|
||||
_Complex _Float16
|
||||
foo (_Complex _Float16 x)
|
||||
{
|
||||
return x;
|
||||
}
|
||||
|
||||
/* { dg-final { scan-assembler {(?n)movd[\t ].*%xmm0} } } */
|
||||
Loading…
Add table
Reference in a new issue