haifa-sched.c (schedule-block): Reorder the inner scheduling loop to reduce duplication...
* haifa-sched.c (schedule-block): Reorder the inner scheduling loop to reduce duplication, and to achieve a slightly more logical order of operations. From-SVN: r174271
This commit is contained in:
Bernd Schmidt
Bernd Schmidt
parent
1aa9438fdb
commit
7b1ac803d3
2 changed files with 70 additions and 88 deletions
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@ -1,3 +1,9 @@
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2011-05-26 Bernd Schmidt <bernds@codesourcery.com>
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* haifa-sched.c (schedule-block): Reorder the inner scheduling loop
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to reduce duplication, and to achieve a slightly more logical order
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of operations.
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2011-05-26 Jakub Jelinek <jakub@redhat.com>
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2011-05-26 Jakub Jelinek <jakub@redhat.com>
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PR tree-optimization/49161
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PR tree-optimization/49161
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@ -3066,63 +3066,77 @@ schedule_block (basic_block *target_bb)
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}
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}
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while (advance > 0);
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while (advance > 0);
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prune_ready_list (temp_state, true);
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if (ready.n_ready > 0)
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prune_ready_list (temp_state, true);
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if (ready.n_ready == 0)
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if (ready.n_ready == 0)
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continue;
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continue;
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if (sort_p)
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{
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/* Sort the ready list based on priority. */
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ready_sort (&ready);
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if (sched_verbose >= 2)
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{
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fprintf (sched_dump, ";;\t\tReady list after ready_sort: ");
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debug_ready_list (&ready);
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}
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}
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/* We don't want md sched reorder to even see debug isns, so put
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them out right away. */
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if (ready.n_ready && DEBUG_INSN_P (ready_element (&ready, 0)))
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{
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while (ready.n_ready && DEBUG_INSN_P (ready_element (&ready, 0)))
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{
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rtx insn = ready_remove_first (&ready);
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gcc_assert (DEBUG_INSN_P (insn));
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(*current_sched_info->begin_schedule_ready) (insn);
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VEC_safe_push (rtx, heap, scheduled_insns, insn);
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last_scheduled_insn = insn;
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advance = schedule_insn (insn);
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gcc_assert (advance == 0);
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if (ready.n_ready > 0)
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ready_sort (&ready);
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}
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if (!ready.n_ready)
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continue;
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}
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/* Allow the target to reorder the list, typically for
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better instruction bundling. */
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if (sort_p && targetm.sched.reorder
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&& (ready.n_ready == 0
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|| !SCHED_GROUP_P (ready_element (&ready, 0))))
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can_issue_more =
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targetm.sched.reorder (sched_dump, sched_verbose,
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ready_lastpos (&ready),
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&ready.n_ready, clock_var);
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else
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can_issue_more = issue_rate;
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first_cycle_insn_p = true;
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first_cycle_insn_p = true;
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cycle_issued_insns = 0;
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cycle_issued_insns = 0;
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can_issue_more = issue_rate;
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for (;;)
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for (;;)
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{
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{
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rtx insn;
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rtx insn;
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int cost;
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int cost;
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bool asm_p = false;
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bool asm_p = false;
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if (sort_p && ready.n_ready > 0)
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{
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/* Sort the ready list based on priority. This must be
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done every iteration through the loop, as schedule_insn
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may have readied additional insns that will not be
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sorted correctly. */
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ready_sort (&ready);
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if (sched_verbose >= 2)
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{
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fprintf (sched_dump, ";;\t\tReady list after ready_sort: ");
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debug_ready_list (&ready);
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}
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}
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/* We don't want md sched reorder to even see debug isns, so put
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them out right away. */
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if (ready.n_ready && DEBUG_INSN_P (ready_element (&ready, 0))
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&& (*current_sched_info->schedule_more_p) ())
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{
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while (ready.n_ready && DEBUG_INSN_P (ready_element (&ready, 0)))
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{
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rtx insn = ready_remove_first (&ready);
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gcc_assert (DEBUG_INSN_P (insn));
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(*current_sched_info->begin_schedule_ready) (insn);
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VEC_safe_push (rtx, heap, scheduled_insns, insn);
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last_scheduled_insn = insn;
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advance = schedule_insn (insn);
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gcc_assert (advance == 0);
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if (ready.n_ready > 0)
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ready_sort (&ready);
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}
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}
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if (first_cycle_insn_p && !ready.n_ready)
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break;
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/* Allow the target to reorder the list, typically for
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better instruction bundling. */
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if (sort_p
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&& (ready.n_ready == 0
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|| !SCHED_GROUP_P (ready_element (&ready, 0))))
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{
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if (first_cycle_insn_p && targetm.sched.reorder)
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can_issue_more
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= targetm.sched.reorder (sched_dump, sched_verbose,
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ready_lastpos (&ready),
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&ready.n_ready, clock_var);
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else if (!first_cycle_insn_p && targetm.sched.reorder2)
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can_issue_more
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= targetm.sched.reorder2 (sched_dump, sched_verbose,
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ready.n_ready
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? ready_lastpos (&ready) : NULL,
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&ready.n_ready, clock_var);
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}
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restart_choose_ready:
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if (sched_verbose >= 2)
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if (sched_verbose >= 2)
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{
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{
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fprintf (sched_dump, ";;\tReady list (t = %3d): ",
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fprintf (sched_dump, ";;\tReady list (t = %3d): ",
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@ -3164,8 +3178,7 @@ schedule_block (basic_block *target_bb)
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/* Finish cycle. */
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/* Finish cycle. */
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break;
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break;
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if (res > 0)
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if (res > 0)
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/* Restart choose_ready (). */
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goto restart_choose_ready;
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continue;
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gcc_assert (insn != NULL_RTX);
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gcc_assert (insn != NULL_RTX);
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}
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}
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@ -3207,7 +3220,7 @@ schedule_block (basic_block *target_bb)
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insn from the split block. */
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insn from the split block. */
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{
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{
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TODO_SPEC (insn) = (TODO_SPEC (insn) & ~SPECULATIVE) | HARD_DEP;
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TODO_SPEC (insn) = (TODO_SPEC (insn) & ~SPECULATIVE) | HARD_DEP;
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continue;
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goto restart_choose_ready;
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}
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}
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/* DECISION is made. */
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/* DECISION is made. */
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@ -3256,45 +3269,8 @@ schedule_block (basic_block *target_bb)
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break;
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break;
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first_cycle_insn_p = false;
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first_cycle_insn_p = false;
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if (ready.n_ready > 0)
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if (ready.n_ready > 0)
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prune_ready_list (temp_state, false);
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prune_ready_list (temp_state, false);
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/* Sort the ready list based on priority. This must be
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redone here, as schedule_insn may have readied additional
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insns that will not be sorted correctly. */
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if (ready.n_ready > 0)
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ready_sort (&ready);
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/* Quickly go through debug insns such that md sched
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reorder2 doesn't have to deal with debug insns. */
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if (ready.n_ready && DEBUG_INSN_P (ready_element (&ready, 0))
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&& (*current_sched_info->schedule_more_p) ())
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{
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while (ready.n_ready && DEBUG_INSN_P (ready_element (&ready, 0)))
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{
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insn = ready_remove_first (&ready);
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gcc_assert (DEBUG_INSN_P (insn));
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(*current_sched_info->begin_schedule_ready) (insn);
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VEC_safe_push (rtx, heap, scheduled_insns, insn);
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advance = schedule_insn (insn);
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last_scheduled_insn = insn;
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gcc_assert (advance == 0);
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if (ready.n_ready > 0)
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ready_sort (&ready);
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}
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}
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if (targetm.sched.reorder2
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&& (ready.n_ready == 0
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|| !SCHED_GROUP_P (ready_element (&ready, 0))))
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{
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can_issue_more =
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targetm.sched.reorder2 (sched_dump, sched_verbose,
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ready.n_ready
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? ready_lastpos (&ready) : NULL,
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&ready.n_ready, clock_var);
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}
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}
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}
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}
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}
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