i386: Introduce V2QImode vectorized shifts [PR103861]
Add V2QImode shift operations and split them to synthesized double HI/LO QImode operations with integer registers. Also robustify arithmetic split patterns. 2022-01-13 Uroš Bizjak <ubizjak@gmail.com> gcc/ChangeLog: PR target/103861 * config/i386/i386.md (*ashlqi_ext<mode>_2): New insn pattern. (*<any_shiftrt:insn>qi_ext<mode>_2): Ditto. * config/i386/mmx.md (<any_shift:insn>v2qi): New insn_and_split pattern. gcc/testsuite/ChangeLog: PR target/103861 * gcc.target/i386/pr103861.c (shl,ashr,lshr): New tests.
This commit is contained in:
Uros Bizjak
parent
b0e5163960
commit
7a7d8c3f61
3 changed files with 128 additions and 4 deletions
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@ -12413,6 +12413,54 @@
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(const_string "*")))
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(set_attr "mode" "<MODE>")])
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(define_insn "*ashlqi_ext<mode>_2"
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[(set (zero_extract:SWI248
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(match_operand:SWI248 0 "register_operand" "+Q")
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(const_int 8)
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(const_int 8))
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(subreg:SWI248
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(ashift:QI
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(subreg:QI
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(zero_extract:SWI248
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(match_operand:SWI248 1 "register_operand" "0")
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(const_int 8)
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(const_int 8)) 0)
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(match_operand:QI 2 "nonmemory_operand" "cI")) 0))
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(clobber (reg:CC FLAGS_REG))]
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"/* FIXME: without this LRA can't reload this pattern, see PR82524. */
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rtx_equal_p (operands[0], operands[1])"
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{
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switch (get_attr_type (insn))
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{
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case TYPE_ALU:
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gcc_assert (operands[2] == const1_rtx);
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return "add{b}\t%h0, %h0";
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default:
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if (operands[2] == const1_rtx
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&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
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return "sal{b}\t%h0";
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else
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return "sal{b}\t{%2, %h0|%h0, %2}";
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}
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}
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[(set (attr "type")
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(cond [(and (match_test "TARGET_DOUBLE_WITH_ADD")
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(match_operand 2 "const1_operand"))
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(const_string "alu")
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]
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(const_string "ishift")))
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(set (attr "length_immediate")
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(if_then_else
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(ior (eq_attr "type" "alu")
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(and (eq_attr "type" "ishift")
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(and (match_operand 2 "const1_operand")
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(ior (match_test "TARGET_SHIFT1")
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(match_test "optimize_function_for_size_p (cfun)")))))
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(const_string "0")
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(const_string "*")))
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(set_attr "mode" "QI")])
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;; See comment above `ashl<mode>3' about how this works.
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(define_expand "<insn><mode>3"
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@ -13143,6 +13191,39 @@
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(const_string "0")
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(const_string "*")))
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(set_attr "mode" "<MODE>")])
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(define_insn "*<insn>qi_ext<mode>_2"
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[(set (zero_extract:SWI248
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(match_operand:SWI248 0 "register_operand" "+Q")
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(const_int 8)
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(const_int 8))
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(subreg:SWI248
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(any_shiftrt:QI
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(subreg:QI
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(zero_extract:SWI248
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(match_operand:SWI248 1 "register_operand" "0")
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(const_int 8)
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(const_int 8)) 0)
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(match_operand:QI 2 "nonmemory_operand" "cI")) 0))
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(clobber (reg:CC FLAGS_REG))]
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"/* FIXME: without this LRA can't reload this pattern, see PR82524. */
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rtx_equal_p (operands[0], operands[1])"
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{
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if (operands[2] == const1_rtx
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&& (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
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return "<shift>{b}\t%h0";
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else
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return "<shift>{b}\t{%2, %h0|%h0, %2}";
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}
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[(set_attr "type" "ishift")
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(set (attr "length_immediate")
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(if_then_else
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(and (match_operand 2 "const1_operand")
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(ior (match_test "TARGET_SHIFT1")
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(match_test "optimize_function_for_size_p (cfun)")))
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(const_string "0")
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(const_string "*")))
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(set_attr "mode" "QI")])
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;; Rotate instructions
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@ -1657,7 +1657,8 @@
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(neg:V2QI
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(match_operand:V2QI 1 "general_reg_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"reload_completed"
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"(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
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&& reload_completed"
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[(parallel
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[(set (strict_low_part (match_dup 0))
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(neg:QI (match_dup 1)))
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@ -1683,7 +1684,8 @@
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(neg:V2QI
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(match_operand:V2QI 1 "sse_reg_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"reload_completed"
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"(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
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&& TARGET_SSE2 && reload_completed"
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[(set (match_dup 0) (match_dup 2))
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(set (match_dup 0)
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(minus:V16QI (match_dup 0) (match_dup 1)))]
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@ -1757,7 +1759,8 @@
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(match_operand:V2QI 1 "general_reg_operand")
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(match_operand:V2QI 2 "general_reg_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"reload_completed"
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"(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
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&& reload_completed"
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[(parallel
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[(set (strict_low_part (match_dup 0))
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(plusminus:QI (match_dup 1) (match_dup 2)))
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@ -1790,7 +1793,8 @@
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(match_operand:V2QI 1 "sse_reg_operand")
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(match_operand:V2QI 2 "sse_reg_operand")))
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(clobber (reg:CC FLAGS_REG))]
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"TARGET_SSE2 && reload_completed"
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"(!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun))
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&& TARGET_SSE2 && reload_completed"
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[(set (match_dup 0)
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(plusminus:V16QI (match_dup 1) (match_dup 2)))]
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{
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@ -2387,6 +2391,38 @@
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(const_string "0")))
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(set_attr "mode" "TI")])
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(define_insn_and_split "<insn>v2qi3"
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[(set (match_operand:V2QI 0 "register_operand" "=Q")
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(any_shift:V2QI
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(match_operand:V2QI 1 "register_operand" "0")
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(match_operand:QI 2 "nonmemory_operand" "cI")))
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(clobber (reg:CC FLAGS_REG))]
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"!TARGET_PARTIAL_REG_STALL || optimize_function_for_size_p (cfun)"
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"#"
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"&& reload_completed"
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[(parallel
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[(set (zero_extract:HI (match_dup 3) (const_int 8) (const_int 8))
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(subreg:HI
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(any_shift:QI
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(subreg:QI
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(zero_extract:HI (match_dup 4)
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(const_int 8)
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(const_int 8)) 0)
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(match_dup 2)) 0))
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(clobber (reg:CC FLAGS_REG))])
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(parallel
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[(set (strict_low_part (match_dup 0))
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(any_shift:QI (match_dup 1) (match_dup 2)))
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(clobber (reg:CC FLAGS_REG))])]
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{
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operands[4] = lowpart_subreg (HImode, operands[1], V2QImode);
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operands[3] = lowpart_subreg (HImode, operands[0], V2QImode);
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operands[1] = lowpart_subreg (QImode, operands[1], V2QImode);
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operands[0] = lowpart_subreg (QImode, operands[0], V2QImode);
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}
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[(set_attr "type" "multi")
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(set_attr "mode" "QI")])
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;
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;; Parallel integral comparisons
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@ -3,6 +3,7 @@
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/* { dg-options "-O2 -dp" } */
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typedef char __v2qi __attribute__ ((__vector_size__ (2)));
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typedef unsigned char __v2qu __attribute__ ((__vector_size__ (2)));
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__v2qi and (__v2qi a, __v2qi b) { return a & b; };
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@ -20,4 +21,10 @@ __v2qi minus (__v2qi a, __v2qi b) { return a - b; };
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__v2qi neg (__v2qi a) { return -a; };
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__v2qi shl (__v2qi a, int b) { return a << b; };
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__v2qi ashr (__v2qi a, int b) { return a >> b; };
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__v2qu lshr (__v2qu a, int b) { return a >> b; };
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/* { dg-final { scan-assembler-not "insvhi" } } */
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