Handle const_vector in mulv4si3 for pre-sse4.1.
From-SVN: r188787
This commit is contained in:
Richard Henderson
Richard Henderson
parent
84ddb6810c
commit
73e9d63709
5 changed files with 106 additions and 59 deletions
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@ -1,3 +1,12 @@
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2012-06-19 Richard Henderson <rth@redhat.com>
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* config/i386/i386-protos.h (ix86_expand_sse2_mulv4si3): Declare.
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* config/i386/i386.c (ix86_expand_sse2_mulv4si3): New.
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* config/i386/predicates.md (nonimmediate_or_const_vector_operand): New.
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* config/i386/sse.md (sse2_mulv4si3): Delete.
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(mul<VI4_AVX2>3): Use ix86_expand_sse2_mulv4si3 and
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nonimmediate_or_const_vector_operand.
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2012-06-19 Richard Henderson <rth@redhat.com>
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* expmed.c (struct init_expmed_rtl): Split ...
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@ -222,6 +222,7 @@ extern void ix86_expand_reduc (rtx (*)(rtx, rtx, rtx), rtx, rtx);
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extern void ix86_expand_vec_extract_even_odd (rtx, rtx, rtx, unsigned);
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extern bool ix86_expand_pinsr (rtx *);
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extern void ix86_expand_sse2_mulv4si3 (rtx, rtx, rtx);
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/* In i386-c.c */
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extern void ix86_target_macros (void);
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@ -38438,6 +38438,82 @@ ix86_expand_vec_extract_even_odd (rtx targ, rtx op0, rtx op1, unsigned odd)
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expand_vec_perm_even_odd_1 (&d, odd);
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}
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void
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ix86_expand_sse2_mulv4si3 (rtx op0, rtx op1, rtx op2)
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{
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rtx op1_m1, op1_m2;
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rtx op2_m1, op2_m2;
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rtx res_1, res_2;
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/* Shift both input vectors down one element, so that elements 3
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and 1 are now in the slots for elements 2 and 0. For K8, at
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least, this is faster than using a shuffle. */
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op1_m1 = op1 = force_reg (V4SImode, op1);
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op1_m2 = gen_reg_rtx (V4SImode);
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emit_insn (gen_sse2_lshrv1ti3 (gen_lowpart (V1TImode, op1_m2),
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gen_lowpart (V1TImode, op1),
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GEN_INT (32)));
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if (GET_CODE (op2) == CONST_VECTOR)
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{
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rtvec v;
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/* Constant propagate the vector shift, leaving the dont-care
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vector elements as zero. */
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v = rtvec_alloc (4);
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RTVEC_ELT (v, 0) = CONST_VECTOR_ELT (op2, 0);
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RTVEC_ELT (v, 2) = CONST_VECTOR_ELT (op2, 2);
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RTVEC_ELT (v, 1) = const0_rtx;
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RTVEC_ELT (v, 3) = const0_rtx;
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op2_m1 = gen_rtx_CONST_VECTOR (V4SImode, v);
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op2_m1 = force_reg (V4SImode, op2_m1);
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v = rtvec_alloc (4);
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RTVEC_ELT (v, 0) = CONST_VECTOR_ELT (op2, 1);
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RTVEC_ELT (v, 2) = CONST_VECTOR_ELT (op2, 3);
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RTVEC_ELT (v, 1) = const0_rtx;
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RTVEC_ELT (v, 3) = const0_rtx;
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op2_m2 = gen_rtx_CONST_VECTOR (V4SImode, v);
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op2_m2 = force_reg (V4SImode, op2_m2);
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}
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else
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{
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op2_m1 = op2 = force_reg (V4SImode, op2);
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op2_m2 = gen_reg_rtx (V4SImode);
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emit_insn (gen_sse2_lshrv1ti3 (gen_lowpart (V1TImode, op2_m2),
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gen_lowpart (V1TImode, op2),
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GEN_INT (32)));
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}
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/* Widening multiply of elements 0+2, and 1+3. */
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res_1 = gen_reg_rtx (V4SImode);
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res_2 = gen_reg_rtx (V4SImode);
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emit_insn (gen_sse2_umulv2siv2di3 (gen_lowpart (V2DImode, res_1),
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op1_m1, op2_m1));
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emit_insn (gen_sse2_umulv2siv2di3 (gen_lowpart (V2DImode, res_2),
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op1_m2, op2_m2));
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/* Move the results in element 2 down to element 1; we don't care
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what goes in elements 2 and 3. Then we can merge the parts
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back together with an interleave.
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Note that two other sequences were tried:
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(1) Use interleaves at the start instead of psrldq, which allows
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us to use a single shufps to merge things back at the end.
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(2) Use shufps here to combine the two vectors, then pshufd to
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put the elements in the correct order.
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In both cases the cost of the reformatting stall was too high
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and the overall sequence slower. */
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emit_insn (gen_sse2_pshufd_1 (res_1, res_1, const0_rtx, const2_rtx,
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const0_rtx, const0_rtx));
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emit_insn (gen_sse2_pshufd_1 (res_2, res_2, const0_rtx, const2_rtx,
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const0_rtx, const0_rtx));
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res_1 = emit_insn (gen_vec_interleave_lowv4si (op0, res_1, res_2));
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set_unique_reg_note (res_1, REG_EQUAL, gen_rtx_MULT (V4SImode, op1, op2));
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}
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/* Expand an insert into a vector register through pinsr insn.
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Return true if successful. */
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@ -816,6 +816,13 @@
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return false;
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})
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;; Return true when OP is a nonimmediate or a vector constant. Note
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;; that most vector constants are not legitimate operands, so we need
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;; to special-case this.
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(define_predicate "nonimmediate_or_const_vector_operand"
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(ior (match_code "const_vector")
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(match_operand 0 "nonimmediate_operand")))
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;; Return true if OP is a register or a zero.
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(define_predicate "reg_or_0_operand"
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(ior (match_operand 0 "register_operand")
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@ -5610,12 +5610,22 @@
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(define_expand "mul<mode>3"
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[(set (match_operand:VI4_AVX2 0 "register_operand")
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(mult:VI4_AVX2 (match_operand:VI4_AVX2 1 "register_operand")
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(match_operand:VI4_AVX2 2 "register_operand")))]
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(mult:VI4_AVX2
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(match_operand:VI4_AVX2 1 "nonimmediate_operand")
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(match_operand:VI4_AVX2 2 "nonimmediate_or_const_vector_operand")))]
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"TARGET_SSE2"
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{
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if (TARGET_SSE4_1 || TARGET_AVX)
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ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);
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{
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if (CONSTANT_P (operands[2]))
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operands[2] = force_const_mem (<MODE>mode, operands[2]);
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ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);
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}
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else
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{
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ix86_expand_sse2_mulv4si3 (operands[0], operands[1], operands[2]);
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DONE;
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}
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})
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(define_insn "*<sse4_1_avx2>_mul<mode>3"
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@ -5633,62 +5643,6 @@
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(set_attr "prefix" "orig,vex")
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(set_attr "mode" "<sseinsnmode>")])
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(define_insn_and_split "*sse2_mulv4si3"
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[(set (match_operand:V4SI 0 "register_operand")
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(mult:V4SI (match_operand:V4SI 1 "register_operand")
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(match_operand:V4SI 2 "register_operand")))]
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"TARGET_SSE2 && !TARGET_SSE4_1 && !TARGET_AVX
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&& can_create_pseudo_p ()"
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"#"
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"&& 1"
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[(const_int 0)]
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{
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rtx t1, t2, t3, t4, t5, t6, thirtytwo;
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rtx op0, op1, op2;
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op0 = operands[0];
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op1 = operands[1];
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op2 = operands[2];
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t1 = gen_reg_rtx (V4SImode);
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t2 = gen_reg_rtx (V4SImode);
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t3 = gen_reg_rtx (V4SImode);
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t4 = gen_reg_rtx (V4SImode);
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t5 = gen_reg_rtx (V4SImode);
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t6 = gen_reg_rtx (V4SImode);
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thirtytwo = GEN_INT (32);
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/* Multiply elements 2 and 0. */
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emit_insn (gen_sse2_umulv2siv2di3 (gen_lowpart (V2DImode, t1),
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op1, op2));
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/* Shift both input vectors down one element, so that elements 3
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and 1 are now in the slots for elements 2 and 0. For K8, at
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least, this is faster than using a shuffle. */
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emit_insn (gen_sse2_lshrv1ti3 (gen_lowpart (V1TImode, t2),
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gen_lowpart (V1TImode, op1),
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thirtytwo));
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emit_insn (gen_sse2_lshrv1ti3 (gen_lowpart (V1TImode, t3),
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gen_lowpart (V1TImode, op2),
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thirtytwo));
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/* Multiply elements 3 and 1. */
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emit_insn (gen_sse2_umulv2siv2di3 (gen_lowpart (V2DImode, t4),
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t2, t3));
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/* Move the results in element 2 down to element 1; we don't care
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what goes in elements 2 and 3. */
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emit_insn (gen_sse2_pshufd_1 (t5, t1, const0_rtx, const2_rtx,
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const0_rtx, const0_rtx));
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emit_insn (gen_sse2_pshufd_1 (t6, t4, const0_rtx, const2_rtx,
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const0_rtx, const0_rtx));
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/* Merge the parts back together. */
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emit_insn (gen_vec_interleave_lowv4si (op0, t5, t6));
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set_unique_reg_note (get_last_insn (), REG_EQUAL,
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gen_rtx_MULT (V4SImode, operands[1], operands[2]));
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DONE;
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})
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(define_insn_and_split "mul<mode>3"
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[(set (match_operand:VI8_AVX2 0 "register_operand")
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(mult:VI8_AVX2 (match_operand:VI8_AVX2 1 "register_operand")
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