RISC-V: Remove masking third operand of rotate instructions
Rotate instructions do not need to mask the third operand.
For example, RV64 the following code:
unsigned long foo1(unsigned long rs1, unsigned long rs2)
{
long shamt = rs2 & (64 - 1);
return (rs1 << shamt) | (rs1 >> ((64 - shamt) & (64 - 1)));
}
Compiles to:
foo1:
andi a1,a1,63
rol a0,a0,a1
ret
This patch removes unnecessary masking.
Besides, I have merged masking insns for shifts that were written before.
gcc/ChangeLog:
* config/riscv/riscv.md (*<optab><GPR:mode>3_mask): New pattern,
combined from ...
(*<optab>si3_mask, *<optab>di3_mask): Here.
(*<optab>si3_mask_1, *<optab>di3_mask_1): And here.
* config/riscv/bitmanip.md (*<bitmanip_optab><GPR:mode>3_mask): New
pattern.
(*<bitmanip_optab>si3_sext_mask): Likewise.
* config/riscv/iterators.md (shiftm1): Use const_si_mask_operand
and const_di_mask_operand.
(bitmanip_rotate): New iterator.
(bitmanip_optab): Add rotates.
* config/riscv/predicates.md (const_si_mask_operand): Renamed
from const31_operand. Generalize to handle more mask constants.
(const_di_mask_operand): Similarly.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/shift-and-2.c: Fixed test
* gcc.target/riscv/zbb-rol-ror-01.c: New test
* gcc.target/riscv/zbb-rol-ror-02.c: New test
* gcc.target/riscv/zbb-rol-ror-03.c: New test
* gcc.target/riscv/zbb-rol-ror-04.c: New test
* gcc.target/riscv/zbb-rol-ror-05.c: New test
* gcc.target/riscv/zbb-rol-ror-06.c: New test
* gcc.target/riscv/zbb-rol-ror-07.c: New test
This commit is contained in:
Jivan Hakobyan
Jeff Law
parent
98827c53ed
commit
6da6ed95c9
12 changed files with 75 additions and 111 deletions
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@ -351,6 +351,42 @@
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"rolw\t%0,%1,%2"
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[(set_attr "type" "bitmanip")])
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(define_insn_and_split "*<bitmanip_optab><GPR:mode>3_mask"
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[(set (match_operand:GPR 0 "register_operand" "= r")
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(bitmanip_rotate:GPR
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(match_operand:GPR 1 "register_operand" " r")
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(match_operator 4 "subreg_lowpart_operator"
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[(and:GPR2
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(match_operand:GPR2 2 "register_operand" "r")
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(match_operand 3 "<GPR:shiftm1>" "<GPR:shiftm1p>"))])))]
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"TARGET_ZBB || TARGET_ZBKB"
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"#"
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"&& 1"
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[(set (match_dup 0)
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(bitmanip_rotate:GPR (match_dup 1)
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(match_dup 2)))]
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"operands[2] = gen_lowpart (QImode, operands[2]);"
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[(set_attr "type" "bitmanip")
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(set_attr "mode" "<GPR:MODE>")])
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(define_insn_and_split "*<bitmanip_optab>si3_sext_mask"
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[(set (match_operand:DI 0 "register_operand" "= r")
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(sign_extend:DI (bitmanip_rotate:SI
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(match_operand:SI 1 "register_operand" " r")
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(match_operator 4 "subreg_lowpart_operator"
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[(and:GPR
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(match_operand:GPR 2 "register_operand" "r")
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(match_operand 3 "const_si_mask_operand"))]))))]
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"TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
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"#"
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"&& 1"
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[(set (match_dup 0)
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(sign_extend:DI (bitmanip_rotate:SI (match_dup 1)
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(match_dup 2))))]
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"operands[2] = gen_lowpart (QImode, operands[2]);"
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[(set_attr "type" "bitmanip")
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(set_attr "mode" "DI")])
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;; orc.b (or-combine) is added as an unspec for the benefit of the support
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;; for optimized string functions (such as strcmp).
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(define_insn "orcb<mode>2"
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@ -117,7 +117,7 @@
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(define_mode_attr HALFMODE [(DF "SI") (DI "SI") (TF "DI")])
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; bitmanip mode attribute
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(define_mode_attr shiftm1 [(SI "const31_operand") (DI "const63_operand")])
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(define_mode_attr shiftm1 [(SI "const_si_mask_operand") (DI "const_di_mask_operand")])
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(define_mode_attr shiftm1p [(SI "DsS") (DI "DsD")])
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;; -------------------------------------------------------------------
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@ -174,6 +174,8 @@
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(define_code_iterator clz_ctz_pcnt [clz ctz popcount])
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(define_code_iterator bitmanip_rotate [rotate rotatert])
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;; -------------------------------------------------------------------
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;; Code Attributes
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;; -------------------------------------------------------------------
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@ -271,7 +273,9 @@
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(umax "umax")
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(clz "clz")
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(ctz "ctz")
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(popcount "popcount")])
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(popcount "popcount")
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(rotate "rotl")
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(rotatert "rotr")])
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(define_code_attr bitmanip_insn [(smin "min")
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(smax "max")
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(umin "minu")
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@ -235,13 +235,15 @@
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(and (match_code "const_int")
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(match_test "SINGLE_BIT_MASK_OPERAND (~UINTVAL (op))")))
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(define_predicate "const31_operand"
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(define_predicate "const_si_mask_operand"
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(and (match_code "const_int")
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(match_test "INTVAL (op) == 31")))
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(match_test "(INTVAL (op) & (GET_MODE_BITSIZE (SImode) - 1))
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== GET_MODE_BITSIZE (SImode) - 1")))
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(define_predicate "const63_operand"
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(define_predicate "const_di_mask_operand"
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(and (match_code "const_int")
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(match_test "INTVAL (op) == 63")))
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(match_test "(INTVAL (op) & (GET_MODE_BITSIZE (DImode) - 1))
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== GET_MODE_BITSIZE (DImode) - 1")))
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(define_predicate "imm5_operand"
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(and (match_code "const_int")
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@ -2048,45 +2048,6 @@
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[(set_attr "type" "shift")
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(set_attr "mode" "SI")])
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(define_insn_and_split "*<optab>si3_mask"
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[(set (match_operand:SI 0 "register_operand" "= r")
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(any_shift:SI
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(match_operand:SI 1 "register_operand" " r")
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(match_operator 4 "subreg_lowpart_operator"
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[(and:SI
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(match_operand:SI 2 "register_operand" "r")
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(match_operand 3 "const_int_operand"))])))]
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"(INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
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== GET_MODE_BITSIZE (SImode)-1"
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"#"
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"&& 1"
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[(set (match_dup 0)
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(any_shift:SI (match_dup 1)
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(match_dup 2)))]
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"operands[2] = gen_lowpart (QImode, operands[2]);"
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[(set_attr "type" "shift")
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(set_attr "mode" "SI")])
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(define_insn_and_split "*<optab>si3_mask_1"
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[(set (match_operand:SI 0 "register_operand" "= r")
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(any_shift:SI
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(match_operand:SI 1 "register_operand" " r")
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(match_operator 4 "subreg_lowpart_operator"
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[(and:DI
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(match_operand:DI 2 "register_operand" "r")
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(match_operand 3 "const_int_operand"))])))]
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"TARGET_64BIT
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&& (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
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== GET_MODE_BITSIZE (SImode)-1"
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"#"
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"&& 1"
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[(set (match_dup 0)
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(any_shift:SI (match_dup 1)
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(match_dup 2)))]
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"operands[2] = gen_lowpart (QImode, operands[2]);"
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[(set_attr "type" "shift")
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(set_attr "mode" "SI")])
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(define_insn "<optab>di3"
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[(set (match_operand:DI 0 "register_operand" "= r")
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(any_shift:DI
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@ -2103,45 +2064,23 @@
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[(set_attr "type" "shift")
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(set_attr "mode" "DI")])
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(define_insn_and_split "*<optab>di3_mask"
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[(set (match_operand:DI 0 "register_operand" "= r")
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(any_shift:DI
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(match_operand:DI 1 "register_operand" " r")
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(define_insn_and_split "*<optab><GPR:mode>3_mask_1"
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[(set (match_operand:GPR 0 "register_operand" "= r")
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(any_shift:GPR
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(match_operand:GPR 1 "register_operand" " r")
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(match_operator 4 "subreg_lowpart_operator"
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[(and:SI
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(match_operand:SI 2 "register_operand" "r")
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(match_operand 3 "const_int_operand"))])))]
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"TARGET_64BIT
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&& (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
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== GET_MODE_BITSIZE (DImode)-1"
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[(and:GPR2
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(match_operand:GPR2 2 "register_operand" "r")
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(match_operand 3 "<GPR:shiftm1>"))])))]
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""
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"#"
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"&& 1"
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[(set (match_dup 0)
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(any_shift:DI (match_dup 1)
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(any_shift:GPR (match_dup 1)
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(match_dup 2)))]
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"operands[2] = gen_lowpart (QImode, operands[2]);"
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[(set_attr "type" "shift")
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(set_attr "mode" "DI")])
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(define_insn_and_split "*<optab>di3_mask_1"
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[(set (match_operand:DI 0 "register_operand" "= r")
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(any_shift:DI
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(match_operand:DI 1 "register_operand" " r")
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(match_operator 4 "subreg_lowpart_operator"
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[(and:DI
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(match_operand:DI 2 "register_operand" "r")
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(match_operand 3 "const_int_operand"))])))]
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"TARGET_64BIT
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&& (INTVAL (operands[3]) & (GET_MODE_BITSIZE (DImode)-1))
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== GET_MODE_BITSIZE (DImode)-1"
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"#"
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"&& 1"
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[(set (match_dup 0)
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(any_shift:DI (match_dup 1)
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(match_dup 2)))]
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"operands[2] = gen_lowpart (QImode, operands[2]);"
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[(set_attr "type" "shift")
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(set_attr "mode" "DI")])
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(set_attr "mode" "<GPR:MODE>")])
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(define_insn "*<optab>si3_extend"
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[(set (match_operand:DI 0 "register_operand" "= r")
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@ -2164,34 +2103,10 @@
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(any_shift:SI
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(match_operand:SI 1 "register_operand" " r")
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(match_operator 4 "subreg_lowpart_operator"
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[(and:SI
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(match_operand:SI 2 "register_operand" " r")
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(match_operand 3 "const_int_operand"))]))))]
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"TARGET_64BIT
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&& (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
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== GET_MODE_BITSIZE (SImode)-1"
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"#"
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"&& 1"
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[(set (match_dup 0)
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(sign_extend:DI
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(any_shift:SI (match_dup 1)
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(match_dup 2))))]
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"operands[2] = gen_lowpart (QImode, operands[2]);"
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[(set_attr "type" "shift")
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(set_attr "mode" "SI")])
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(define_insn_and_split "*<optab>si3_extend_mask_1"
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[(set (match_operand:DI 0 "register_operand" "= r")
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(sign_extend:DI
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(any_shift:SI
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(match_operand:SI 1 "register_operand" " r")
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(match_operator 4 "subreg_lowpart_operator"
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[(and:DI
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(match_operand:DI 2 "register_operand" " r")
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(match_operand 3 "const_int_operand"))]))))]
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"TARGET_64BIT
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&& (INTVAL (operands[3]) & (GET_MODE_BITSIZE (SImode)-1))
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== GET_MODE_BITSIZE (SImode)-1"
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[(and:GPR
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(match_operand:GPR 2 "register_operand" " r")
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(match_operand 3 "const_si_mask_operand"))]))))]
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"TARGET_64BIT"
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"#"
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"&& 1"
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[(set (match_dup 0)
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@ -11,10 +11,10 @@ sub2 (int i, long j)
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}
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/* Test for <optab>si3_extend_mask. */
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unsigned long
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sub3 (int mask)
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int
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sub3 (short mask)
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{
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return 1 << (mask & 0xff);
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return 1 << ((int)mask & 0x1f);
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}
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/* Test for <optab>si3_extend_mask_1. */
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@ -14,4 +14,5 @@ unsigned long foo2(unsigned long rs1, unsigned long rs2)
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}
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/* { dg-final { scan-assembler-times "rol" 2 } } */
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/* { dg-final { scan-assembler-times "ror" 2 } } */
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/* { dg-final { scan-assembler-times "ror" 2 } } */
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/* { dg-final { scan-assembler-not "and" } } */
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@ -14,4 +14,5 @@ unsigned int foo2(unsigned int rs1, unsigned int rs2)
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}
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/* { dg-final { scan-assembler-times "rol" 2 } } */
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/* { dg-final { scan-assembler-times "ror" 2 } } */
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/* { dg-final { scan-assembler-times "ror" 2 } } */
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/* { dg-final { scan-assembler-not {and} { target { no-opts "-O0" } } } } */
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@ -15,4 +15,5 @@ unsigned int ror(unsigned int rs1, unsigned int rs2)
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}
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/* { dg-final { scan-assembler-times "rolw" 1 } } */
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/* { dg-final { scan-assembler-times "rorw" 1 } } */
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/* { dg-final { scan-assembler-times "rorw" 1 } } */
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/* { dg-final { scan-assembler-not "and" } } */
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@ -2,6 +2,7 @@
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/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */
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/* { dg-skip-if "" { *-*-* } { "-g" } } */
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/* { dg-final { check-function-bodies "**" "" } } */
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/* { dg-final { scan-assembler-not "and" } } */
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/*
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**foo1:
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@ -2,6 +2,7 @@
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/* { dg-options "-march=rv32gc_zbb -mabi=ilp32 -fno-lto -O2" } */
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/* { dg-skip-if "" { *-*-* } { "-g" } } */
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/* { dg-final { check-function-bodies "**" "" } } */
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/* { dg-final { scan-assembler-not "and" } } */
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/*
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**foo1:
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@ -2,6 +2,7 @@
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/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */
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/* { dg-skip-if "" { *-*-* } { "-g" } } */
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/* { dg-final { check-function-bodies "**" "" } } */
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/* { dg-final { scan-assembler-not "and" } } */
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/*
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**foo1:
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@ -2,6 +2,7 @@
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/* { dg-options "-march=rv64gc_zbb -mabi=lp64d -fno-lto -O2" } */
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/* { dg-skip-if "" { *-*-* } { "-g" } } */
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/* { dg-final { check-function-bodies "**" "" } } */
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/* { dg-final { scan-assembler-not "and" } } */
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/*
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**foo1:
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